WO2002071476A2

WO2002071476A2 - Method of forming conductive interconnections in porous insulating films and associated device

Info

Publication number: WO2002071476A2
Application number: PCT/US2002/003945
Authority: WO
Inventors: John G. Pellerin; Derick J. Wristers
Original assignee: Advanced Micro Devices, Inc.
Priority date: 2001-03-06
Filing date: 2002-02-01
Publication date: 2002-09-12
Also published as: WO2002071476A3

Abstract

The integrated circuit device disclosed herein comprises an insulating layer (32) comprised of a first insulating material that has an opening (36) formed therein as defined by at least one sidewall (36A), at least one sidewall spacer (40) positioned adjacent the sidewall (36A) of the opening (36), the sidewall spacer (40) being comprised of a second insulating material, and a conductive interconnection (42) formed in the opening (36) in the insulating layer (32). In a further embodiment, the first insulating material has a dielectric constant less than approximately 3, and a density less than approximately 1.2 grams/cc, whereas the second insulating material has a dielectric constant less than approximately 7 and a density less than approximately 3 grams/cc. The method disclosed herein comprises forming an opening (36) in a first layer (32) of a first insulating material, the opening (36) being defined by at least one sidewall (36A), and conformally depositing a second layer (38) comprised of a second insulating material in the opening (36) above the sidewall (36A). The method further comprises performing an anisotropic etching process on the second layer to define a sidewall spacer (40) comprised of the second insulating material positioned adjacent the sidewall (36A) of the opening (36), and forming a conductive interconnection (42) in the opening (36) in the insulating layer (32) between the sidewall spacer (40).

Description

METHOD OF FORMING CONDUCTIVE INTERCONNECTIONS IN POROUS INSULATING

FILMS AND ASSOCIATED DEVICE

TECHNICAL FIELD The present invention is generally directed to the field of semiconductor manufacturing, and, more particularly, to a method of forming conductive interconnections, e.g., conductive lines and plugs, in an opening in a porous insulating layer, and the resulting semiconductor device.

BACKGROUND ART There is a constant drive to reduce the size, or scale, of transistors to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. A conventional integrated circuit device, such as a microprocessor, is typically comprised of millions of transistors formed within the surface of a semiconducting substrate. For the integrated circuit device to function, the transistors must be electrically connected to one another through conductive interconnections, i.e., conductive lines and plugs.

Many modern integrated circuit devices are very densely packed, i.e., there is very little space between the transistors formed above the substrate. Thus, these conductive interconnections must be made in multiple layers to conserve plot space on the semiconducting substrate. This is typically accomplished through the formation of alternating layers of conductive lines and conductive plugs (sometimes referred to as contacts or vias) formed in layers of insulating materials formed on the device. As is readily apparent to those skilled in the art, the conductive plugs are means by which various layers of conductive lines, and/or semiconductor devices, may be electrically coupled to one another. The conductive lines and plugs may be comprised of a variety of conductive materials, such as copper, aluminum, metal alloys, titanium, tantalum, titanium nitride, tantalum nitride, tungsten, etc.

One illustrative prior art process flow for forming such conductive interconnections will now be described with reference to Figures 1 and 2. As shown therein, a layer of insulating material 10, e.g., silicon dioxide, may be formed above a transistor 11 that was previously formed above a semiconducting substrate 13 in an area between trench isolation regions 17. Alternatively, although not depicted in the figures, the layer of insulating material 10 may be formed above a previously formed layer of insulating material (not shown) having conductive interconnections, e.g., conductive lines, formed therein. Another layer 25 comprised of, for example, silicon nitride, may then be formed above the insulating material 10. Next, an opening 12, defined by sidewalls 14, is formed in the insulating material 10. The opening 12 depicted in the figures is formed above one of the source/drain regions 15 of the transistor 11, and a conductive interconnection 19 (see Figure 2), i.e., a conductive plug, will be formed in the opening 12 and contacted to the source/drain region 15.

Thereafter, a barrier metal layer 16 is formed above the surface 25 A of the layer 25 and in the opening 12. The barrier metal layer 16 may be comprised of a material sufficient to serve its intended function, e.g., preventing or reducing migration of material that will comprise the conductive interconnection 19 into unwanted areas of the insulating material 10. The barrier metal layer 16 may be comprised of a variety of materials, e.g., tantalum, tantalum nitride, titanium, titanium nitride, etc. In some situations, the barrier metal layer 16 may be comprised of two or more layers of material, e.g., a titanium/titanium nitride bi-layer, although that is not depicted in Figure 1. Thereafter, in the case where the conductive line or plug to be formed in the opening 12 is comprised of copper, a copper seed layer 19 may be formed above an upper surface 16A of the barrier metal layer 16 by PVD, CVD or electroplating. Copper may then be formed above the copper seed layer 19 and in the opening 12 by using known electroplating techniques. In the situation where the conductive line or plug is comprised of another material, e.g., tungsten, the copper seed layer 19 would not be required. Rather, in that situation, a layer of the appropriate material, e.g., tungsten, would be blanket-deposited above the barrier metal layer 16 in the opening 12. If desired, a layer of adhesion material (not shown) may also be formed above the barrier metal layer 16 prior to depositing the metal layer.

Next, one or more chemical mechanical polishing ("CMP") operations are performed to remove portions of the conductive material, e.g., copper, tungsten, etc., and the barrier metal layer 16 lying outside of the opening 12 above the surface 25A of the layer 25 to define the conductive interconnection 19, e.g., a line or plug, in the opening 12, as shown in Figure 2. Typically, in the case of conductive interconnections comprised of copper, one or two CMP processes will be performed to remove substantially all of the copper, and an additional CMP operation will be performed to remove portions of the barrier metal layer 16 lying above the surface 25 A of the layer 25.

However, as stated previously, modern integrated circuit devices are becoming more densely packed, i.e., devices are being built closer and closer to one another. Similarly, conductive interconnections, e.g., conductive lines and plugs, are also formed closer and closer to one another. As a result, the capacitive coupling between adjacent conductive interconnections becomes greater. This increased capacitive coupling is problematic in that it slows the operating speed of the integrated circuit device, may lead to signal "cross-talk" or interference, and it increases the amount of power consumed by the device, both of which are undesirable characteristics of modern integrated circuit devices.

One technique for attempting to reduce this capacitive coupling is to increase the spacing between conductive interconnections, i.e., to increase the distance between conductive lines. However, as stated previously, due to the constant drive to increase the packing density of integrated circuit devices, this option is at best difficult, and sometimes completely foreclosed by the nature of the design of the integrated circuit. Another alternative is to reduce the dielectric constant ("k") of the insulating material positioned between adjacent conductive interconnections. That is, all other things being equal, the lower the dielectric constant of the material between the adjacent conductive interconnections, e.g., conductive lines, the less the capacitive coupling between those lines. Thus, there is a drive in the semiconductor industry to continually produce insulating materials with decreasing dielectric constants in order to minimize some of the capacitive coupling problems described above. These are generally referred to in the industry as so-called "low-k" materials, and they generally have a dielectric constant less than approximately 3. Examples of such materials include hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), aerogels, xerogels, SiC_xOH_y, SiLK (Dow Chemical), CORAL (Novellus), Black Diamond (Applied Materials), CVD-deposited methyl silanes, etc.

However, these low-k type materials tend to be very porous, i.e., they tend to have a density on the order of 1.2 grams/cc or less. This low density is problematic in that it may be conducive to the diffusion of metal atoms from both the barrier metal layer 16 and the conductive interconnection 19 into the porous insulating material layer 10. Such diffusion of metal atoms into the insulating material layer 10 can lead to excessive leakage currents between other conductive interconnections, e.g., adjacent conductive lines, and a general breakdown of the insulating characteristics of the insulating material layer 10. Another problem that may result from the use of such porous/low-k dielectric materials is that openings formed in such materials, such as the opening 12 depicted in Figures 1 and 2, have relatively rough sidewalls due to the porous nature of the insulating material. This may create problems in filling the opening with an appropriate conductive metal, i.e., voids or seams may be created. Also, low density or porous dielectric are more prone to chemical- or plasma-induced degradation of dielectric constant and/or other physical properties, e.g., moisture resistance, densification, optical property changes, etc.

The present invention is directed to solving, or at least reducing, some or all of the aforementioned problems. DISCLOSURE OF INVENTION

The present invention is directed to a novel integrated circuit device, and a method of making same. In one illustrative embodiment, the integrated circuit device has an insulating layer comprised of a first insulating material, the layer has an opening formed therein as defined by at least one sidewall. The device further comprises at least one sidewall spacer positioned adjacent the sidewall of the opening, the sidewall spacer being comprised of a second insulating material, and a conductive interconnection formed in the opening in the insulating layer. In further embodiments of the present inventions, the first insulating material has a dielectric constant less than approximately 3, and a density less than approximately 1.2 grams/cc, whereas the second insulating material has a dielectric constant less than approximately 7 and a density less than approximately 3 grams/cc. In one illustrative embodiment, the method disclosed herein comprises forming an opening in a first layer of a first insulating material, the opening being defined by at least one sidewall, and conformally depositing a second layer comprised of a second insulating material in the opening above the sidewall. The method further comprises performing an anisotropic etching process on the second layer to define a sidewall spacer comprised of the second insulating material positioned adjacent the sidewall of the opening, and forming a conductive interconnection in the opening in the insulating layer between the sidewall spacer.

BRIEF DESCRIPTION OF THE DRAWINGS The invention may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:

Figure 1 is a cross-sectional view of a portion of an integrated circuit device with an insulating layer having an opening for a conductive interconnection formed therein in accordance with prior art processing techniques;

Figure 2 is a cross-sectional view of the device shown in Figure 1 with a conductive interconnection formed in the opening;

Figure 3 is a cross-sectional view of a portion of an integrated circuit device having a layer of insulating material formed thereabove;

Figure 4 is the device depicted in Figure 3 wherein the insulating layer has an opening for a conductive interconnection formed therein;

Figure 5 is the device depicted in Figure 4 with a conformal layer of dielectric material formed thereabove; Figure 6 is the device depicted in Figure 5 after an anisotropic etching process has been performed to define a sidewall spacer comprised of the dielectric material in the opening in the insulating layer;

Figure 7 is a depiction of the device shown in Figure 6 after a conductive interconnection has been formed in the opening in the insulating layer between the sidewall spacer; and Figures 8-12 depict an illustrative embodiment of the present invention in the context of a dual damascene process flow.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

MODE(S) FOR CARRYING OUT THE INVENTION

Illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

The present invention will now be described with reference to the attached figures. Although the various regions and structures of a semiconductor device are depicted in the drawings as having very precise, sharp configurations and profiles, those skilled in the art recognize that, in reality, these regions and structures are not as precise as indicated in the drawings. Additionally, the relative sizes of the various features depicted in the drawings may be exaggerated or reduced as compared to the size of those feature sizes on fabricated devices. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present invention.

In general, the present invention is directed to a method of forming conductive interconnections in porous dielectric films and an associated device. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the present method is applicable to a variety of technologies, e.g.,

NMOS, PMOS, CMOS, etc., and is readily applicable to a variety of devices, including, but not limited to, logic devices, memory devices, etc. Moreover, the present invention may be used with a variety of combinations of insulating materials, barrier metal materials and conductive materials.

As shown in Figure 3, an insulating layer 32 is formed above a substrate 30 and a dielectric cap layer 34 is formed above the insulating layer 32. The insulating layer 32 may be positioned above a transistor (not shown) that was previously formed above the semiconducting substrate 30, or it may be formed above a previously formed layer of insulating material (not shown) having conductive interconnections, e.g., conductive lines or plugs, formed therein. That is, the present invention may be used in the context of forming any of a vast variety of conductive interconnections on an integrated circuit device. For example, the present invention may be used to form conductive contacts to underlying semiconductor devices, to form conductive lines at any level of an integrated circuit device, and or to form conductive vias between conductive lines. Thus, the particular embodiments of the invention depicted in the attached drawings should not be considered a limitation of the invention unless such limitations are specifically recited in the appended claims.

The insulating layer 32 may be comprised of a variety of insulating materials having a dielectric constant less than approximately 3, i.e., so-called low-k dielectrics. For example, the insulating layer 32 may be comprised of HSQ, MSQ, hydroxylated silicon carbides (SiC_x(OH_y)), polymeric dielectrics, such as SILK^® (sold by Dow Chemical), mesoporous silica, aerogels, xerogels, etc. The insulating layer 32 may be formed by a variety of techniques, such as chemical vapor deposition ("CVD"), spin-coating, sputtering, etc. Moreover, the insulating layer 32 may have a variety of thicknesses. In one illustrative embodiment, the insulating layer 32 may have a thickness ranging from approximately 0.2-1.0nm (2000-10000 A). Thus, the particular materials of construction of the insulating layer 32, and the manner in which it is made, should not be considered a limitation of the present invention unless specifically set forth in the appended claims.

The dielectric cap layer 34 may be formed above the insulating layer 32 for a variety of purposes, e.g., to serve as an etch-stop layer. The dielectric cap layer 34 may also be comprised of a variety of materials, e.g., silicon nitride, silicon oxynitride, silicon carbide, an oxide, an oxynitride, etc., and it may be formed using a variety of techniques, e.g., CVD, physical vapor deposition ("PVD"), etc. In one illustrative embodiment, the dielectric cap layer 34 is comprised of approximately 200-800 A of silicon nitride that is formed by a CVD process.

Thereafter, as shown in Figure 4, an opening 36 is formed in the insulating layer 32 using known photolithographic and etching processes. The opening 36 is defined by sidewalls 36 A. The opening 36 may be formed by performing one or more etching processes, such as reactive ion etching processes. For example, a first etching process may be performed to etch through the dielectric cap layer 34, and, thereafter, a second etching process may be performed to form the opening 36 in the insulating layer 32.

The dimensions and shape of the opening 36 may be varied as a matter of design choice depending upon the structure ultimately to be formed in the opening 36, e.g., a conductive line or a conductive plug. For example, in the case where a conductive line will be formed in the opening 36, the opening 36 is essentially a trench that may be routed as desired above the substrate 30. In situations where a conductive contact or via will be formed in the opening 36, the opening 36 may have a circular, square, oval or rectangular cross-sectional configuration when viewed from above. Irrespective of its shape, e.g., circular, rectangular, etc., the opening 36 should be understood to be defined by at least one sidewall. Thus, the particular size, shape or configuration of the opening 36 should not be considered a limitation of the present invention unless it is specifically set forth in the appended claims.

Next, as shown in Figure 5, a second layer of insulating material 38 is conformally deposited above the surface 35 of the dielectric cap layer 34 and in the opening 36. The layer 38 substantially covers the sidewalls 36A of the opening 36, as shown in Figure 5. As will become apparent upon a complete reading of the present application, a sidewall spacer 40 (see Figure 6) will ultimately be formed from the insulating layer 38. The layer 38 may be formed from a variety of insulating materials, e.g., silicon dioxide, silicon oxynitride, an oxide, an oxynitride, a fluorinated oxide, silicon carbide, SiC_x(OH)_y, etc. The layer 38 may be comprised of an insulating material having a dielectric constant greater than approximately 2.5 and/or having a density of at least 1.2 grams/cc. That is, the layer 38 is comprised of an insulating material that is more dense and less porous than the insulating material comprising the layer 32. The thickness of the layer 38, as well as the manner in which it is formed, are matters of design choice. For example, the layer 38 may be comprised of a conformally deposited layer of silicon dioxide having a thickness ranging from approximately 5-10nm (50-100 A), and it may be formed by a CVD process. In view of the foregoing, it is readily apparent that the materials of construction, as well as the manner in which the layer 38 is formed, should not be considered a limitation of the present invention unless specifically recited in the appended claims.

Next, an anisotropic etching process is performed on the layer 38 to thereby define a sidewall spacer 40 positioned in the opening 36 adjacent the sidewalls 36A, as shown in Figure 6. The spacer 40, due to the more dense nature of the material used to make the spacer 40, has a surface 41 that is less rough than the original sidewall 36A of the opening 36 formed in the relatively porous structure of the insulating material layer

10. In one illustrative embodiment, where the opening 36 is approximately 50-200nm (500-2000 A) in diameter, the sidewall spacer 40 may have a thickness at the base 40A that ranges from approximately 3-100nm (30-1000 A). Note that, this anisotropic etching process removes the layer 38 from the surface 35 of the dielectric cap layer 34 and from the bottom 36B of the opening 36. That is, through this process, a denser insulating material, in the form of the sidewall spacer 40, is positioned in the opening 36 adjacent the sidewalls

36A of the insulating layer 32, i.e., where the conductive interconnection will be formed.

Thereafter, a conductive material (or layers of conductive material), e.g., copper, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, etc., is then formed in the opening 36 above the sidewall spacer 40, and one or more CMP processes are performed to define a conductive line or plug 42 in the opening 36, as shown in Figure 7. By way of example, in the case of forming conductive interconnections comprised of copper, a barrier metal layer and a copper seed layer (not shown) may be formed above the surface 35 of the dielectric cap layer 34 and in the opening 36 above the sidewall spacer 40 using known processing techniques. As will be appreciated by those skilled in the art with benefit of the present disclosure, the insulating material layer 32, comprised of a porous, relatively low-k insulating material, is isolated from the barrier metal and copper seed layer by the sidewall spacer 40, comprised of a more dense, less porous insulating material, formed in the opening 36. Thus, migration of the copper in the copper seed layer and/or the copper conductive interconnection into the relatively porous low-k insulating layer 32 may be reduced or prevented. Additionally, in contrast to the prior processes described in the background section of this application, the copper seed layer is formed above the relatively smoother surface 41 of the sidewall spacer 40, thereby insuring better coverage of the copper seed layer within the opening 36. This, in turn, helps to reduce the likelihood of voids being formed in the conductive interconnection formed in the opening 36.

Thereafter, a layer of conductive material (not shown) comprised of copper may be formed above the surface 35 of the dielectric cap layer 34 and in the opening 36. The copper material may be formed using known electrodes or electroplating techniques. For example, after formation of the copper seed layer, having a thickness ranging from approximately 10-lOOnm (100-1000 A), the structure may be submerged in an inorganic electrolytic bath consisting of copper sulfate, an acid, such as sulfuric acid, and an inorganic anion, such as chloride. An electrical current may then be uniformly applied across the wafer to begin the plating process. Organic compounds may also be added to the bath to enhance uniformity. However, the particular process parameters of the electroplating process should not be considered a limitation of the present invention unless they are specifically set forth in the appended claims. Although not depicted in the drawings, in situations where the conductive interconnections may be comprised of another material, e.g., tungsten, the layer of conductive material may be directly deposited above the surface 35 of the dielectric cap layer 34 and in the opening 36 above the sidewall spacer 40. Such a layer may be fonned by a variety of known processes, e.g., CVD, PVD, etc. Additionally, although not depicted in the drawings, prior to the formation of such a layer of conductive material, a layer of adhesion material (not shown), comprised of, for example, titanium, titanium nitride, tantalum, tantalum nitride, etc., may be formed above the surface 35 of the cap layer 34 and in the opening 36 above the sidewall spacer 40.

Thereafter, one or more chemical mechanical polishing ("CMP") operations are performed to remove portions of the conductive layer lying outside of the opening 36 above the surface 35 of the dielectric cap layer 34 to define a conductive interconnection 42. That is, CMP operations are performed until such time that substantially all of the conductive material, e.g., copper, tungsten, is removed from above the surface 35 of the dielectric cap layer 34. When CMP operations are completed, a surface 43 of the conductive interconnection 42 is approximately planar with the surface 35 of the dielectric cap layer 34.

Figures 8-12 depict an illustrative embodiment of the present invention disclosed in the context of a dual damascene process that may be used in forming conductive interconnections comprised of copper or other metals. It should be understood that, with respect to this embodiment of the invention, the various layers and structures may be comprised of materials, and made in manner similar to, corresponding layers and structures described with respect to the previous embodiment disclosed herein.

As shown in Figure 8, an insulating layer 52, an etch-stop layer 54, an insulating layer 56, and a dielectric cap layer 58 may be formed above a semiconducting substrate 50 (or other structure or process layer), using a variety of known processing techniques, e.g., CVD, PVD, etc. The insulating layers 52, 56 may be comprised of materials similar to that described with respect to insulating layer 32. Similarly, the dielectric cap layer 58 may be comprised of materials similar to that described above with respect to the dielectric cap layer 34. The etch-stop layer 54 may be comprised of materials, such as silicon nitride, and it may have a thickness ranging from approximately 20-80nm (200-800 A).

Next, as shown in Figure 9, openings 60, 62 are formed in the insulating layers 52, 56, respectively, by performing one or more etching processes commonly used in dual damascene processing techniques. The opening 62 is defined by sidewalls 56A in the insulating layer 56, and the opening 60 is defined by sidewalls 52A in the insulating layer 52. As will be recognized by those skilled in the art, the opening 62 may be adapted for a conductive line, whereas the opening 60 may be for a conductive contact or via to connect to a transistor device or an underlying metal line (not shown).

Next, as shown in Figure 10, a layer of insulating material 64 is conformally deposited above the structure depicted in Figure 9, i.e., above the surface 59 of the dielectric cap layer 58 and in the openings 60 and 62. The insulating layer 64 may be comprised of similar materials to that described above with respect to the insulating layer 38, and it may be made by similar techniques.

Next, as shown in Figure 11, one or more anisotropic etching processes are performed to define sidewall spacers 64B and 64A in openings 60 and 62, respectively. Thereafter, a conductive interconnection may be formed in the opening 60, 62 using a variety of techniques. For example, when it is desired to form conductive interconnections comprised of copper, a barrier metal layer (not shown) and a copper seed layer (not shown) may be formed above the structure depicted in Figure 11, i.e., in the openings 62 and 60, and copper

-1- may be filled within the openings by performing traditional electroplating processes. Alternatively, depending upon the conductive material selected for the conductive interconnection, a barrier metal layer (not shown) and a layer of conductive material (not shown), e.g., tungsten, may be deposited in the opening 60, 62. Thereafter, one or more chemical mechanical polishing operations are performed to define a conductive interconnection structure 65 as depicted in Figure 12.

Through use of the present invention, relatively porous, low-k insulating materials may be employed in forming conductive interconnections in integrated circuit devices while reducing or eliminating some or all of the problems described in the background section of the application. That is, in using the present invention, a sidewall spacer 40, comprised of a relatively dense insulating material, is positioned adjacent sidewalls 36A of an opening 12 formed in a relatively porous, low-k insulating material 32. As a result, the conductive material positioned in the opening 36 is formed or deposited over the relatively smoother sidewalls 41 of the spacers 40, thereby reducing the tendency to form voids or seams in the resulting interconnection. Additionally, the relatively dense sidewall spacer 40 tends to reduce or eliminate the migration of metal atoms from the conductive interconnection into the relatively porous low-k insulating material 32. The present invention is directed to a novel integrated circuit device, and a method of making same. In one illustrative embodiment, the integrated circuit device comprises an insulating layer 32 comprised of a first insulating material that has an opening 36 formed therein as defined by at least one sidewall 36A. The device further comprises at least one sidewall spacer 40 positioned adjacent the sidewall 36A of the opening 36, the sidewall spacer 40 being comprised of a second insulating material, and a conductive interconnection 42 formed in the opening 36 in the insulating layer 32. In a further embodiment, the first insulating material has a dielectric constant less than approximately 2.5, and has a density less than approximately 1.2 grams/cc, whereas the second insulating material has a dielectric constant less than approximately 7 and a density less than approximately 3 grams/cc.

In one illustrative embodiment, the method disclosed herein comprises forming an opening 36 in a first layer 32 comprised of a first insulating material, the opening 36 being defined by at least one sidewall 36A, and conformally depositing a second layer 38 comprised of a second insulating material in the opening 36 above the sidewall 36 A. The method further comprises performing an anisotropic etching process on the second layer 38 to define a sidewall spacer 40 comprised of the second insulating material positioned adjacent the sidewall 36A of the opening 36, and forming a conductive interconnection 42 in the opening 36 in the insulating layer 32. The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention.

Accordingly, the protection sought herein is as set forth in the claims below.

Claims

1. An integrated circuit device, comprising: an insulating layer (32) comprised of a first insulating material, said insulating layer (32) having an opening (36) defined therein by at least one sidewall (36 A); at least one sidewall spacer (40) positioned adjacent said sidewall (36A) of said opening (36), said spacer (40) comprised of a second insulating material; and a conductive interconnection (42) formed in said opening.

2. The integrated circuit device of claim 1, wherein said first insulating material is comprised of a material having a dielectric constant less than approximately 3.

3. The integrated circuit device of claim 1, wherein said first insulating material has a density less than approximately 1.2 grams/cc.

4. The integrated circuit device of claim 1, wherein said first insulating material is comprised of at least one of hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), hydroxylated silicon carbides (SiC_xOH_y), a polymeric dielectric, mesoporous silica, an aerogel and a xerogel.

5. The integrated circuit device of claim 1, wherein said second insulating material is comprised of a material having a dielectric constant less than approximately 7.

6. The integrated circuit device of claim 1, wherein said second insulating material is comprised of a material having a density less than approximately 3 grams/cc.

7. The integrated circuit device of claim 1, wherein said second insulating material is comprised of at least one of an oxide, an oxynitride, silicon dioxide, silicon oxynitride, and a fluorinated oxide.

8. The integrated circuit device of claim 1, wherein said sidewall spacer (40) has a base having a thickness ranging from approximately 3-100nm.

9. The integrated circuit device of claim 1, wherein said conductive interconnection (42) is comprised of at least one of copper, tungsten and aluminum.

10. The integrated circuit device of claim 1, wherein said conductive interconnection (42) is comprised of at least one of a conductive line and a conductive plug.

11. An integrated circuit device, comprising: an insulating layer (32) comprised of a first insulating material having a density less than 1.2 grams/cc and a dielectric constant less than about 2.5, said insulating layer having an opening (36) defined therein by at least one sidewall (36A); at least one sidewall spacer (40) positioned adjacent said sidewall (36A) of said opening (36), said spacer (40) comprised of a second insulating material having a density less than approximately 3.0 grams/cc and a dielectric constant less than about 7; and a conductive interconnection formed in said opening.

12. The integrated circuit device of claim 11, wherein said first insulating material is comprised of at least one of hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), hydroxylated silicon carbides (SiC_xOH_y), a polyermic dielectric, mesoporous silica, an aerogel and a xerogel.

13. The integrated circuit device of claim 11, wherein said second insulating material is comprised of at least one of an oxide, an oxynitride, silicon dioxide, silicon oxynitride, and a fluorinated oxide.

14. A method, comprising: forming an opening (36) in a first layer (32) of a first insulating material, said opening (36) defined by at least one sidewall (36A); conformally depositing a second layer (38) comprised of a second insulating material in said opening

(36) above said at least one sidewall (36A); performing an anisotropic etching process on said conformally deposited second layer (38) of insulating material to define a sidewall spacer (40) comprised of said second insulating material positioned adjacent said at least one sidewall of said opening (36); and forming a conductive interconnection (42) in said opening between said at least one sidewall spacer (40) comprised of said second insulating material.

15. The method of claim 14, wherein said first insulating material has a dielectric constant less than approximately 3.

16. The method of claim 14, wherein said first insulating material is comprised of at least one of hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), hydroxylated silicon carbides (SiC_xOH_y), a polymeric dielectric, mesoporous silica, an aerogel and a xerogel.

17. The method of claim 14, wherein said second insulating material has a dielectric constant greater than approximately 3.5.

18. The method of claim 14, wherein said second insulating material is comprised of at least one of an oxide, an oxynitride, silicon dioxide, silicon oxynitride, and a fluorinated oxide.

19. The method of claim 14, wherein said first insulating material has a density less than approximately 1.2 grams/cc.

20. The method of claim 14, wherein said second insulating material has a density less than approximately 3 grams/cc.