WO2002071476A3 - Method of forming conductive interconnections in porous insulating films and associated device - Google Patents

Method of forming conductive interconnections in porous insulating films and associated device Download PDF

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Publication number
WO2002071476A3
WO2002071476A3 PCT/US2002/003945 US0203945W WO02071476A3 WO 2002071476 A3 WO2002071476 A3 WO 2002071476A3 US 0203945 W US0203945 W US 0203945W WO 02071476 A3 WO02071476 A3 WO 02071476A3
Authority
WO
WIPO (PCT)
Prior art keywords
opening
sidewall
insulating material
layer
comprised
Prior art date
Application number
PCT/US2002/003945
Other languages
French (fr)
Other versions
WO2002071476A2 (en
Inventor
John G Pellerin
Derick J Wristers
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of WO2002071476A2 publication Critical patent/WO2002071476A2/en
Publication of WO2002071476A3 publication Critical patent/WO2002071476A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

Abstract

The integrated circuit device disclosed herein comprises an insulating layer (32) comprised of a first insulating material that has an opening (36) formed therein as defined by at least one sidewall (36A), at least one sidewall spacer (40) positioned adjacent the sidewall (36A) of the opening (36), the sidewall spacer (40) being comprised of a second insulating material, and a conductive interconnection (42) formed in the opening (36) in the insulating layer (32). In a further embodiment, the first insulating material has a dielectric constant less than approximately 3, and a density less than approximately 1.2 grams/cc, whereas the second insulating material has a dielectric constant less than approximately 7 and a density less than approximately 3 grams/cc. The method disclosed herein comprises forming an opening (36) in a first layer (32) of a first insulating material, the opening (36) being defined by at least one sidewall (36A), and conformally depositing a second layer (38) comprised of a second insulating material in the opening (36) above the sidewall (36A). The method further comprises performing an anisotropic etching process on the second layer to define a sidewall spacer (40) comprised of the second insulating material positioned adjacent the sidewall (36A) of the opening (36), and forming a conductive interconnection (42) in the opening (36) in the insulating layer (32) between the sidewall spacer (40).
PCT/US2002/003945 2001-03-06 2002-02-01 Method of forming conductive interconnections in porous insulating films and associated device WO2002071476A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US80025001A 2001-03-06 2001-03-06
US09/800,250 2001-03-06

Publications (2)

Publication Number Publication Date
WO2002071476A2 WO2002071476A2 (en) 2002-09-12
WO2002071476A3 true WO2002071476A3 (en) 2003-03-13

Family

ID=25177889

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/003945 WO2002071476A2 (en) 2001-03-06 2002-02-01 Method of forming conductive interconnections in porous insulating films and associated device

Country Status (1)

Country Link
WO (1) WO2002071476A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5372323B2 (en) * 2006-03-29 2013-12-18 富士通株式会社 Interface roughness reducing film, wiring layer and semiconductor device using the same, and method for manufacturing semiconductor device
DE102008045036B4 (en) * 2008-08-29 2011-06-22 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG, 01109 Reducing critical dimensions of vias and contacts above the device level of semiconductor devices

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5661344A (en) * 1994-08-05 1997-08-26 Texas Instruments Incorporated Porous dielectric material with a passivation layer for electronics applications
US5753967A (en) * 1995-09-14 1998-05-19 Advanced Micro Devices, Inc. Damascene process for reduced feature size
US5759906A (en) * 1997-04-11 1998-06-02 Industrial Technology Research Institute Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits
US5916823A (en) * 1998-10-13 1999-06-29 Worldwide Semiconductor Manufacturing Corporation Method for making dual damascene contact
US6140221A (en) * 1998-07-29 2000-10-31 Philips Electronics North America Corp. Method for forming vias through porous dielectric material and devices formed thereby

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5661344A (en) * 1994-08-05 1997-08-26 Texas Instruments Incorporated Porous dielectric material with a passivation layer for electronics applications
US5753967A (en) * 1995-09-14 1998-05-19 Advanced Micro Devices, Inc. Damascene process for reduced feature size
US5759906A (en) * 1997-04-11 1998-06-02 Industrial Technology Research Institute Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits
US6140221A (en) * 1998-07-29 2000-10-31 Philips Electronics North America Corp. Method for forming vias through porous dielectric material and devices formed thereby
US5916823A (en) * 1998-10-13 1999-06-29 Worldwide Semiconductor Manufacturing Corporation Method for making dual damascene contact

Also Published As

Publication number Publication date
WO2002071476A2 (en) 2002-09-12

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