WO2002073696A1 - Procede pour fabriquer un dispositif semi-conducteur a circuit integre - Google Patents
Procede pour fabriquer un dispositif semi-conducteur a circuit integre Download PDFInfo
- Publication number
- WO2002073696A1 WO2002073696A1 PCT/JP2001/009547 JP0109547W WO02073696A1 WO 2002073696 A1 WO2002073696 A1 WO 2002073696A1 JP 0109547 W JP0109547 W JP 0109547W WO 02073696 A1 WO02073696 A1 WO 02073696A1
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- WIPO (PCT)
- Prior art keywords
- film
- integrated circuit
- semiconductor integrated
- circuit device
- manufacturing
- Prior art date
Links
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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Definitions
- the present invention relates to a semiconductor integrated circuit device manufacturing technique, and in particular, has a MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a polymetal structure in which a gate electrode is formed by a laminated film of polycrystalline silicon and a refractory metal. He relates to effective technology applied to the manufacture of semiconductor integrated circuit devices. Profile:
- MISFET Metal Insulator Semiconductor Field Effect Transistor
- Japanese Patent Application Laid-Open No. H11-26395 discloses that as a measure to alleviate the electric field concentration at the end of the gate electrode, the gate electrode has a W / WSixNy / WOx structure and a reducing atmosphere. Discloses a technique for reducing W 0 X by performing a heat treatment at a lower temperature to make the bottom end of the gate electrode round.
- Japanese Patent Application Laid-Open No. 2000-331978 discloses that after a gate electrode having a polymetal structure containing W is processed, an acidic or alkaline solution substantially free of hydrogen peroxide is used. It discloses a technology to prevent W from dissolving by washing.
- USP 4282270 and the like relate to oxynitriding. Further, regarding the treatment of hydrogen exhaust gas, there are USP5202096, USP5088314, JP-A-8-83772, JP-A-9-75651 and the like.
- JP-A-7-321102 JP-A-60-107840 and USP 5693578.
- CMOS LSIs which are composed of fine M ⁇ S FETs with gate lengths of 0.18 m or less, and DRAMs that use gate electrodes and gate electrode layers with a width of 0.18 ⁇ m or less for wiring, even at low voltage operation
- a gate processing process using a low-resistance conductive material including a metal layer is considered to be adopted.
- Promising as this kind of low-resistance gate electrode material is a so-called polymetal in which a refractory metal film is laminated on a polycrystalline silicon film.
- Polymetal can be used not only as a gate electrode material but also as a wiring material because its sheet resistance is as low as 2 ⁇ / port.
- As a high melting point metal it shows good low resistance even in a low temperature process of 800 ° C or less, and has electromigration resistance W (tungsten), Mo (molybdenum), etc. are used.
- the polymetal gate has a three-layer structure in which a barrier layer made of a metal nitride film such as WNX (tungsten nitride) is interposed between a polycrystalline silicon film and a refractory metal film.
- a barrier layer made of a metal nitride film such as WNX (tungsten nitride) is interposed between a polycrystalline silicon film and a refractory metal film.
- An object of the present invention is to provide a technique for reducing contamination of a substrate by oxide of a high melting point metal constituting a part of a polymetal gate.
- a method for manufacturing a semiconductor integrated circuit device includes the following steps.
- a method for manufacturing a semiconductor integrated circuit device includes the following steps.
- a method for manufacturing a semiconductor integrated circuit device includes the following steps.
- FIG. 1 is an overall plan view of a semiconductor chip on which a semiconductor integrated circuit device according to an embodiment of the present invention is formed.
- FIG. 2 is a plan view of a main part of a semiconductor integrated circuit device according to an embodiment of the present invention.
- FIG. 3 is a sectional view of a main part of a semiconductor integrated circuit device according to an embodiment of the present invention.
- FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
- FIG. 5 is a plan view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
- FIG. 6 is a fragmentary cross-sectional view of a semiconductor substrate illustrating a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.
- FIG. 7 is a fragmentary cross-sectional view of a semiconductor substrate illustrating a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.
- FIG. 8 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating the method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
- FIG. 9 is a diagram illustrating a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention. It is principal part sectional drawing of a conductor board.
- FIG. 10 is a plan view of a principal part of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
- FIG. 11 is an enlarged cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
- FIG. 12 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
- FIG. 13 is a fragmentary enlarged cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
- FIG. 14 is a schematic diagram of a batch type vertical oxidation furnace used for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
- FIG. 15 is a schematic diagram showing a catalytic steam / hydrogen mixed gas generator connected to the batch type vertical oxidation furnace shown in FIG.
- FIG. 16 is a piping diagram of the steam / hydrogen mixed gas generator shown in FIG. Figure 17 shows the equilibrium vapor pressure ratio (P H20
- FIG. 18 is an explanatory diagram of a reoxidation process sequence using the batch type vertical oxidation furnace shown in FIG.
- FIG. 19 is an enlarged cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
- FIG. 20 (a) is a schematic diagram of a single-wafer oxidizing furnace used for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention, and (b) is a cross-sectional view of FIG. It is sectional drawing along the line.
- FIG. 21 is a phase diagram showing the relationship between the oxidation-reduction potential of tungsten-water system and pH.
- FIG. 22 is a graph showing the result of measuring the effect of removing the natural oxide film formed on the surface of the W film by washing with water using total reflection X-ray fluorescence.
- FIG. 23 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
- FIG. 24 shows a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.
- FIG. 2 is a sectional view of a principal part of a semiconductor device.
- FIG. 25 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating the method of manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention.
- FIG. 26 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
- FIG. 27 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.
- FIG. 28 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method of manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention.
- FIG. 29 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating the method of manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention.
- FIG. 30 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
- FIG. 31 is a plan view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.
- FIG. 32 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method of manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention.
- FIG. 33 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.
- FIG. 34 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating the method of manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention.
- FIG. 35 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
- FIG. 36 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
- FIG. 37 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention.
- FIG. 38 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 39 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 40 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 41 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 42 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 43 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 44 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 45 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 46 is a graph showing the result of examining the relationship between the nitrogen flow rate and the crystal structure of the WN X film when forming the WN X film constituting a part of the gate electrode by X-ray diffraction measurement.
- FIG 4 7 (a), (b ) keeps the flow rate of argon gas constant, because a graph of film stress was measured when the heat treatment of the WN X film varying Ete deposited nitrogen gas flow rate at various temperatures .
- Figure 48 shows the results of examining the relationship between the breakdown voltage of the gate electrode including the WN X film and the contact resistance at the interface between the WN X film and the polycrystalline silicon film, which were formed by changing the flow ratio of nitrogen gas and argon gas.
- FIG. 48 shows the results of examining the relationship between the breakdown voltage of the gate electrode including the WN X film and the contact resistance at the interface between the WN X film and the polycrystalline silicon film, which were formed by changing the flow ratio of nitrogen gas and argon gas.
- FIG. 49 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 50 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 51 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 52 shows a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 3 is a sectional view of a main part of a semiconductor substrate.
- FIG. 53 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 54 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 55 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 56 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 57 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 58 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 59 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 60 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 61 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 62 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 63 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 64 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 65 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 66 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 67 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 68 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 69 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 70 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 71 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 72 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 73 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 74 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- FIG. 75 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
- a semiconductor integrated circuit wafer or a semiconductor wafer refers to a silicon single crystal substrate (generally a substantially circular shape), a sapphire substrate, a glass or other insulating, anti-insulating or semiconductor substrate used in the manufacture of a semiconductor integrated circuit, and the like. Refers to a composite substrate.
- semiconductor integrated circuit device or “electronic device”, “electronic circuit device”, etc. refers not only to those made on a single-crystal silicon substrate, but also to the case where it is clearly stated otherwise.
- SOI Silicon On Insulator
- TFT Thin Film Transistor
- ST ST Super Twisted Nematic liquid crystal substrate
- the material is a material that has the material as a major component, and that the addition of other elements is permitted.
- silicon oxide silicon films various silicon oxide-based films containing various additives and auxiliary components, that is, P S, are generally used unless otherwise specified.
- TEOS Tetra-Ethoxy Silane
- silicon oxynitride film a TEOS (Tetra-Ethoxy Silane) oxide film and a silicon oxynitride film.
- the gate oxide film includes a silicon thermal oxide film, a silicon oxynitride film, a thermal oxide film, a deposited film, a coating film, and a non-silicon-based metal other than the silicon oxide film.
- insulating nitrides such as oxides and silicon nitride, or composite films thereof.
- silicon When the material of the conductive region on the substrate surface or the conductive region of the deposited film is referred to as “silicon” or “silicon base”, unless otherwise specified, it is possible to add impurities to silicon in addition to relatively pure silicon members. And conductive materials containing silicon as a main component (for example, Si Ge alloy containing more than 50% Ge in a silicon-based alloy. , And the gate polysilicon portion and the channel region are made to be Si Ge). They also allow high resistance at the outset, as long as they are not technically inconsistent.
- Some deposited films are amorphous at the beginning of the deposition, but become polycrystalline immediately after the subsequent heat treatment.However, these are used to avoid inconsistencies in expression except when it is deemed necessary. It may be displayed in a later form from the beginning.
- polycrystalline silicon polysilicon
- polysilicon is in an amorphous state at the beginning of deposition, and is changed to polycrystalline silicon by a subsequent heat treatment.
- An amorphous state at the beginning of deposition has advantages such as prevention of channeling in ion implantation, avoidance of workability depending on agglomerate shape at the time of dry etching, and low sheet resistance after heat treatment.
- Patent Application No. 2000-1-184091 Japanese Patent Application Laid-Open No. H09-1721011, Japanese Patent Application Laid-Open No. H10-3653652, Japanese Patent Application No. Japanese Patent No. 340909, Japanese Unexamined Patent Application Publication No. Hei 11-33409, Japanese Unexamined Patent Application Publication No. Hei 10-34992, U.S. Pat.No. 6,066,508, International Publication No. WO98 / 39808, International Publication No. WO97 / 28085, and the like.
- FIG. 1 is an overall plan view of a semiconductor chip 1A on which a DRAM (Dynamic Random Access Memory) of the present embodiment is formed.
- a DRAM Dynamic Random Access Memory
- This DRAM is mainly composed of a storage section composed of a plurality of memory arrays (MARY) and a peripheral circuit section PC arranged around them.
- MARY memory arrays
- PC peripheral circuit section
- FIG. 2 is a plan view of a semiconductor substrate showing a part of a memory array (MARY) of the DRAM
- FIG. 3 is a sectional view of a main part of the semiconductor substrate showing the DRAM.
- the left area of FIG. 3 is a cross-sectional view taken along the line A—A of FIG. 2, the central area is a cross-sectional view taken along the line B—B of FIG. 2, and the right area is the peripheral circuit (PC).
- PC peripheral circuit
- a semiconductor substrate made of p-type single-crystal silicon hereinafter, referred to as a substrate. In some cases, a semiconductor wafer or simply a wafer).
- the p-type cell of the memory array is composed of an n-channel type memory cell selection MI SFE T (Metal Insulator Semiconductor Field Effect Transistor) Qt and an information storage capacitor C formed on top of it. Are formed.
- MI SFE T Metal Insulator Semiconductor Field Effect Transistor
- the MI SFET Qt for memory cell selection is mainly composed of the gate insulating film 6, the gate electrode 7A constituting the lead line WL in a region other than the active region L, and a pair of n-type semiconductor regions (source, drain) 9, 9. ing.
- the peripheral circuit PC of the DRAM is composed of a so-called complementary MIS circuit combining a plurality of n-channel MISFETQn and a plurality of P-channel MISFETQp.
- the n-channel MISFET Qn is formed in a p-type well 3 and mainly includes a gate insulating film 6, a gate electrode 7B, and a pair of n + -type semiconductor regions (source and drain) 12, 12. Also, p-channel type Ml
- the SFET Qp is formed in the n-type well 4, mainly composed of the gate insulating film 6, the gate electrode
- the gate electrodes 7B and 7C are connected to the memory cell selection MI SFETQt.
- the gate electrode 7A (word line WL) is formed of a conductive film having the same polymethanol structure.
- a sidewall spacer 11s made of a silicon nitride film is formed on the side walls of the gate electrodes 7B and 7C.
- the interlayer insulating film 15 is composed of, for example, a spin-on-glass (Spin On Glass) film (a silicon oxide-based insulating film formed by a coating method) and a two-layer silicon oxide film formed thereon.
- a silicon oxide film 19 is formed on the eyebrow insulating film 15, and a through-hole 20 is formed on the silicon oxide on one of the pair of contact holes 16, 17 (contact hole 16). .
- the through hole 20 is disposed above the element isolation groove 2 deviating from the active region L, and has a two-layer conductive film in which a W film is laminated on top of, for example, a TiN (nitride titanium) film.
- the plug 23 composed of is embedded.
- the plug 23 embedded in the through hole 20 is connected to one of the source and drain of the memory cell selecting MI SFET Qt (the two memory cell selecting MI SFET Qt) through the plug 18 embedded in the lower contact hole 16. It is electrically connected to the shared n-type semiconductor region 9).
- Contact holes 21 and 22 are formed in the silicon oxide film 19 in the peripheral circuit portion and the interlayer insulating film 15 thereunder.
- the contact hole 21 is formed above a pair of n + -type semiconductor regions (source and drain) 12 and 12 constituting the source and the drain of the n-channel type MIS FETQn, and the contact hole 22 is formed as a p-channel type.
- a pair of p + type semiconductor regions that constitute the source and drain of MI SFETQp (Source, drain) 13, 13 are formed on the upper part.
- Plugs 23 made of the same conductive material as the plugs 23 embedded in the through holes 20 of the memory array are embedded in the contact holes 21 and 22.
- bit lines BL for reading data from the memory cells are formed above the silicon film 19 of the memory array. These bit lines BL are arranged above the element isolation grooves 2 and extend in the direction orthogonal to the gate electrode 7A (word line WL) with the same width and the same interval. Each of the bit lines BL is formed on the silicon oxide film 19 underneath, and through a plug 23 in a through hole 20 and a plug 18 in a contact hole 16 under the source, the source of the memory cell selecting MISFETQt is formed. Is electrically connected to one of the source and drain (n-type semiconductor region 9). Bit line BL is constituted by a conductive film formed by laminating a W film on e.g. WN X film.
- First-layer wirings 30 to 33 are formed on the silicon oxide film 19 of the peripheral circuit section PC. These wirings 30 to 33 are formed of the same conductive film as the bit line BL, and are formed simultaneously with the bit line BL as described later.
- the wirings 30 and 31 are electrically connected to the source and drain (n + type semiconductor region 12) of the n-channel MISFET Qn via the plug 23 in the contact hole 21 formed in the silicon oxide films 19 and 15.
- the wirings 32 and 33 are electrically connected to the source and drain (p + type semiconductor region 13) of the p-channel type MIS FETQp via the plug 23 in the contact hole 22 formed in the silicon oxide films 19 and 15.
- an interlayer insulating film 40 is formed over the bit line BL and the first-layer wirings 30 to 33.
- the interlayer insulating film 40 like the lower interlayer insulating film 15, is composed of a spin-on glass film and a two-layer silicon oxide film formed on the spin-on glass film. They are flattened so that they are at the same height.
- a through hole 43 is formed in the interlayer insulating film 40 of the memory array and the underlying silicon oxide layer 19.
- the through-hole 43 is disposed directly above the contact hole 17 under the through-hole 43. Inside the through-hole 43, for example, a plug formed of an n-type polycrystalline silicon film doped with P (phosphorus) is provided. 44 is embedded.
- a silicon nitride film 45 and a thick silicon oxide film 46 are formed, and a deep silicon oxide film 46 formed in the silicon oxide film 46 of the memory array is formed.
- an information storage capacitance element C composed of a lower electrode 48, a capacitance insulating film 49, and an upper electrode 50 is formed.
- the lower electrode 48 of the information storage capacitor C is formed of, for example, a low-resistance n-type polycrystalline silicon film doped with P (phosphorus), and the through-hole 43 and the capacitor formed thereunder are formed.
- the capacitor insulating film 4 9 of the information storage capacity element C is constituted by, for example T a 2 0 5 (tantalum oxide) film, an upper electrode 5 0 is constituted by, for example, T i N film.
- a silicon oxide film 51 is formed on the information storage capacitive element C, and about two layers of A1 wiring are formed on the silicon oxide film 51, but these are not shown.
- a substrate made of, for example, p-type single crystal silicon
- B boron
- P phosphorus
- p-type well 3 and n-type well 4 are formed.
- an element isolation region of the substrate 1 is etched to form a groove having a depth of about 350 nm, and then a CVD (Chemical Vapor Vapor) is formed inside the groove and on the substrate 1. Deposition) silicon oxide film
- CMP Removed by Mechanical Polishing
- an n-type polycrystalline silicon film 14 n doped with P (phosphorus) is deposited on the gate insulating film 6.
- the polycrystalline silicon film 14 ⁇ has a ⁇ concentration of at least 1.10 ⁇ 10 19 cm 3 in order to reduce electric resistance.
- a silicon film containing Ge (germanium) in an amount of 5% to about 50% at the maximum may be used. If moistened with Ge in silicon, the band gap of silicon is narrow and, due to the solubility limit of the impurity is high, there is an advantage that the contact resistance between the upper layer of WN X film is reduced .
- a method of depositing a silicon film containing Ge by CVD using monosilane (SiH 4 ) and GeH 4 is required. is there.
- WN X film 24 functions as a barrier layer for preventing the reaction between the polycrystalline silicon film 14n and the W film 25.
- a plasma CVD method capable of forming a film at a relatively low temperature (around 480 ° C.) is used.
- a thin silicon nitride film of about 1 Onm is deposited on the film 25, and then a lamp anneal of about 950 ° for 10 seconds is performed to remove gas components in the silicon nitride film.
- it is preferable to deposit a silicon nitride film of about 150 nm using a low-pressure CVD method (deposition temperature around 780 ° C).
- a plasma CVD method may be deposited on the W film 25 using a plasma CVD method, and then the silicon nitride film 8 may be deposited on the W film 25 using a low-pressure CVD method.
- a photoresist formed on the silicon nitride film 8 is formed.
- the gate electrode 7A (word line WL) is formed to extend in a direction orthogonal to the long side of the active region L.
- the line width (gate length) of the gate electrode 7A (word line WL) and the interval between adjacent gate electrodes 7A (word line WL) are, for example, 0.13 to 0.14 zm.
- the gate electrode 7A word line WL
- a part of the conductive material forming the gate electrodes 7B and 7C into a polymetal structure formed of a low-resistance metal (W)
- the sheet is formed. Since the resistance is reduced to about 2 ⁇ / port or less and the gate delay is suppressed, a DRAM that operates at high speed can be realized.
- the gate electrodes 7A (word lines WL), 7B, and 7C As shown in FIG. 11, the gate electrodes 7A (word lines WL), 7B, It is desirable to leave the gate insulating film 6 thin (eg, about 3 nm) on the surface of the substrate 1 around 7 C.
- the gate insulating film 6 thin (eg, about 3 nm) on the surface of the substrate 1 around 7 C.
- a contaminant containing W which is a part of the gate electrode material, is deposited on the surface of the substrate 1 in a later heat treatment step.
- reaction products such as W silicide, which adheres directly and is difficult to remove by ordinary cleaning treatment, may occur.
- the substrate is transferred from 1 Doraiedzuchingu device Adzushingu device, as shown in FIG. 1 2, is removed by dividing the photoresist film 2 6 by Adzushingu with 0 2 plasma.
- the surface of the substrate 1 is exposed to the air in the process.
- the photoresist film 26 is removed by asking using O 2 plasma, the surface of the substrate 1 is exposed to an O 2 plasma atmosphere. Therefore, when the above-mentioned asshing is completed, as shown in FIG. 13, the surface of the W film 25 exposed on the side walls of the gate electrodes 7A, 7B, and 7C is coated with an undesired oxide film (W).
- O x ) 27 is formed.
- the oxide 27 sublimates in the subsequent heat treatment step, adheres to the inner wall of the heat treatment chamber, and then adheres again to the surface of the substrate 1 to become a contaminant. This causes deterioration of device characteristics (such as refresh failure in the case of DRAM).
- the gate insulating film 6 in the lower portions of the side walls of the gate electrodes 7A, 7B, and 7C and in the peripheral region is also cut to some extent. Since the film thickness is smaller than that at the beginning of the formation (see FIG. 13), problems such as a decrease in the gate breakdown voltage occur if left as it is.
- FIG. 14 is a schematic view showing an example of a batch type vertical oxidation furnace used for the re-oxidation treatment of the gate insulating film 6.
- the vertical oxidation furnace 150 includes a chamber 151 formed of a quartz tube, and a heater 152 for heating the wafer (substrate) 1 is provided around the chamber 151. Inside the chamber 151, a British boat 153 that holds a plurality of wafers 1 horizontally is installed.
- a gas introduction pipe 154 for introducing a steam / hydrogen mixed gas and a purge gas, and an exhaust pipe 155 for discharging these gases are connected to the bottom of the chamber 151.
- the other end of the gas introduction pipe 154 is connected to a gas generator 140 as shown in FIGS.
- FIG. 15 is a schematic diagram showing a catalytic steam / hydrogen mixed gas generator connected to the batch type vertical oxidation furnace 150
- FIG. 16 is a piping diagram of the gas generator.
- the gas generator 140 includes a reactor 141 made of a heat-resistant and corrosion-resistant alloy, and a coil 142 made of a catalytic metal such as Pt (platinum), Ni (nickel), or Pd (palladium).
- a heater 143 for heating the coil 142 is provided.
- a process gas composed of hydrogen and oxygen and a purge gas composed of an inert gas such as nitrogen are introduced into the reactor 141 from the gas storage tanks 14a, 144b, 144c through a pipe 145.
- the process gas (hydrogen and oxygen) introduced into the reactor 141 was 350
- the catalytic gas generator 140 as described above can control the amounts of hydrogen and oxygen involved in the generation of water and their ratio with high precision, the steam / hydrogen introduced into the chamber 151
- the water vapor concentration in the mixed gas can be controlled over a wide range from a very low concentration on the order of ppm to a high concentration of about 10%, and with high accuracy.
- process gas is introduced into the reactor 144, water is instantaneously generated, so that a water vapor / hydrogen mixed gas having a desired water vapor concentration can be obtained in real time. This also minimizes the entry of foreign matter, so that a clean steam / hydrogen mixed gas can be introduced into the chamber 151.
- the catalyst metal in the reactor 141 is not limited to the above-mentioned metals as long as they can radicalize hydrogen and oxygen.
- it may be processed into, for example, a hollow tube or a fine fiber filter, and a process gas may be passed through the inside.
- Figure 17 is a graph showing the temperature dependence of the equilibrium vapor pressure ratio ( PH20 / PH2) of the oxidation-reduction reaction using a steam / hydrogen mixed gas.
- the curves (a) to (e) in the figure It shows the equilibrium vapor pressure ratios of W, Mo, Ta (tantalum), Si, and Ti (titanium).
- the steam / hydrogen partial pressure ratio of the steam / hydrogen mixed gas introduced into the chamber 151 of the vertical oxidation furnace 150 is defined as the range of the region between the curves (a) and (d).
- both the metals (W, Mo, Ta, Ti) and the silicon have a higher acid velocity as the steam concentration in the steam / hydrogen mixed gas increases. Therefore, by increasing the water vapor concentration in the water vapor / hydrogen mixed gas introduced into the chamber 151, silicon can be selectively oxidized by heat treatment in a shorter time. be able to.
- the metal parts of the gate electrodes 7A, 7B, and 7C are composed of Mo (molybdenum)
- the partial pressure ratio of water vapor / hydrogen is defined by the region between the curves (b) and (d). By setting it within the range, it is possible to selectively oxidize only silicon without oxidizing the Mo film.
- a quartz boat 153 holding a plurality of wafers 1 is loaded into a chamber 151 filled with a purge gas (nitrogen).
- the time required to load the quartz boat 153 is about 10 minutes.
- the purge gas (nitrogen) in the chamber 15 1 is preheated in advance in order to shorten the time for raising the temperature of the wafer 1.
- the upper limit of the preheating temperature should be less than 500 ° C.
- hydrogen gas was introduced into Channo U51 through the gas introduction pipe 154 for about 10 minutes, and the gas in the chamber 155 was replaced. Make the atmosphere where 7 is reduced. Then, the wafer 1 is heated to a temperature of 600 ° C. or more, for example, 800 ° C., over a period of about 30 to 40 minutes while continuously supplying the hydrogen gas into the chamber 151.
- the supply of oxygen may be interrupted before the reactor 141, and only hydrogen may be supplied.
- the oxide 27 on the side walls of the gate electrodes 7A, 7B and 7C is reduced, most of the oxide 27 can be removed. Since it is reduced to W, the amount of the oxide 27 sublimated in the chamber 15 1 can be kept at an extremely low level. As a result, the contamination of the substrate 1 in the step of re-oxidizing the gate insulating film 6 can be kept at an extremely low level, so that the reliability and the production yield of the DRAM are improved.
- oxygen and excess hydrogen are introduced into the reactor 141 of the gas generator 140, and a water vapor containing about 10% of water generated from oxygen and hydrogen by a catalytic action in a partial pressure ratio is contained.
- a gas / hydrogen mixed gas is introduced into the chamber 15 1.
- the temperature of the water vapor / hydrogen mixed gas in the chamber 151 is set to 800 ° C, and the atmospheric pressure is set to normal pressure, or quasi-normal pressure reduction is a pressure reduction range of about 10% to 50% of atmospheric pressure.
- Area (Subatmospheric region) That is, the surface of the wafer 1 is oxidized for 25 to 30 minutes. Depending on the type of the oxidation furnace, the oxidation treatment may be performed in a lower pressure reduction region.
- the pressure during the oxidation treatment is low, the oxidation treatment remaining on the side walls of the gate electrodes 7A, 7B, and 7C may be performed. Object 27 sublimates easily. Therefore, it is desirable that the pressure during the oxidation treatment be at least about 130 OPa or more.
- the substrate 1 around the gate electrodes 7A, 7B, and 7C is reoxidized, so that the substrate is thinned in the above-described dry etching step.
- the thickness of the gate insulating film 6 thus formed is substantially equal to the initial thickness (6 nm).
- the steam / hydrogen partial pressure ratio of the steam / hydrogen mixed gas introduced into the chamber 151 is set in the region between the curve (a) and the curve (d) shown in FIG. to perform set within a range, is not the gate electrode 7A, the W film 25 and WN X film 24 constituting 7B, 7 C are Sani spoon.
- the wafer 1 is heated to a temperature of less than 500 ° C. for about 30 to 40 minutes while supplying only hydrogen into the chamber 151, for example, Cool down to 400 ° C. Subsequently, the supply of hydrogen gas is stopped, nitrogen gas is introduced into the chamber 151 for about 10 minutes to perform gas replacement, and then the quartz boat 153 is unloaded from the chamber 151.
- the temperature at which the inside of the chamber 151 is switched from the hydrogen gas atmosphere to the nitrogen gas atmosphere is high, the W film 25 on the side walls of the gate electrodes 7A, 7B and 7C and the oxide 27 remaining without being reduced sublime. There is a fear.
- the temperature of the wafer 1 is lowered to about 300 ° C. to 200 ° C.
- the temperature of the wafer 1 is lowered to about 100 ° C, more preferably, to 70 ° C to room temperature, and then the atmosphere is switched to the nitrogen gas atmosphere. It is needless to say that by performing the above, the oxidation of the W film 25 can be suppressed.
- FIG. 20 (a) is a schematic diagram showing an example of a single-wafer oxidation furnace used for the re-oxidation treatment
- FIG. 20 (b) is a cross-sectional view taken along line BB of FIG. 20 (a). .
- This single-wafer oxidation furnace 100 includes a chamber 101 formed of a multi-wall quartz tube.
- a halogen lamp 107 for heating the wafer 1 is provided below the heater.
- a disk-shaped soaking ring 103 for uniformly dispersing the heat supplied from the halogen lamp 107 to the entire surface of the wafer 1 is housed.
- the susceptor 104 is held horizontally.
- the soaking ring 103 is made of a heat-resistant material such as quartz or silicon carbide (SiC), and is supported by a support arm 105 extending from a wall surface of the chamber 101.
- a thermocouple 106 for measuring the temperature of the wafer 1 held by the susceptor 104 is installed near the soaking ring 103.
- One end of a gas introduction pipe 108 for introducing a steam / hydrogen mixed gas and a purge gas into the chamber 101 is connected to a part of the wall surface of the chamber 101.
- the other end of the gas inlet pipe 108 is connected to the catalytic gas generator 140 shown in FIGS. 15 and 16.
- a partition 110 having a large number of through holes 109 is provided in the vicinity of the gas inlet pipe 108, and gas introduced into the chamber 101 is supplied to the partition 110 by the gas. After passing through the through hole 109, it is evenly distributed in the chamber 101.
- One end of an exhaust pipe 111 for discharging the gas introduced into the chamber 101 is connected to another part of the wall surface of the chamber 101.
- the re-oxidation process using the single wafer oxidation furnace 100 is similar to the re-oxidation process using the batch vertical oxidation furnace 150 except that the wafer 1 is oxidized one by one. It is almost the same. However, since the temperature of the wafer 1 is raised and lowered by lamp heating in a very short time (usually, about several seconds), the loading / unloading of the wafer 1 is performed at room temperature.
- An example of the reoxidation process using the single-wafer oxidation furnace 100 described above is as follows. First, the chamber 101 previously filled with the purge gas (nitrogen) at room temperature is opened, and the gate electrode 7A, The wafer 1 after the processing of 7B and 7C is loaded on the susceptor 104. Next, the chamber 101 is closed, and hydrogen gas is introduced.
- the purge gas nitrogen
- the temperature of the wafer 1 is raised to a temperature of 600 ° C. or more, for example, 950 ° C., in about 5 seconds while maintaining this atmosphere.
- oxygen and excess hydrogen are introduced into the reactor 141 of the gas generator 140, and a water vapor / hydrogen mixed gas containing water generated by the catalytic action at a partial pressure ratio of about 10%. Is introduced into chamber 101. Then, the halogen lamp 107 is turned on, and the surface of the wafer 1 is oxidized in about three minutes while maintaining the temperature of the steam / hydrogen mixed gas in the chamber 101 at 950 ° C.
- the halogen lamp 107 was turned off, the supply of water vapor / hydrogen mixed gas was stopped, and the inside of the chamber 101 was returned to a hydrogen atmosphere. Then, the wafer 1 was taken for about 10 seconds while maintaining this atmosphere. Cool down to a temperature below 500 ° C, for example 400 ° C. Next, the supply of hydrogen gas is stopped, nitrogen gas is introduced into the chamber 101 to perform gas replacement, and when the temperature in the chamber 101 drops to about room temperature, the wafer 1 is unloaded. Also in this case, the replacement of the hydrogen gas with the nitrogen gas is preferably performed after the temperature of the wafer 1 is lowered to about 300 ° C. to 200 ° C.
- the temperature of the wafer 1 is reduced to about 100 ° C., more preferably to 70 ° C. to room temperature, and then the wafer 1 is cooled to a nitrogen gas atmosphere. It goes without saying that the switching can suppress the oxidation of the W film 25.
- the W film 25 constituting the gate electrodes 7A, 7B, and 7C is obtained in the same manner as the re-oxidation treatment using the vertical W-type vertical oxidation furnace 150.
- the thickness of the gate insulating film 6 can be increased without oxidizing the WN x film 24.
- the oxidized substance sublimated in the chamber 15 1 Since the amount of 27 can be kept at an extremely low level, the contamination of the substrate 1 in the step of reoxidizing the gate insulating film 6 can be kept at an extremely low level.
- the temperature rise to the desired temperature and the subsequent temperature increase were obtained regardless of whether the batch type vertical oxidation furnace 150 was used or the single-wafer type oxidation furnace 100 was used.
- the amount of the oxide 27 attached to the surface of the substrate 1 is reduced by about two to three orders of magnitude when compared with the case of raising and lowering the temperature in a nitrogen atmosphere. It was confirmed that.
- the temperature of the wafer 1 was raised and lowered in a hydrogen atmosphere, but other gases capable of reducing the W oxide, for example, ammonia (NH 3 ),
- a gas atmosphere such as C ⁇ or N 20 .
- a gas atmosphere such as C ⁇ or N 20 .
- a rare gas such as argon (Ar), helium (He :), or xenon (Xe) other than nitrogen is used.
- argon (Ar) argon
- He helium
- Xe xenon
- the wafer 1 was oxidized using a steam / hydrogen mixed gas.
- gases that can oxidize silicon without oxidizing the W film and the Mo film for example oxygen ( ⁇ 2), NO, CO, and Sani ⁇ gas such as C 0 2, may use these oxidizing gases and steam Z hydrogen mixed gas and the mixed gas.
- C 0 and C 0 2 since there is a possibility of reacting with W and M o generating a foreign matter such as force one carbide during heat treatment, it is necessary to use with that in mind.
- the oxide contamination on the surface of the substrate 1 is kept at an extremely low level, so that the temperature is raised to a desired temperature and then lowered in a nitrogen atmosphere. It was possible to reduce the amount of the oxidized substance 27 attached to the surface of the substrate 1 by about two to three digits.
- oxide contamination may adhere during the reoxidation process.
- oxide contamination may occur in the gate insulating film 6 during the next step of ion implantation of impurities, which may degrade the electrical characteristics of the device.
- the cleaning here needs to be performed under the condition that the W film 25 exposed on the side walls of the gate electrodes 7A, 7B, and 7C is not oxidized.
- the surface of the W film 25 exposed to the reducing atmosphere in the reoxidation process is more active than the normal W film, and the surface area is increased by the reduction of the oxide 27, so that It is easier to oxidize than the W film 25 before the re-oxidation process.
- the use of an oxidizing solution must also be avoided in this washing step.
- the substrate can be washed with a reducing solution, and that the W oxide on the surface of the W film 25 exposed on the side walls of the gate electrodes 7A, 7B, and 7C can be removed at the same time.
- the present inventors considered the tungsten shown in FIG.
- an aqueous solution which is made weak by adding ammonia to the above-described ultrapure water or hydrogen-containing water may be used.
- the pH was reduced to 11.5 and the oxidation-reduction potential was reduced from 580 mV to 870 mV.
- the W oxide formed on the surface could be eluted into water and removed without oxidizing the W film.
- This result shows that can be removed by eluting the WO x deposited on the silicon oxide film of the gate electrode peripheral.
- the amount of sublimation of W oxide in the next heat treatment step can be reduced, and contamination of the LSI can be suppressed.
- the above-mentioned water or chemical solution which does not substantially contain hydrogen peroxide which easily oxidizes the W film. Even if it contains a small amount of hydrogen peroxide, when the concentration of hydrogen peroxide at a concentration of 30% by weight is set to 100%, the volume ratio of hydrogen peroxide is 0.3% or more. Those not included should be used.
- the efficiency of removing contamination can be further increased by applying mechanical vibration such as ultrasonic waves.
- mechanical vibration such as ultrasonic waves.
- the electric double possible to the water one S I_ ⁇ 2 interface It is considered that the effect of removing adhering wo x by the layer and the electrokinetic potential ( ⁇ ⁇ potential () potential) of the flowing water will increase the pollution reduction effect.
- the W film exposed to the reducing atmosphere in the reoxidation process is more easily oxidized than the normal W film, and thus the above cleaning should be performed immediately after the reoxidation treatment.
- measures to prevent oxidation due to contact with the air being transported such as by directly connecting the oxidation furnace to the cleaning device, are also effective.
- FIG. 22 is a graph showing the result of measuring the effect of removing the natural oxide film formed on the surface of the W film by washing with water using total reflection X-ray fluorescence.
- the W film those formed at room temperature and those formed at 500 ° C. were used.
- the W film formed at 500 ° C. has a higher crystallinity than the W film formed at room temperature, and is characterized in that a natural oxide film is hardly formed.
- the natural oxide film increases as the water temperature rises from room temperature, but when the temperature exceeds about 60 ° C, the cleaning effect is greater than the increase in the natural oxide film, so the removal effect is reduced.
- the natural oxide film increases as the water temperature rises from room temperature, but when the temperature exceeds about 60 ° C, the cleaning effect is greater than the increase in the natural oxide film, so the removal effect is reduced.
- the temperature of the water or the chemical at the time of washing is from room temperature to less than 50 degrees Celsius, or 70 degrees Celsius or more, and more preferably, from room temperature to less than 45 degrees Celsius, or 75 degrees Celsius or more.
- the natural oxide film can be efficiently removed.
- the upper part of the p-type well 3 is covered with a photoresist film 28, and B (boron) is ion-implanted into the n-type well 4.
- B boron
- As arsenic
- the dose of B and As is, for example, 3 ⁇ 10 13 atoms Z cm 2 .
- the surface of the substrate 1 is wet-cleaned in order to remove the racing residue attached to the surface of the substrate 1. Since this wet cleaning needs to be performed under the condition that the W film (25) exposed on the side walls of the gate electrodes 7A, 7B, and 7C is not oxidized, the wet cleaning used in the cleaning step immediately after the reoxidation process is performed. Use pure water or chemicals.
- the substrate 1 is heat-treated by lamp annealing for about 10 seconds to electrically activate the impurities, thereby forming the gate electrode as shown in FIG. 25.
- An rr-type semiconductor region 9 is formed in the p-type well 3 on both sides of 7 A and 7 B
- a ⁇ -type semiconductor region 10 is formed in the n-type well 4 on both sides of the gate electrode 7C.
- the above-mentioned heat treatment for activating the impurities causes sublimation from the side walls of the gate electrodes 7A, 7B, and 7C, and a very small amount of the contamination from the side surfaces of the gate electrodes 7A, 7B, and 7C.
- the surface of the substrate 1 may be washed for the purpose of removal. For this cleaning, it is desirable to use the pure water or the chemical used in the cleaning step immediately after the reoxidation process.
- a nitride silicon film 11 having a thickness of about 5 O nm is deposited on the substrate 1.
- the silicon nitride film 1 1 deposited by, for example, monosilane (S i H 4) and Ann Monia (NH 3) and the low-pressure C VD method using a source gas.
- the flow of forming the silicon nitride film 11 is, for example, as follows.
- the wafer 1 is loaded into a chamber of a low-pressure CVD apparatus previously filled with nitrogen.
- the preheating temperature in the chamber should be less than 500 ° C.
- ammonia which is a part of the source gas
- the inside of the chamber is set to an atmosphere in which W oxide is reduced.
- the wafer 1 is heated to a temperature of 600 ° C. or more, for example, 70 ° C. to 780 ° C., while continuously supplying ammonia into the chamber.
- ammonia and monosilane are supplied into the chamber, and these gases are reacted to deposit a silicon nitride film 11.
- the deposition time of the silicon nitride film 11 is about 10 minutes.
- the temperature of wafer 1 was lowered to less than 500 ° C., for example, 400 ° C. while only supplying ammonia to the chamber, and then the inside of the chamber was replaced with nitrogen. To unload. If the temperature at which the chamber is switched from the ammonia gas atmosphere to the nitrogen gas atmosphere is high, the W film 25 on the side walls of the gate electrodes 7A, 7B, and 7C and the oxide film remaining without being reduced There is a risk that 27 will sublime. Therefore, it is more preferable that the replacement of the ammonia gas with the nitrogen gas is performed after the temperature of the wafer 1 is lowered to about 300 ° C. to about 200 ° C.
- the temperature of the wafer 1 is reduced to about 100 ° C., and more preferably to 70 ° C. to room temperature. It is needless to say that the switching to the nitrogen gas atmosphere can suppress the oxidation of the W film 25 from then on.
- the gate electrode 7 By depositing the silicon nitride film 11 by the method described above, the gate electrode 7
- the W film 25 and the WN X film 24 constituting A, 7B, and 7C can be formed without oxidation.
- the silicon nitride film 11 can be deposited in a warm atmosphere.
- the temperature of the wafer 1 is increased under the condition that the oxide 27 on the side walls of the gate electrodes 7A, 7B, and 7C is reduced, the amount of the oxide 27 sublimated in the chamber is kept at an extremely low level. Accordingly, the contamination of the substrate 1 in the step of forming the silicon nitride film 11 can be kept at an extremely low level.
- the temperature of the wafer 1 was raised and lowered in an ammonia atmosphere, but other gases capable of reducing oxides of W, for example, hydrogen, C ⁇ , N 20, etc.
- the temperature of the wafer 1 may be raised and lowered in the above gas atmosphere.
- a rare gas such as argon (Ar), helium (He), or xenon (X ⁇ ) can be used as a purge gas.
- a mixed gas of dichlorosilane (SiH 2 Cl 2 ) and ammonia can be used as a source gas.
- the silicon nitride film 11 can be deposited by a plasma CVD method instead of the low pressure CVD method.
- the plasma CVD method has the advantage that a film can be formed at a lower temperature (400 ° C; up to 500 ° C) than the low-pressure CVD method. Film densities are inferior to low pressure CVD. Also in this case, by raising and lowering the temperature in an atmosphere in which the W oxide is reduced, the contamination of the substrate 1 in the step of forming the silicon nitride film 11 can be kept at an extremely low level.
- the oxide formed on the surface of the W film 25 in a preceding process is removed by removing the plasma in a reducing atmosphere containing the aforementioned ammonia or hydrogen. After the treatment, it is effective to form a film.
- the process after depositing the silicon nitride film 11 will be briefly described.
- the upper portion of the substrate 1 of the memory array is covered with a photoresist film (not shown), and the silicon nitride film 11 of the peripheral circuit portion is anisotropically etched to form a peripheral region.
- Sidewall spacers 11c are formed on the side walls of the gate electrodes 7B and 7C of the circuit section.
- a high impurity concentration n + type semiconductor region (source, drain) 12 is formed by ion-implanting As or P into the p-type well 3 in the peripheral circuit section, and B-type semiconductor 4 is formed in the n-type well 4.
- p + -type semiconductor regions (source and drain) with a high impurity concentration.
- a photoresist film (FIG.)
- the silicon film 11 on the n-type semiconductor region 9 is removed by dry etching using a mask (not shown), and the contact holes 16 and 17 are formed by exposing the surface of the n-type semiconductor region 9. I do.
- the silicon nitride film 11 is etched under such conditions that the etching rate of the silicon nitride film 11 with respect to the silicon nitride film 5 embedded in the element isolation groove 2 is increased, so that the element isolation groove 5 is not etched deeply.
- a plug 18 is formed inside the contact hole 1617.
- a P-doped polycrystalline silicon film is deposited inside the contact holes 16 and 17 and on the interlayer insulating film 15 by a CVD method, and then, on the interlayer insulating film 15. Unnecessary polycrystalline silicon film is removed by dry etching.
- the substrate 1 is heat-treated in a nitrogen gas atmosphere, and P in the polycrystalline silicon film forming the plug 18 is diffused into the n ⁇ type semiconductor region 9, thereby forming the low resistance n-type semiconductor region 9 ( Source and drain) are formed.
- the MISFETQt for memory cell selection is formed in the memory array.
- an oxidized silicon film 19 is deposited on the interlayer insulating film 15 by a CVD method, and the periphery thereof is dry-etched using a photoresist film (not shown) as a mask.
- Oxidation silicon film 19 in the circuit section and interlayer insulation beneath it By dry etching the edge film 15, a contact hole 21 is formed above the source and drain (n + type semiconductor region 12) of the n-channel MISFETQ n, and the source and drain of the p-channel MISFETQ p
- a contact hole 22 is formed above the (p + type semiconductor region 13).
- a through hole 20 is formed above the contact hole 16 by etching the silicon oxide film 19 of the memory array.
- plugs 23 are formed inside the contact holes 21 and 22 formed in the peripheral circuit portion and the through holes 20 formed in the memory array.
- the TiN film and the W film are formed on the silicon oxide film 19 including the insides of the contact holes 21 and 22 and the through hole 20 by the sputtering method and the CVD method. After depositing the film, the unnecessary W film and TN film on the silicon oxide film 19 are removed by chemical mechanical polishing.
- a bit line BL is formed on the silicon oxide film 19 of the memory array, and wirings 30 to 33 are formed on the silicon oxide film 19 of the peripheral circuit portion.
- Bidzuto line BL and the wiring 3 0-3 3 for example Supadzu on the silicon oxide film 1 9 evening depositing the W film and the WN X film ring method, these films in Delahaye Dzuchingu using a photoresist film as a mask It is formed by patterning.
- an interlayer insulating film 40 composed of a spin-on glass film and two silicon oxide films is formed on the bit line BL and the wirings 30 to 33, Subsequently, the through-glove insulating film 40 and the underlying silicon oxide film 19 are dry-etched to form a through-hole 43 above the contact hole 17, and then a polycrystalline silicon film is formed inside the through-hole 43. A plug 4 of 4 is formed. To form the plug 44, a P-doped polycrystalline silicon film is deposited inside the through hole 43 and on the interlayer insulating film 40 by CVD, and then the upper portion of the interlayer insulating film 40 is formed. Unnecessary polycrystalline silicon film is removed by dry etching.
- a silicon nitride film 45 is deposited on the interlayer insulating film 40 by a CVD method, and subsequently, a silicon nitride film 45 is deposited on the silicon nitride film 45 by a CVD method.
- the silicon oxide film 46 of the memory array is dry-etched using the photoresist film as a mask, and then the silicon nitride film 45 below it is dried. By performing etching, a groove 47 is formed above the through hole 44.
- the lower electrode 48 of the information storage capacitor C made of a polycrystalline silicon film is formed on the inner wall of the groove 47.
- an amorphous silicon film (not shown) doped with P (phosphorus) is formed by a CVD method inside the groove 47 and above the silicon oxide film 46. After the deposition, the unnecessary amorphous silicon film on the silicon oxide film 46 is removed by dry etching.
- the information storage capacitor C is formed on the surface of the lower electrode 48 formed inside the groove 47 and the surface of the silicon oxide film 46 outside the groove 47.
- a T i N film as the T a 2 0 5 upper electrode 5 0 upper portion of the information storage capacitor C of the film, and T a 2 0 5 film and T i N film in the peripheral circuit portion Is removed by etching.
- an oxidized silicon film 50 is deposited on the information storage capacitor C by the CVD method, and about two layers of A1 wiring (not shown) are formed on the silicon film 50 by the CVD method.
- the DRAM of the present embodiment shown in FIG. 3 is completed.
- This embodiment is applied to a mouthpiece-mixed DRAM.
- An example will be described in the order of steps with reference to FIGS.
- the left part of each cross-sectional view showing the manufacturing method shows a part of a DRAM memory array, and the right part shows a part of a logic part.
- a p-type well 3 is formed on a part of the substrate 1 and an n-type well 4 is formed on the other part, and then the substrate 1 is steam-oxidized to form a p-type well 3 and an n-type well 4 on the surface.
- a clean gate insulating film 6 made of a silicon oxide film having a thickness of about 6 nm is formed.
- the gate insulating film 6 may be formed of a silicon oxynitride film, a silicon nitride film, a composite insulating film of the silicon oxide film and the silicon nitride film instead of the silicon oxide film. .
- a non-doped amorphous silicon film 14a is deposited on the gate insulating film 6.
- the amorphous silicon film 14a is deposited by, for example, a CVD method using monosilane (SiH 4 ) as a source gas, and has a thickness of about 70 nm.
- the deposition temperature is set to 500 ° C! Set to within 550 ° C, for example, 530 ° C.
- the film formation temperature is set to 600 ° C. or higher, a polycrystalline silicon film 14n is obtained as in the first embodiment.
- amorphous silicon film 14a is obtained.
- a silicon film containing Ge germanium up to about 50% may be used.
- an amorphous silicon film containing Ge can be obtained by depositing a polycrystalline silicon film by the CVD method and then introducing Ge into the polycrystalline silicon film by an ion implantation method.
- the logic-embedded DRAM of the present embodiment uses one of the gate electrodes of the n-channel MISFET because the n-channel MISFET and the p-channel MISFET of the logic part are both surface channel MISFETs.
- the polycrystalline silicon film, which is the part is composed of n-type, and the polycrystalline silicon film Construct a p-type membrane.
- a non-doped polycrystalline silicon film is deposited on top of the gate insulating film 6, and then boron (B) ions are added to make the polycrystalline silicon film in the p-channel type MISFET formation region P-type.
- B boron
- a part of boron may penetrate through the polycrystalline silicon film and the gate insulating film 6 due to a channeling phenomenon, and may be introduced into the channel region of the substrate 1.
- a part of the gate electrode of the p-channel type MISFET is formed of a P-type polycrystalline silicon film as in the present embodiment, it is desirable to use the above-mentioned amorphous silicon film 14a in which the channeling phenomenon does not easily occur.
- the silicon film of all the gate electrodes (7A, 7B, 7C) is composed of an n-type conductive silicon film as in the DRAM of the first embodiment, the boron penetration described above is performed. Therefore, a polycrystalline silicon film may be used instead of the amorphous silicon film 14a.
- the upper part of the p-type well 3 is covered with a photoresist film 60, and B (boron) is ion-implanted into the amorphous silicon film 14a on the upper part of the n-type well 4.
- the dose amount of B is, for example, 2 ⁇ 10 15 at oms / cm 2
- the implantation energy is, for example, 5 keV.
- the upper part of the n-type well 4 is covered with a photoresist film 61, and the amorphous silicon film 14a on the upper part of the p-type well 3 is formed.
- P phosphorus
- the dose amount of P is, for example, 2 ⁇ 10 15 at oms / cm 2 ⁇ , and the injection energy is, for example, 10 keV.
- the photoresist film 61 is removed by ashes, the surface of the polycrystalline silicon film 14n is washed with hydrofluoric acid, and a lamp anneal is performed for about 1 minute in a nitrogen atmosphere at about 950 ° C. Then, the amorphous silicon film 14a is crystallized and the impurities (B and P) are electrically activated. As a result, as shown in FIG. 42, the amorphous silicon film 14a in the n-channel MISFET formation region becomes the n-type polycrystalline silicon film 14n, and the amorphous silicon film 14a in the p-channel MISFET formation region becomes It becomes a p-type polycrystalline silicon film 14p.
- a heat treatment for crystallizing the amorphous silicon film 14a is performed.
- the stress change caused by the crystallization there is a possibility that WN X film or W film may peel off.
- the above heat treatment is preferably performed before depositing the WN X film and W film on the amorphous silicon film 1 4 a.
- an amorphous silicon film is formed on the polycrystalline silicon films 14 n and 14 p.
- a recon film 34a is deposited.
- the amorphous silicon film 34a has an extremely low impurity concentration of less than 1.0 ⁇ 10 17 cm 3 or substantially less than 1.0 ⁇ 1 O w cm 3 . It is composed of non-doped amorphous silicon.
- the amorphous silicon film 34a is used to block the contact between the extremely thin native oxide film formed on the surface of the polycrystalline silicon films 14n and 14p and the WN X film 2 deposited on the upper surface in the next step. Formed.
- the amorphous silicon film 34a does not need to be in a completely amorphous state, and may be, for example, an aggregate of extremely small silicon crystal grains.
- the WN X film 24 is formed on the amorphous silicon film 34a by a sputtering method.
- a W film 25 is successively deposited, and a silicon nitride film 8 is deposited on the W film 25 by CVD.
- the thickness of the WN X film 24 is set to about 5 nm to 1 O nm.
- the thickness of the W film 25 deposited on the WN X film 24 is about 70 nm to 80 nm, and the thickness of the silicon nitride film 8 is about 16 O nm.
- a Mo film may be deposited instead of the W film 25.
- an atmosphere in which the WN X film 24 contains a high concentration of nitrogen is used.
- the film may be formed in an atmosphere. That is, the sputtering may be performed by setting the atmosphere in the chamber to a gas atmosphere in which the flow ratio of nitrogen gas to argon gas is 1.0 or more.
- a nitrogen gas flow rate of 50 sccm to 80 sccm, an argon gas flow rate of 20 sccm to 30 sccm, a vacuum degree of the chamber 0.5 Pa, and a temperature of 200 to 500 ° C Film formation is performed under the conditions.
- the thickness of WN X film 24 at the time of film formation is preferably in the range from 10 nm 5 nm.
- the thickness of the WN X film 24 at the time of film formation is preferably in the range from 10 nm 5 nm.
- WN X to film 24 even when a film was formed in an atmosphere such as high concentration of nitrogen is included, because the excess nitrogen in the heat treatment step after the film formation is disengaged from diffusing, upon device finished 1 ⁇
- the film 24 is mainly composed of stoichiometrically most stable W 2 N.
- the silicon nitride film 8 As shown in FIG. 45, using the photoresist film 62 formed on the silicon nitride film 8 as a mask, the silicon nitride film 8, the WE24 WN X E25 N amorphous silicon film 34a and the polycrystalline silicon film are formed. 14n and 14p are sequentially dry-etched to form a gate electrode 7A (lead line WL) on the gate insulating film 6 of the memory array and gate electrodes 7D and 7E on the gate insulating film 6 of the logic area. I do.
- a memory cell selecting MI SFET Qt is formed in the memory array by the method described in the first embodiment, and an n-channel MISFET and a p-channel MI SFET are formed in the logic section. Also in this case, the re-oxidation process, the cleaning process, the deposition of the silicon nitride film, etc. of the gate insulating film 6 are performed in the same manner as in the first embodiment, so that the contamination of 1 by the oxide of W is extremely low. Can be kept. 4 6, the relationship between the crystal structure of the gate electrode 7 A, 7 D, the nitrogen flow rate of 7 when it forms a WN X film 2 4 constituting a part of the E and WN X film 2 4, WN X FIG.
- FIG. 9 is a graph showing the results of X-ray diffraction measurement immediately after film 24 was formed and after heat treatment was performed in nitrogen gas at 950 ° C. for 1 minute.
- nitrogen flow rate when forming the WN X film 24 is set to 10 sccm
- nitrogen in the WN X film 24 is released in the process of the high-temperature heat treatment to become a W film.
- the function of the WN X film 2 as a barrier layer was lost.
- Figure 48 shows the results of examining the relationship between the breakdown voltage of the gate electrode including the WN X film and the contact resistance at the interface between the WN X film and the polycrystalline silicon film while changing the flow ratio of nitrogen gas and argon gas. Is shown. As shown, when the WN X film, which was formed under the conditions the flow ratio is small of the nitrogen gas, the breakdown voltage of the gate electrode is reduced, the contact resistance of the WN X film / polysilicon film interface is increased.
- N is remaining in the WN X film even after the heat treatment step because, there is no possibility that the function as a barrier layer of WN X film 2 4 is lost.
- an amorphous silicon film 34a between the WN X film 24 and the polycrystalline silicon films 14n and 14p it is formed on the surface of the polycrystalline silicon films 14n and 14p. the formation of the high resistance layer due to contact between the extremely thin natural oxide film and the WN X film 2 4 can be suppressed.
- the amorphous silicon film 34a that has undergone the heat treatment process becomes a polycrystalline film having a smaller average crystal grain size than the underlying polycrystalline silicon films 14n and 14p.
- the contact resistance at the interface between the WN X film 24 and the polycrystalline silicon films 14 n and 14 p constituting the gate electrodes 7 A, 7 D, and 7 E is reduced by 5 k before the countermeasure. From lk Q / ⁇ m 2 .
- the re-oxidation process, the cleaning process, the deposition of the silicon nitride film, and the like of the gate insulating film 6 are performed in the same manner as in the first embodiment, so that the contamination of the substrate 1 by the oxide of W is extremely low.
- the WN X film 24 and the polycrystalline silicon films 14 n and 14 p are formed by interposing the amorphous silicon film 34 a between the WN X film 24 and the polycrystalline silicon films 14 n and 14 p. was reduced in the contact resistance, in the present embodiment, by interposing a thin film thickness of W film 62 between the WN x film 24 and the polycrystalline silicon film 14 n, 14p, WN X film 24 and the multi Reduces contact resistance with crystalline silicon films 14n and 14p.
- an n-type polycrystalline silicon film 14n is formed on the gate insulating film 6 in the n-channel type MISF ET formation region, and the p-channel type MISFET formation region is formed.
- a p-type polycrystalline silicon film 14p is formed on the gate insulating film 6. The steps so far are the same as the steps shown in FIGS. 38 to 42 of the second embodiment.
- a W film 65 is deposited on the polycrystalline silicon films 14n and 1 as shown in FIG.
- the film 65 is deposited by, for example, a sputtering method, and has a thickness of about 5 nm.
- WN X 2 is sequentially deposited WN X 2, W film 25 and the silicon nitride film 8 in the same manner as in the second embodiment the upper portion of the W film 65.
- the thickness of the WN X film 24 is about 5 nm to 10 nm
- the thickness of the W film 25 is about 70 nm to 80 nm
- the thickness of the silicon nitride film 8 is about 16 Onm.
- a Mo film may be deposited instead of the W film 25.
- WN X film 24 the same as in the second embodiment performs a deposition in an atmosphere such as contain high concentrations of nitrogen, nitrogen elemental composition when the device completed at least 7% to 10% or more, preferably Should be 13% or more, more preferably 18% or more. Subsequent steps are the same as in the second embodiment.
- the W film 62 between the WN X film 24 and the polycrystalline silicon films 14n and 14p react during the subsequent heat treatment. and, a conductive layer consisting mainly of W silicide (WS i x) is formed.
- WS i x W silicide
- the contact resistance at the interface between the WN X film 24 constituting the gate electrodes 7A, 7D and 7E and the polycrystalline silicon films 14n and 14p is reduced to 5 k ⁇ / ⁇ 2 11 before the countermeasure.
- OkQ / m 2 could be reduced to 1 k ⁇ / ⁇ 2 .
- the re-oxidation process, the cleaning process, the deposition of the silicon nitride film, and the like of the gate insulating film 6 are performed in the same manner as in the first embodiment, so that the contamination of the substrate 1 by the oxide of W is extremely low. As a result, the DRAM refresh time was significantly improved.
- the W film 62 is interposed between the WN X film 24 and the polycrystalline silicon films 14 n and 14 p, and the W film 62 and the polycrystalline silicon films 14 n and 14 p was conductive layer formed mainly of W silicide by reacting the door, polycrystalline silicon film 14n, 14 p upper thin W silicide film is formed, and a WN X film 24 and W film 25 thereon It may be deposited.
- the W silicide layer is formed by reacting the W film 62 with the polycrystalline silicon films 14n and 14p during the heat treatment, the reaction may occur locally and the gate breakdown voltage may decrease. Such a local reaction is unlikely to occur when a W silicide film is deposited.
- the thickness of the W silicide film may be about 5 nm to 20 nm.
- X of WSi x is preferably about 2.0 to 2.7.
- the present embodiment is applied to a CMOS logic LSI in which a circuit is constituted by an n-channel MISFET and a p-channel MISFET, and an example of a manufacturing method thereof will be described in the order of steps with reference to FIGS. 52 to 56. .
- a substrate 1 made of, for example, p-type single crystal silicon is provided, and an element isolation groove 2 and a p-type substrate are formed on the main surface of the substrate 1 in the same manner as in the first embodiment.
- a well 3, an n-type well 4, and a gate insulating film 6 are sequentially formed.
- a low-resistance n-type polycrystalline silicon film 1 doped with P (phosphorus) at a concentration of 1.0 ⁇ 10 19 cm 3 or more is formed on the gate insulating film 6.
- a WN X having a film thickness of about 5 nm to 10 nm is formed on the polycrystalline silicon film 14 n by a sputtering method.
- the film 24 is deposited.
- WN X film 2 4 high concentration perform film formation at Kiri ⁇ gas as contained nitrogen, nitrogen elemental composition during device completed at least 7% to 1 0% or more, It is preferably at least 13%, more preferably at least 18%.
- the WN x film 24 is deposited to a thickness such that the remaining film thickness when the device is completed is at least 1 nm.
- WN X film 2 A W film 62 may be formed between 4 and the polycrystalline silicon film 14 ⁇ .
- ⁇ (phosphorus) is ion-implanted into the main surface of the substrate 1.
- This ion implantation is performed with energy such that ⁇ penetrates the WN X film 24 and reaches a region of 1 O nm or less from the surface of the polycrystalline silicon film 14 n.
- the thickness of the WN X film 24 is 3 ⁇ !
- the implantation energy of P is 2 keV to 10 keV.
- the P concentration in the surface region of the polycrystalline silicon film 14 n is 5 X
- the dose is set so as to be 10 19 atoms / cin 3 or more.
- lamp annealing is performed for about 1 minute in a nitrogen atmosphere at about 950 ° C. to electrically activate impurities ( ⁇ ) in the polycrystalline silicon film 14 ⁇ . You may do it. Since the impurities ( ⁇ ) in the polycrystalline silicon film 14 ⁇ are electrically activated in a subsequent heat treatment step, the heat treatment here may be omitted.
- the ion implantation is formed by depositing a polycrystalline silicon film 1 4 eta, it may be performed before the sedimentary the WN X film 2 4. Also, between the WN X film 24 and the polycrystalline silicon film 14 n When forming a W film 62 performs the ion implantation after the formation of the W film, then, it may be deposited WN X film 24 on top of the W film.
- a W film 25 having a thickness of about 70 nm is deposited on the WN X film 24 by a sputtering method, and then a 160 nm film thickness is formed on the W film 25 by a CVD method.
- a silicon nitride film 8 is deposited. Note that the top of the WN X film 24 may be deposited Mo layer in place of the W film 25.
- another ion implantation is performed on the main surface of the substrate 1, and P is doped into the polycrystalline silicon film 14 n through the W film 25 and the WN X film 24. The surface region may be further reduced in resistance.
- the photo registry film 63 as a mask the silicon nitride film 8 formed on the top of ⁇ I ⁇ silicon film 8, W film 24, WN X film 25 and the polycrystalline silicon S trillions 14
- a gate electrode 7F of an n-channel MISFET is formed on the p-type well 3
- a gate electrode 7G of a p-channel MISFET is formed on the n-type well 4.
- the gate insulating film 6 removed by the above-mentioned dry etching was subjected to the re-oxidation treatment, the subsequent cleaning treatment, and the deposition of the silicon nitride film. This is performed in the same manner as in the first embodiment.
- the polycrystalline silicon film which is a part of each of the gate electrodes 7 F and 7 G, is formed of the n-type.
- both the n-channel type MISFET and the p-channel type In order to form a gate electrode, the polycrystalline silicon film, which is a part of the gate electrode 7 F of the n-channel MISFET, is composed of n-type and is a part of the gate electrode 7 G of the p-channel MISFET.
- the polycrystalline silicon film may be of a p-type.
- a non-doped amorphous silicon film is deposited on the gate insulating film 6, and then the amorphous silicon in the n-channel MISFET formation region is formed by ion implantation using a photoresist film as a mask.
- the polycrystalline silicon film 14 is formed by ion implantation of impurities. Although the surface area of n has been reduced in resistance, the surface area of the polycrystalline silicon film 14n can be reduced in resistance by the following method.
- an element isolation groove 2 for example, an element isolation groove 2, a p-type well 3, an n-type well 4, and a gate insulating film 6 are sequentially formed on a main surface of a substrate 1 made of, for example, p-type single crystal silicon.
- P phosphorus
- a low-resistance n-type polycrystalline silicon film 6 having a concentration of 5.0 ⁇ 10 19 cm 3 or more doped with P is formed on the polycrystalline silicon film 14 n. 4 is deposited by CVD, the substrate 1 is heat-treated, and P in the n-type polycrystalline silicon film 64 is diffused from the surface of the polycrystalline silicon film 14n to a surface region of 10 nm or less.
- the P concentration in the surface region is set to 5 X 1 O 19 atoms / cm 3 or more.
- lamp annealing was performed for about 1 minute in a nitrogen atmosphere at about 950 ° C. to electrically activate P in the polycrystalline silicon film 14 n.
- the WN X film 24 is formed in an atmosphere containing a high concentration of nitrogen, and has a nitrogen element composition of at least 7% to 10% or more, preferably at the completion of the device, preferably It should be at least 13%, more preferably at least 18%. Further, WN X film 2 4 is deposited to a thickness such as residual film thickness when the device completed is at least 1 nm or more.
- WN X is used for the purpose of suppressing the formation of a high resistance layer due to contact between the natural oxidation film formed on the surface of the polycrystalline silicon film 14 n and the WN X film 24.
- a W film may be formed between 24 and the polycrystalline silicon film 14 n.
- a film thickness of 7 was formed on the WN X film 24 by sputtering.
- the film thickness 1 A silicon nitride film 8 of about m is deposited.
- a gate electrode 7F of an n-channel MISFET is formed on the p-type well 3
- a gate electrode 7G of a p-channel MISFET is formed on the n-type well 4.
- the gate insulating film 6 removed by the dry etching is subjected to a re-oxidation process, a subsequent cleaning process, and a deposition of a silicon nitride film. This is performed in the same manner as in the first embodiment.
- P in the polycrystalline silicon film 64 deposited on the polycrystalline silicon film 14 n is thermally diffused to reduce the resistance of the surface region of the polycrystalline silicon film 14 n.
- P is introduced into the surface region of the polycrystalline silicon film 14n by an ion implantation method, and then an insulating film such as an oxide silicon film is formed on the polycrystalline silicon film 14n and heat-treated. After the P introduced into the surface region of the polycrystalline silicon film 14n is segregated near the interface with the insulating film, the insulating film is removed to reduce the surface region of the polycrystalline silicon film 14n. You may do resistance.
- the insulating film is composed of, for example, an oxide silicon film formed by thermally oxidizing the surface of the polycrystalline silicon film 14 n, or a silicon oxide film deposited on the polycrystalline silicon film 14 n by the CVD method.
- the present invention is not limited to this.
- the present embodiment is applied to a flash memory, and an example of a manufacturing method thereof will be described in the order of steps with reference to FIGS.
- FIG. 63 after forming the element isolation groove 2, the p-type well 3, and the gate insulating film 6 on the main surface of the substrate 1 in the same manner as in the first embodiment, FIG. As shown in 65, a film thickness of 7 ⁇ !
- An n-type polycrystalline silicon film 66 n of about 10 O nm is deposited.
- the polycrystalline silicon film 66 n is doped with an n-type impurity, for example, phosphorus (P) during the deposition process.
- an n-type impurity may be doped by ion implantation after depositing a non-doped polycrystalline silicon film.
- the polycrystalline silicon film 66 n is the floating MISFET that constitutes the memory cell. Used as a gate electrode.
- the polycrystalline silicon film 66n is dry-etched using the photoresist film as a mask, so that the polycrystalline silicon film 66n extends over the active region L along the extending direction.
- a polycrystalline silicon film 66n having a long band-like planar pattern is formed.
- a 0NO film 67 made of a silicon oxide film, a silicon nitride film, and an oxidized silicon film is formed on the substrate 1 on which the polycrystalline silicon film 66n is formed.
- the film 67 is used as a second gate insulating film of a MISFET constituting a memory cell.
- a 5-nm-thick silicon oxide film and a 7-nm-thick silicon nitride film are formed on the substrate 1 by a CVD method. And a 4 nm-thick silicon oxide film.
- the n-type polycrystalline silicon film 14 n doped with syrup (phosphorus), the WN X M24, W film 25 and the nitride film 8 are sequentially deposited.
- Polycrystalline silicon film 14n, W film 25 and silicon nitride film 8 are deposited by the same method as in the first embodiment.
- WN X film 24 for reducing the contact resistance between Tayui crystal silicon film 14 n is deposited in the same way as the second embodiment. That, WN X film 24 is more than 7% to 10% even with less nitrogen elemental composition at the time element completion, preferably 13% or more, more preferably formed by so that conditions Do 18% or more.
- the thickness of the WN X film 24 at the time of film formation is preferably in the range from 5 nm to 10 nm.
- the contact resistance between the WN X film 24 and the polycrystalline silicon film 14 n to the low reduction may be employed a process described in Embodiment 3, 4 or 5 of the embodiment.
- the polycrystalline silicon film 14n is used as a control gate electrode and a lead line WL of a MISFET constituting a memory cell.
- the silicon nitride film 8 is used as an insulating film for protecting the upper part of the control gate electrode.
- the polycrystalline silicon film 14 ⁇ can also be composed of a silicon film containing Ge (germanium) up to around 50%.
- the photoresist formed on the silicon nitride film 8 Preparative layer ⁇ I ⁇ silicon film 8 to a (not shown) as a mask, ⁇ 2 4, WN X II 2 5 polycrystalline silicon film 1 4 n, ONO film 6 7 and polycrystalline silicon film 6 sequentially Dora the 6 n
- n-type semiconductor region 70 constituting the source and drain of the MISFET is formed.
- the n-type semiconductor region 70 is formed by implanting n-type impurities (for example, arsenic (A s)) into the p-type well 3 and then heat-treating the substrate 1 at about 900 ° C. to remove the n-type impurities. It is formed by diffusing into the p-type well 3.
- n-type impurities for example, arsenic (A s)
- the gate insulating film 6 in the space region of the gate electrode (the floating gate electrode 68 and the control gate electrode 69) is damaged by the gate electrode application process and the impurity ion implantation process. Has occurred. This damage sufficiently deteriorates the quality of the gate insulating film 6, such as a path in which electrons injected into the floating gate electrode 68 leak from the end of the floating gate electrode 68 to the substrate 1. It must be removed.
- a silicon nitride film 11 is deposited on the substrate 1 by a low pressure CVD method as shown in FIG.
- the contamination of the substrate 1 by the oxide of W can be kept at an extremely low level.
- the present invention is applied to a DRAM, a logic LSI with embedded DRAM, a CMOS logic LSI, and a flash memory has been described.
- the present invention can be widely applied to an LSI having a MISTFET having a gate electrode.
- the invention described in the present application is deeply tied to the polysilicon layer, so that it can be applied to a non-polysilicon metal gate electrode without a polysilicon layer unless the polysilicon layer is essential. Not even. Industrial applicability
- the present invention can be used, for example, for manufacturing an integrated circuit device having a polymetal gate.
Description
Claims
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/468,441 US7049187B2 (en) | 2001-03-12 | 2001-10-31 | Manufacturing method of polymetal gate electrode |
KR1020037011347A KR100653796B1 (ko) | 2001-03-12 | 2001-10-31 | 반도체 집적 회로 장치의 제조 방법 |
JP2002572641A JP4109118B2 (ja) | 2001-03-12 | 2001-10-31 | 半導体集積回路装置の製造方法 |
KR10-2004-7020408A KR20050004924A (ko) | 2001-03-12 | 2001-10-31 | 반도체 집적 회로 장치의 제조 방법 |
US11/198,858 US7144766B2 (en) | 2001-03-12 | 2005-08-08 | Method of manufacturing semiconductor integrated circuit device having polymetal gate electrode |
US11/553,690 US7300833B2 (en) | 2001-03-12 | 2006-10-27 | Process for producing semiconductor integrated circuit device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2001-69514 | 2001-03-12 | ||
JP2001069514 | 2001-03-12 |
Related Child Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10468441 A-371-Of-International | 2001-10-31 | ||
US11/198,858 Continuation-In-Part US7144766B2 (en) | 2001-03-12 | 2005-08-08 | Method of manufacturing semiconductor integrated circuit device having polymetal gate electrode |
US11/198,858 Continuation US7144766B2 (en) | 2001-03-12 | 2005-08-08 | Method of manufacturing semiconductor integrated circuit device having polymetal gate electrode |
Publications (1)
Publication Number | Publication Date |
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WO2002073696A1 true WO2002073696A1 (fr) | 2002-09-19 |
Family
ID=18927541
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2001/009547 WO2002073696A1 (fr) | 2001-03-12 | 2001-10-31 | Procede pour fabriquer un dispositif semi-conducteur a circuit integre |
Country Status (6)
Country | Link |
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US (3) | US7049187B2 (ja) |
JP (2) | JP4109118B2 (ja) |
KR (2) | KR20050004924A (ja) |
CN (2) | CN1290197C (ja) |
TW (1) | TW536753B (ja) |
WO (1) | WO2002073696A1 (ja) |
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JP2012174790A (ja) * | 2011-02-18 | 2012-09-10 | Elpida Memory Inc | 半導体装置及びその製造方法 |
JP2022504926A (ja) * | 2018-10-18 | 2022-01-13 | アプライド マテリアルズ インコーポレイテッド | ビット線抵抗低減のためのキャップ層 |
JP7303874B2 (ja) | 2018-10-18 | 2023-07-05 | アプライド マテリアルズ インコーポレイテッド | ビット線抵抗低減のためのキャップ層 |
Also Published As
Publication number | Publication date |
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CN100447980C (zh) | 2008-12-31 |
US7300833B2 (en) | 2007-11-27 |
CN1505840A (zh) | 2004-06-16 |
TW536753B (en) | 2003-06-11 |
US20070048917A1 (en) | 2007-03-01 |
KR20050004924A (ko) | 2005-01-12 |
JP4607197B2 (ja) | 2011-01-05 |
CN1941324A (zh) | 2007-04-04 |
JPWO2002073696A1 (ja) | 2004-07-08 |
JP2008211212A (ja) | 2008-09-11 |
US7049187B2 (en) | 2006-05-23 |
KR100653796B1 (ko) | 2006-12-05 |
US7144766B2 (en) | 2006-12-05 |
JP4109118B2 (ja) | 2008-07-02 |
CN1290197C (zh) | 2006-12-13 |
KR20030080239A (ko) | 2003-10-11 |
US20040063276A1 (en) | 2004-04-01 |
US20060009046A1 (en) | 2006-01-12 |
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