WO2002075343A1

WO2002075343A1 - Ate calibration method and corresponding test equipment

Info

Publication number: WO2002075343A1
Application number: PCT/US2002/008145
Authority: WO
Inventors: Paul Roush; Paul R. Hatmaker; Michael Gebis; Kurtis S. Araki
Original assignee: Teradyne, Inc.
Priority date: 2001-03-19
Filing date: 2002-03-14
Publication date: 2002-09-26
Also published as: TWI220934B

Abstract

A method of calibrating a semiconductor tester is disclosed. The method includes first selecting at least one golden device having known electrical characteristics and a plurality of failure mechanisms. The at least one golden device is then interfaced to the plurality of channels. Following the interface step, the tester channels are characterized in parallel with edge-specific tester waveforms. The edge-specific tester waveforms are operative to isolate a specific subset of the plurality of failure mechanisms and generate specific characterization data. The edge-specific characterization data is then compared to the known electrical characteristics to detect edge parameter inconsistencies. After the comparing step, the plurality of channels are tuned to minimize the edge parameter inconsistencies.

Description

ATE CALIBRATION METHOD AND CORRESPONDING TEST EQUI PMENT

FIELD OF THE INVENTION The invention relates generally to automatic test equipment and more particularly a calibration method that utilizes "golden devices" and calibration waveforms to characterize semiconductor tester parameters accurately and quickly.

BACKGROUND OF THE INVENTION Semiconductor device manufacturing typically includes test processes at both the wafer and packaged-device levels. The testing is normally carried out by automatic test equipment (ATE) that simulates a variety of operating conditions to verify the functionality of each device. As modern semiconductor device performance levels increase, device manufacturers place increasing importance on ATE accuracy to maximize device yields.

Referring now to Figure 1, a typical semiconductor tester, generally designated 10, includes a tester controller 12 such as a mainframe or PC to execute a test program for controlling device testing. Pin electronics 20 (Figure 2) for generating, delivering and receiving tester signals to and from one or more devices-under-test (DUTs) 14 are generally disposed remotely from the controller inside a test head 16 and positioned proximate the DUTs to minimize tester signal propagation delays. The tester pin electronics often comprises from several hundred to over one-thousand channels that couple to a corresponding number of DUT input/output (I/O) and address/clock (A/CLK) pins via a tester interface 18. Figure 2 illustrates a high-level signal path, or channel, between the pin electronics 20 and the DUT 16. Transmission lines 22 and conductive traces formed on a device interface board (DIB) 24 route signals between the pin electronics and the DUTs in an effort to maintain a fifty-ohm environment. Although the pin electronics are positioned near the DUTs, the various signals propagating along the transmission lines and PCB traces between the electronics and the DUT are nevertheless susceptible to various forms of signal degradations.

To minimize the signal degradations noted above, a semiconductor tester usually undergoes regular calibration to ensure that test results are reliable and repeatable to a high degree of precision and accuracy. One conventional calibration scheme involves the use of "golden devices", such as that described in U.S. Patent No. 6,032,107 to Hitchcock. Golden devices are semiconductor devices similar to those being tested, and whose characteristics are known and can thus define a "standard" or reference. By using the golden devices, the signal path uncertainties attributable to the pin electronics and the tester-to-DUT interface can be detected and calibrated out. While the conventional golden DUT calibration (GDC) method works well for its intended low-accuracy applications, for high-accuracy implementations the method appears problematic. A typical problem with the conventional GDC method involves using regular test patterns to calibrate tester channels. Normal tester patterns are designed to stress a semiconductor device and attempt to identify multiple fail mechanisms (such as "stick-to" fails or cell-to-cell "bleeding"). For tester calibration procedures, however, the aim is to measure the performance of the tester. Consequently, when attempting to calibrate a semiconductor tester with golden devices and conventional test programs, accuracy often suffers because of the large number of unisolated edge parameter variables. What is needed and heretofore unavailable is a calibration method that utilizes golden devices to calibrate edge parameters of a tester waveform accurately and cost- effectively. The method of the present invention satisfies these needs.

SUMMARY OF THE INVENTION

The ATE calibration method of the present invention provides a high- accuracy and fast tester calibration scheme using conventional golden devices for existing tester hardware. As a result, semiconductor tester hardware already employed in the field may be easily upgradeable to higher accuracy specifications by merely upgrading the tester software.

To realize the foregoing advantages, the invention in one form comprises a method of calibrating a semiconductor tester having a plurality of channels. The method includes first selecting at least one golden device having known electrical characteristics and a plurality of failure mechanisms. The at least one golden device is then interfaced to the plurality of channels. Following the interface step, the tester channels are characterized in parallel with edge-specific tester waveforms. The edge- specific tester waveforms are operative to isolate a specific subset of the plurality of failure mechanisms and generate specific characterization data. The edge-specific characterization data is then compared to the known electrical characteristics to detect edge parameter inconsistencies. After the comparing step, the plurality of channels are tuned to minimize the edge parameter inconsistencies.

In another form, the invention comprises semiconductor tester software for operating a semiconductor tester. The tester software includes a test program including pattern and control data for testing one or more semiconductor devices and a control code library. The tester software further includes golden device calibration software for calibrating a plurality of tester channels. The golden device calibration software includes a golden DUT calibration control file for programming calibration control commands, and a golden DUT calibration pattern file having edge-specific pattern data for applying to said golden DUT, according to said GDC control file.

Other features and advantages of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be better understood by reference to the following more detailed description and accompanying drawings in which

FIG. 1 is a block diagram of a semiconductor test system according to one form of the present invention;

FIG. 2 is a generalized block diagram of the tester interface shown in Figure 1;

FIG. 3 is a block diagram of a program structure according to one embodiment of the present invention;

FIG. 4 is a flowchart illustrating steps employed in the method of the present invention; and

FIG. 5 is a flowchart of the parallel searching step shown in Figure 4.

DETAILED DESCRIPTION OF THE INVENTION

The method of the present invention provides a way of calibrating a semiconductor tester, such as that shown in Figure 1, with golden devices to a high degree of accuracy while minimizing calibration run-time. Generally, this is done by applying edge-specific calibration test patterns to the golden device pins, in parallel, to isolate specific fail mechanisms that can be accurately detected by the tester. By isolating specific fail mechanisms relating to certain edge parameters, the tester can be finely tuned to provide very high accuracy. Moreover, since the calibration is performed on multiple channels in parallel, calibration run-time is significantly minimized.

With reference to Figures 1 and 2, the ATE calibration method of the present invention employs conventional hardware in the form of a semiconductor tester and "golden devices", as those terms are understood in the art. The inventors have discovered a beneficial way of operating the tester and golden devices through unique software that enhances accuracy with minimal calibration run-time.

Referring now to Figure 3, the conventional hardware noted above is controlled by and responds to an overall tester software package 30. The general architecture of the overall software package includes a production test program 32 for controlling standard production device testing, a control code library 34 for managing control operations, and calibration software including a golden DUT calibration

(GDC) control file 36, and a GDC pattern file 38. The calibration software is more fully described below in conjunction with the steps that carry out the method of the present invention.

With reference now to Figure 4, the ATE calibration method generally begins by first loading the "golden devices" into respective device-interface-board (DIB) sockets (not shown), at step 40. The DIB and the sockets form a portion of the tester interface that often contributes significant signal degradations that are minimized by the present invention. The tester calibration software is then informed of the golden DUT types, at step 42, in order to access the appropriate "golden" characterization files associated with the devices from the GDC calibration pattern file 38 (Figure 3).

The GDC control file 36 (Figure 3), in particular, maintains information on the specific calibration waveforms that should be used to maximize calibration accuracy for a given golden device.

Once the golden devices and appropriate test procedures (patterns) are identified and ready, the tester channels are characterized in parallel, at step 44, by applying the same calibration pattern over a plurality of tester channels to the same corresponding golden device pins. More specifically, for the case where thirty-two 64-pin golden devices are loaded in respective DUT sockets, the same calibration pattern will be fed to the same pin for all thirty-two devices in parallel. For a given pin, several calibration patterns may be applied to and captured from the device in order to separately isolate and "tune" specific tester edge parameters. Different tester edge parameters may include, for example, rising/falling edges for many drive/compare edge generators. The possible combinations may be multiplied if multiple signal paths are employed (for multiplexing). Referring now to Figure 5, the characterization step 44 in further detail comprises a parallel edge search algorithm that advantageously reduces calibration time by automatically storing and using previously detected search information. The algorithm for a specific edge parameter at all thirty-two sites includes first selecting a time interval, at step 50, where the edge is expected to be located. Within the time interval, a specific point is selected, at step 52, for taking the first sampling of data. One of the sites is then identified as the controlling site, at step 54. As the controlling site, pass/fail determinations are made for that site (and also for the other sites in parallel), and continue for that site until the edge is found. Once the controlling site is identified, the algorithm looks to a memory (not shown) in the tester to see whether the pass/fail condition for that point has in fact already been detected and stored, at step 56.

If the pass/fail information hasn't been determined or stored, then the algorithm directs the tester pattern generator to apply an edge-specific waveform to the DUTs in parallel, at step 58, to allow for isolation of a specific fail mechanism in the tester. The pass-fail condition at the specified data point in response to the edge- specific pattern is then detected in parallel, at step 60, and then stored to the memory (not shown), in parallel, at step 62.

Following the storing step 62, a determination of whether the edge has been detected is made at step 64. If the edge is located, then the algorithm looks to determine if all thirty-two sites are characterized, at step 66. If all of the sites are not characterized, then a new controlling site is selected, at step 68, followed by an edge detection step 64.

If the edge is not located from the determination at step 64, then the algorithm selects a new data point, at step 52, and repeats the foregoing steps until the edge is located. Where subsequent sites are selected, and pass/fail information is already stored in memory for a specific data point (from the determination at step 56), then the previously used information is utilized in the search, rather than re-generated in steps 58 through 64. Referring back to Figure 4, once the characterization step is complete, the measured data is compared to the known golden data, at step 46, to determine respective offsets. To eliminate the offsets for specific edge parameters, the tester calibration registers (not shown) corresponding to the edge parameters are adjusted, at step 48. Following a successful tester calibration, the tester is then ready to commence production testing of semiconductor devices in high volume and at high accuracy.

Those skilled in the art will appreciate the many benefits and advantages afforded by the present invention. Of significance is the high accuracy achievable by applying edge-specific calibration patterns during the calibration procedure to isolate specific electrical parameters that may then be adjusted to a high degree of accuracy. Carrying out the procedure in parallel provides added benefit by minimizing calibration run-times. Additionally, since the present invention is employed as software, conventional semiconductor tester hardware may be easily upgraded with minimal cost and effort. While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will, be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims

WHAT IS CLAIMED IS:

1. A method of calibrating a semiconductor tester having a plurality of channels, said method including the steps of: selecting at least one golden device having known electrical characteristics, and a plurality of failure mechanisms; interfacing said at least one golden device with said plurality of channels, said at least one golden device having a plurality of pins corresponding to said plurality of channels; characterizing said plurality of channels in parallel with edge-specific tester waveforms applied to and detected from said at least one golden device, said edge-specific tester waveform operative to isolate a specific subset of said plurality of failure mechanisms and generate edge-specific characterization data; comparing said edge-specific characterization data to said known electrical characteristics associated with said at least one golden device to detect electrical parameter inconsistencies; and tuning said plurality of channels to minimize said edge parameter inconsistencies.

2. A method according to claim 1 wherein said characterizing step includes: identifying the actual transition timing of a signal edge within an expected timing range.

3. A method according to claim 2 wherein said identifying step includes the steps of: searching for a pass/fail threshold for said transition for all of said pins in parallel at a specified point in time; detecting pass/fail conditions at said point in time for all of said pins; storing said pass/fail conditions at said specified point in time for all of said pins; continuing said searching, detecting and storing steps until said transition timing is identified; finding transition thresholds for all of said pins and, where possible, substituting said detecting step for the step of utilizing said previously stored pass/fail condition.

4. Semiconductor tester software for operating a semiconductor tester, said tester software including: a test program including pattern and control data for testing one or more semiconductor devices; a control code library; golden device calibration software for calibrating a plurality of said tester channels, said golden device calibration software including a GDC control file operative to cooperate with said control code library for programming calibration control commands, and a GDC pattern file having edge-specific pattern data for applying to said golden DUT, according to said GDC control file.

5. Semiconductor tester software according to claim 3 wherein said edge- specific pattern data includes: programmed edge timings sufficient to isolate a specific edge parameter from other edge parameters.

6. Automatic test equipment including: a semiconductor tester; and semiconductor tester software for operating said semiconductor tester, said tester software including a test program including pattern and control data for testing one or more semiconductor devices; a control code library; golden device calibration software for calibrating a plurality of said tester channels, said golden device calibration software including a GDC control file operative to cooperate with said control code library for programming calibration control commands, and a GDC pattern file having edge-specific pattern data for applying to said golden DUT, according to said GDC control file.