WO2002084727A2 - Method of fabricating an oxide layer on a silicon carbide layer utilizing an anneal in a hydrogen environment - Google Patents

Method of fabricating an oxide layer on a silicon carbide layer utilizing an anneal in a hydrogen environment Download PDF

Info

Publication number
WO2002084727A2
WO2002084727A2 PCT/US2002/011691 US0211691W WO02084727A2 WO 2002084727 A2 WO2002084727 A2 WO 2002084727A2 US 0211691 W US0211691 W US 0211691W WO 02084727 A2 WO02084727 A2 WO 02084727A2
Authority
WO
WIPO (PCT)
Prior art keywords
oxide layer
annealing
oxide
layer
silicon carbide
Prior art date
Application number
PCT/US2002/011691
Other languages
French (fr)
Other versions
WO2002084727A3 (en
Inventor
Lori A. Lipkin
Mrinal Kanti Das
Original Assignee
Cree, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/834,283 external-priority patent/US6610366B2/en
Application filed by Cree, Inc. filed Critical Cree, Inc.
Priority to EP02733980A priority Critical patent/EP1378006B1/en
Priority to JP2002581576A priority patent/JP4781610B2/en
Priority to DE60228695T priority patent/DE60228695D1/en
Priority to CA2442929A priority patent/CA2442929C/en
Priority to KR1020037013333A priority patent/KR100855388B1/en
Publication of WO2002084727A2 publication Critical patent/WO2002084727A2/en
Publication of WO2002084727A3 publication Critical patent/WO2002084727A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
    • H01L21/02326—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen into a nitride layer, e.g. changing SiN to SiON
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048—Making electrodes
    • H01L21/049—Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3145—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers formed by deposition from a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs

Definitions

  • the present invention was made, at least in part, with support from United States Air Force Wright Labs contract number F33615-99-C-2914. The Government may have certain rights in this invention.
  • the present invention relates to the fabrication of semiconductor devices and more particularly, to the fabrication of oxide layers on silicon carbide (SiC).
  • NO is a health hazard having a National Fire Protection Association (NFPA) health danger rating of 3
  • NFPA National Fire Protection Association
  • Suzuki et al. investigated post oxidation annealing in hydrogen.
  • Suzuki et al "Effect of Post- oxidation-annealing in Hydrogen on SiO 2 /4H-SiC Interface," Material Science Forum, Vols. 338-342, pp. 1073-1076, 2000.
  • These researchers reported that flat- band voltage shift and interface state density could be improved by post oxidation annealing in both argon and hydrogen.
  • 4H-SiC was oxidized in dry O 2 at 1200 °C.
  • Post oxidation annealing was then carried out in argon or hydrogen for 30 minutes at 400, 700, 800 and 1000 °C.
  • Other researchers have reported that post oxidation anneals in hydrogen provide no increased benefit over post oxidation anneals in other gases. Mrinal Das, "Fundamental Studies of the Silicon Carbide MOS Structure,” Doctoral Thesis, Purdue University, submitted December, 1999.
  • Embodiments of the present invention provide for fabricating a silicon carbide structure by fabricating a nitrided oxide layer on a layer of silicon carbide and annealing the nitrided oxide layer in an environment containing hydrogen.
  • Such a fabrication of the nitrided oxide layer may be provided by forming, annealing or forming and annealing the oxide layer in at least one of nitric oxide, nitrous oxide and/or an ambient containing a reactive nitrogen species.
  • the nitrided oxide layer may be provided by fabricating an oxide layer and fabricating a nitride layer on the oxide layer so as to provide the nitrided oxide layer on which the nitride layer is fabricated.
  • Such a formation of a nitride layer may both provide the nitrided oxide layer and hydrogenate the nitrided oxide layer as hydrogen may be a byproduct of the formation of the nitride layer.
  • hydrogen annealing the oxide layer may be provided substantially concurrently with the step of fabricating the nitride layer.
  • the silicon carbide layer comprises 4H polytype silicon carbide.
  • the silicon carbide layer may be a silicon carbide layer on a non-silicon carbide substrate, a silicon carbide layer on a silicon carbide substrate and/or a portion of a silicon carbide substrate.
  • annealing the oxide layer is provided by a subsequent processing step which heats the oxide layer to a temperature of greater than about 400 °C in a hydrogen containing environment whether it be a part of a separate anneal step or other such processing step.
  • the oxide layer is annealed at a temperature of greater than about 400 °C in a hydrogen containing environment.
  • the oxide layer may also be annealed at a temperature of between about 400 °C and about 1000 °C in a hydrogen containing environment.
  • the oxide layer is annealed at a temperature of less than about 900 °C in a hydrogen containing environment.
  • the oxide layer is annealed at a temperature of between about 400 °C and about 800 °C in a hydrogen containing environment.
  • the anneal may be carried out for a time of greater than about 2 minutes.
  • processing steps subsequent to the anneal in a hydrogen containing environment high temperature processing steps are also carried out in a hydrogen containing environment.
  • the hydrogen anneal is preceded by forming metallization for a semiconductor device associated with the oxide layer.
  • the hydrogen anneal of the oxide layer can be provided by annealing the oxide layer at a temperature of less than about 900 °C in a hydrogen containing environment.
  • the annealing of the oxide layer may be a contact anneal.
  • a silicon carbide metal oxide semiconductor device may be formed having the oxide layer as a gate oxide of the metal oxide semiconductor device.
  • the nitrided oxide is annealed in forming gas having about 4% hydrogen and about 96% inert gases.
  • an oxide layer on a silicon carbide layer is fabricated by nitriding the oxide layer on the silicon carbide layer with at least one of nitric oxide and nitrous oxide and annealing the nitrided oxide layer at a temperature of between about 400 °C about 900 °C in a hydrogen containing environment for at least about 2 minutes.
  • Figure 1A is a flowchart illustrating processing steps for hydrogen annealing according to embodiments of the present invention
  • Figure IB is a flowchart illustrating the incorporation of additional processing steps with hydrogen annealing according to further embodiments of the present invention
  • Figure 2 is a schematic illustration of a furnace tube suitable for use in embodiments of the present invention
  • Figure 3 is a graph of Drr versus energy level from the conduction band for various thermal oxidation, post-growth N 2 O anneals and N O oxidation;
  • Figures 4A and 4B are graphs of interface state density for an oxide which has been N 2 O annealed at 1300 °C measured before and after anneal at 800 °C in a forming gas of 4% hydrogen and 96% inert gases according to embodiments of the present invention
  • Figure 5 is a graph of capacitance versus voltage for capacitors having an oxide which has been N 2 O annealed at 1300 °C measured before and after anneal at 800 °C in a forming gas of 4% hydrogen and 96% inert gases according to embodiments of the present invention.
  • Figure 6 is a graph of field effect mobility versus gate voltage for MOSFETs having a gate oxide which has been N 2 O annealed at 1300 °C measured before and after anneal at 800 °C in a forming gas of 4% hydrogen and 96%) inert gases according to embodiments of the present invention.
  • Embodiments of the present invention provide methods which may improve the interface between an oxide layer and SiC in any device which includes such an interface. These methods are especially advantageous in the fabrication of Metal- Oxide-Semiconductor (MOS) devices created on SiC.
  • MOS Metal- Oxide-Semiconductor
  • interface states with energy levels near the conduction band of SiC may be dramatically reduced. Reduction of such defects may be advantageous, because these defects may limit a MOS device's effective surface channel mobility.
  • FIGS 1A and IB are flow charts illustrating operations according to particular embodiments of the present invention.
  • embodiments of the present invention utilize an anneal of a nitrided oxide layer to further reduce interface state densities at the silicon carbide oxide boundary.
  • nitrided oxide layer refers to oxide layers formed or subsequently annealed (as a separate anneal step and/or as subsequent processing such as the deposition of a nitride or oxynitride layer) in the an atmosphere which yields chemically reactive nitrogen species, such as nitrogen precursors, including nitric oxide (NO) and/or nitrous oxide (N 2 O), and/or as part of a processing step where a reactive nitrogen species is a byproduct, to thereby introducing nitrogen into the layer.
  • a silicon carbide layer is provided (block 70).
  • the SiC layer may be an epitaxial layer and/or a substrate.
  • a nitrided oxide layer is provided on the silicon carbide layer (block 72).
  • the nitridation may be provided, as described herein, by growth and/or anneal in an N 2 O and/or NO environment.
  • nitridation of the oxide layer may be provided by processing steps for deposition of a nitride layer on the oxide layer, for example, in an oxide-nitride (ON) or oxide- nitride-oxide (ONO) structure.
  • ONO and ON structures are described in commonly assigned United States Patent No. 6,246,076, the disclosure of which is incorporated herein by reference as if set forth fully herein.
  • the oxide layer may be formed by deposition, such as Low Pressure Chemical Vapor Deposition (LPCVD), thermally grown through a thermal oxidation process and/or formed using other techniques.
  • LPCVD Low Pressure Chemical Vapor Deposition
  • the oxide layer is formed utilizing a wet reoxidation process as described in United States Patent No. 5,972,801, the disclosure of which is incorporated herein by reference as if set forth fully herein.
  • the nitrided oxide layer is annealed in a hydrogen containing environment
  • Such an anneal may be a separate processing step or may be part of a subsequent deposition or other such process, for example, the deposition of a nitride layer on an oxide layer in a wet environment may provide both the nitridation and anneal.
  • the anneal is preferably carried out at a temperature of greater than about 400 °C and less than about 1000 °C.
  • the anneal is carried out at a temperature of from about 400 °C to about 800 °C.
  • the anneal is preferably carried out for about 2 or more minutes.
  • the anneal in a hydrogen containing environment may be carried out immediately after nitridation or intervening steps may be performed before the anneal.
  • the anneal may be provided as a subsequent processing step which provides a contact anneal.
  • a nitrided oxide layer is provided on a SiC layer (blocks 80 and 82).
  • Further device fabrication may then be performed to provide a silicon carbide semiconductor device (block 84).
  • contact metallization is fabricated for the device (block 86).
  • the contact metallization is then subjected to a contact anneal in a hydrogen containing environment (block 88), preferably at a temperature of greater than about 400 °C and less than about 900 °C.
  • a contact anneal provides at least part of the anneal of the nitrided oxide layer in a hydrogen containing environment.
  • Subsequent high temperature processing steps are then also carried out in a hydrogen containing environment (block 90).
  • the anneal may be provided subsequent to metallization of the device by performing a contact anneal in a hydrogen containing environment at a temperature of less than about 900 °C.
  • the oxide layer may provide a gate oxide of a metal oxide semiconductor field effect transistor (MOSFET).
  • MOSFET metal oxide semiconductor field effect transistor
  • the contact anneal may anneal the contacts of the device as well as provide the anneal of the nitrided oxide. Whenever in the fabrication process the anneal of the nitrided oxide layer takes place, it may be preferred that subsequent high temperature (i.e. processing at temperatures greater than about 400 °C) processing be conducted in a hydrogen containing environment.
  • the term hydrogen containing environment refers to hydrogen and/or a hydrogen precursor either alone or in combination with other gases.
  • a forming gas of 4% hydrogen and 96% argon may be utilized for the hydrogen anneal.
  • the hydrogen may be provided by a hydrogen precursor, such as NH 3 and/or may be a byproduct of a processing step.
  • the present invention should not be construed as limited to pure hydrogen environments but includes hydrogen and/or hydrogen precursors as a constituent gas with other gases as well.
  • FIG 2 is an illustration of a furnace tube suitable for use in particular embodiments of the present invention to provide the nitrided oxide layer.
  • the furnace tube 10 has a plurality of wafers 12 of SiC either with an oxide layer, such as SiO 2 , formed thereon or on which an oxide layer is to be formed.
  • the SiC wafer is 4H-SiC.
  • the wafers 12 are placed on a carrier 14 such that the wafers will, typically have a fixed position in the furnace tube 10.
  • the carrier 14 is positioned so that the wafers are a distance L1+L2 from an inlet of the furnace tube 10 and extend for a distance L3 within the furnace tube 10.
  • Input gases 16, which may include N 2 O and/or NO, are passed into the furnace tube 10 and are heated as they traverse the distance LI based on a predetermined temperature profile so as to provide the heated gases 18.
  • the heated gases 18 may be maintained at temperatures based on the predetermined temperature profile and traverse the distance L2 to reach the first of the wafers 12.
  • the heated gases 18 continue to pass through the furnace tube 10 until they leave the furnace tube 10 through an outlet port as exhaust gases 20.
  • the heated gases 18 traverse the distance L3.
  • the heated gases 18 are preferably maintained at a substantially constant temperature for the distances L2 and L3, however, as will be appreciated by those of skill in the art in light of the present disclosure, various temperature profiles may also be utilized. Such profiles may include variations in temperature over time and/or distance.
  • the predetermined temperature profile should include either an anneal temperature of greater than about 1100 °C or an oxidation temperature of at least about 1200 °C.
  • the heated gases 18 may reach a temperature at which the N 2 O begins to break down into its constituents at the end of the LI distance. This distance may depend on the physical characteristics of the furnace tube 10, the predetermined temperature profile and the flow rate profile. The heated gases 18 also traverse the distance L2 before reaching the wafers 12.
  • the amount of time that it takes the heated gases to traverse the distance L2 is referred to herein as an "initial residence time.”
  • the heated gasses are maintained at a substantially constant temperature corresponding to an anneal temperature of greater than about 1100 °C or an oxidation temperature of at least about 1200 °C for the initial residence time.
  • differing heating profiles could be utilized which increase or decrease the initial residence time. It may be preferred, however, that the heating profile be rapid such that the initial residence time is substantially the same as the time that the heated gases 18 are maintained at an anneal temperature of greater than about 1100 °C or an oxidation temperature of at least about 1200 °C before traversing the L3 distance.
  • total residence time The total amount of time that it takes the heated gases 18 to traverse the distance L2+L3 is referred to herein as the "total residence time.” As will be appreciated by those of skill in the art in light of the present disclosure, these residence times depend on the velocity of the heated gases 18 through the furnace tube 10 which may be determined based on the flow rates of the heated gases 18 and the cross-sectional area of the furnace tube 10. Such velocities may be average velocities, for example, if turbulent flow is achieved, or may be actual velocities, for example, in laminar flow systems. Thus, the term velocity is used herein to refer to both average and actual velocities.
  • the nitrided oxide layer may be provided by, among other ways, growth and/or anneal in an NO and/or an N 2 O environment. NO growth and/or annealing as described above may be utilized alone or in combination with N 2 O growth and/or annealing. If the nitrided oxide layer if provided by growth and/or annealing in an N O environment, it is preferred that such growth and/or annealing be carried out at a predetermined temperature and a predetermined flow rate as described herein.
  • the oxide is annealed using a predetermined temperature profile which includes an anneal temperature of greater than about 1100 °C in a chamber in which N 2 O is supplied at a flow rate profile within predetermined flow rate limits.
  • the temperature of the anneal is about 1175 °C or higher and more preferably, about 1200 °C may be utilized.
  • the flow rate limits of N O may be selected based on the particular equipment in which the process is used. However, in particular embodiments the flow rate limits of N O may be as low as about 2 Standard Liters per Minute (SLM) or as high as about 8 SLM. In further embodiments, flow rate limits of from about 3 to about 5 SLM may be preferred.
  • gas velocities as low as about 0.37 cm/sec or as high as about 1.46 cm/sec or velocities of from about 0.55 cm/s to about 0.95 cm s may be suitable.
  • such velocities result in an initial residence time of from about 11 seconds to about 45 seconds and a total residence of from about 28 seconds to about 112 seconds.
  • the initial residence time is from about 16 seconds to about 31 seconds and a total residence time of from about 41 to about 73 seconds.
  • the N 2 O and/or NO anneal may be carried out for about 3 hours, however, anneals of from about 30 minutes to about 6 hours may also be utilized although longer times may also be utilized.
  • the SiC wafers 12 are oxidized using a predetermined temperature profile which includes an oxidation temperature of greater than about 1200 °C in a chamber in which N O is supplied at a flow rate profile within predetermined flow rate limits.
  • the temperature of the oxidation is about 1300 °C.
  • the flow rate limits of N 2 O may be selected based on the particular equipment in which the process is used. However, in particular embodiments, the flow rate limits of N 2 O may be as low as about 2 Standard Liters per Minute (SLM) or as high as about 6 SLM or higher. In further embodiments, flow rate limits of from about 3.5 SLM to about 4 SLM may be preferred.
  • gas velocities as low as about 0.37 cm/sec or as high as about 1.11 cm/sec may be utilized, while velocities of from about 0.65 cm/s to about 0.74 cm/s may be preferred.
  • velocities for an L2 distance of about 12 inches (about 30.48 cm) and an L3 distance of about 18 inches (about 45.72 cm), such velocities result in an initial residence time of from about 11 seconds to about 33 seconds and a total residence time of from about 28 seconds to about 84 seconds.
  • the initial residence time is from about 19 second to about 22 seconds and the total residence time is from about 49 to about 56 seconds.
  • the N 2 O oxidation may be carried out for an amount of time dependent on the desired thickness of the oxide layer. For example, oxidation times of about 3 hours or greater may be utilized.
  • N 2 O refers to pure N 2 O or N 2 O in combination with other oxidizing agents, such as steam, O 2 , and/or inert gases.
  • Oxidation in an NO and/or N 2 O environment and/or anneals in an NO and/or N 2 O environment may be followed by an optional anneal in inert gas or gases, such as argon and/or N 2 or combinations thereof with other gases.
  • an anneal may be carried out for about 1 hour, however, anneals of up to about 3 hours or longer may also be utilized.
  • Figures 3 through 6 illustrate results which may be obtained utilizing embodiments of the present invention.
  • Figure 3 illustrates results which were obtained for N 2 O growth and N 2 O annealing without subsequent annealing in a hydrogen containing environment.
  • Figures 4A, 4B, 5 and 6 illustrate results obtained with a hydrogen anneal of a nitrided oxide layer.
  • the solid line represents a thermally grown oxide without nitridation.
  • exposing an existing oxide to N 2 O increases the interface state density, as shown by comparing the heavy solid line representing a thermal oxide to the data for the same thermal oxide exposed to an
  • FIGS. 4A and 4B are graphs of interface state density for an oxide which has been N 2 O annealed at 1300 °C measured before and after anneal at 800 °C in a forming gas of 4% hydrogen and 96%) inert gases.
  • line 180 illustrates the interface trap density for the oxide before the anneal and line 182 after the anneal.
  • line 184 illustrates the interface trap density for the oxide before the anneal and line 186 after the anneal.
  • Lines 180 and 184 may represent the lowest reported values for Drr on the 4H-SiC MOS interface.
  • the 4% hydrogen present in the forming gas further improves this result on both the upper ( Figure 4B) and lower ( Figure 4A) halves of the bandgap.
  • Figure 5 is a graph of capacitance versus voltage for capacitors having an oxide which has been N 2 O annealed at 1300 °C measured before and after anneal at 800 °C in a forming gas of 4% hydrogen and 96% inert gases.
  • line 190 illustrates the capacitance for the oxide before the anneal and line 192 after the anneal.
  • the forming gas anneal reduces the flatband voltage by 4.5 Volts, which corresponds to a 1.7E12 cm " reduction in effective oxide charge.
  • Figure 6 is a graph of field effect mobility versus gate voltage for MOSFETs having a gate oxide which has been N 2 O annealed at 1300 °C measured before and after anneal at 800 °C in a forming gas of 4% hydrogen and 96% inert gases.
  • line 200 illustrates field effect mobility for MOSFETs with a nitrided gate oxide before the anneal and line 202 after the anneal. As is seen in Figure 6, inversion channel mobility increases by almost 20% and the threshold voltage is reduced by 2 V.

Abstract

Silicon carbide structures are fabricated by fabricating a nitrided oxide layer on a layer of silicon carbide and annealing the nitrided oxide layer in an environment containing hydrogen. Such a fabrication of the nitrided oxide layer may be provided by forming the oxide layer in at least one of nitric oxide and nitrous oxide and/or annealing an oxide layer in at least one of nitric oxide and nitrous oxide. Alternatively, the nitrided oxide layer may be provided by fabricating an oxide layer and fabricating a nitride layer on the oxide layer so as to provide the nitrided oxide layer on which the nitride layer is fabricated. Furthermore, annealing the oxide layer may be provided as a separate step and/or substantially concurrently with another step such as fabricating the nitride layer or performing a contact anneal. The hydrogen environment may be pure hydrogen, hydrogen combined with other gases and/or result from a hydrogen precursor. Anneal temperatures of 400 °C or greater are preferred.

Description

METHOD OF FABRICATING AN OXIDE LAYER ON A SILICON CARBIDE LAYER UTILIZING AN ANNEAL IN A HYDROGEN ENVIRONMENT
Related Applications The present application is a continuation-in-part of United states Patent Application Serial No. entitled "METHOD OF N2O GROWTH OF AN OXIDE LAYER ON A SILICON CARBIDE LAYER" filed October 1, 2001 (Attorney Docket No. 5308-157IP) which claims priority from United States Provisional Application Serial No. 60/294,307 entitled "METHOD OF N2O GROWTH OF AN OXIDE LAYER ON A SILICON CARBIDE LAYER" filed May 30, 2001 and claims priority from, and is a continuation-in-part of, United States Patent Application Serial No. 09/834,283 filed April 12, 2001 entitled "METHOD OF N2O ANNEALING AN OXIDE LAYER ON A SILICON CARBIDE LAYER". The disclosures of each of the above-cited applications are incorporated herein by reference as if set forth fully herein.
Statement of Government Interest
The present invention was made, at least in part, with support from United States Air Force Wright Labs contract number F33615-99-C-2914. The Government may have certain rights in this invention.
Field of the Invention
The present invention relates to the fabrication of semiconductor devices and more particularly, to the fabrication of oxide layers on silicon carbide (SiC).
Background of the Invention Devices fabricated from silicon carbide are typically passivated with an oxide layer, such as SiO2, to protect the exposed SiC surfaces of the device and/or for other reasons. However, the interface between SiC and SiO2 may be insufficient to obtain a high surface mobility of electrons. More specifically, the interface between SiC and SiO2 conventionally exhibits a high density of interface states, which may reduce surface electron mobility.
Recently, annealing of a thermal oxide in a nitric oxide (NO) ambient has shown promise in a planar 4H-SiC MOSFET structure not requiring a p-well implant. See M. K. Das, L. A. Lipkin, J. W. Palmour, G. Y. Chung, J. R. Williams, K.
McDonald, and L. C. Feldman, "High Mobility 4H-S1C Inversion Mode MOSFETs Using Thermally Grown, NO Annealed SiO2," IEEE Device Research Conference, Denver, CO, June 19-21, 2000 and G. Y. Chung, C. C. Tin, J. R. Williams, K. McDonald, R. A. Weller, S. T. Pantelides, L. C. Feldman, M. K. Das, and J. W. Palmour, "Improved Inversion Channel Mobility for 4H-SiC MOSFETs Following High Temperature Anneals in Nitric Oxide," IEEE Electron Device Letters accepted for publication, the disclosures of which are incorporated by reference as if set forth fully herein. This anneal is shown to significantly reduce the interface state density near the conduction band edge. G. Y. Chung, C. C. Tin, J. R. Williams, K. McDonald, M. Di Ventra, S. T. Pantelides, L. C. Feldman, and R. A. Weller, "Effect of nitric oxide annealing on the interface trap densities near the band edges in the 4H polytype of silicon carbide," Applied Physics Letters, Vol. 76, No. 13, pp. 1713-1715, March 2000, the disclosure of which is incorporated herein as if set forth fully. High electron mobility (35-95 cm2Ns) is obtained in the surface inversion layer due to the improved MOS interface.
Unfortunately, NO is a health hazard having a National Fire Protection Association (NFPA) health danger rating of 3, and the equipment in which post- oxidation anneals are typically performed is open to the atmosphere of the cleanroom. They are often exhausted, but the danger of exceeding a safe level of NO contamination in the room is not negligible.
Growing the oxide in N2O is possible as described in J. P. Xu, P. T. Lai, C. L. Chan, B. Li, and Y. C. Cheng, "Improved Performance and Reliability of N O-Grown Oxynitride on 6H-SiC," IEEE Electron Device Letters, Vol. 21, No. 6, pp. 298-300, June 2000, the disclosure of which is incorporated by reference as if set forth fully herein. Xu et al. describe oxidizing SiC at 1100 °C for 360 minutes in a pure N2O ambient and annealing in N2 for 1 hour at 1100 °C.
Post-growth nitridation of the oxide on 6H-SiC in N2O at a temperature of 1100 °C has also been investigated by Lai et al. P. T. Lai, Supratic Chakraborty, C. L. Chan, and Y. C. Cheng, "Effects of nitridation and annealing on interface properties of thermally oxidized SiO2/SiC metal-oxide-semiconductor system," Applied Physics Letters, Vol. 76, No. 25, pp. 3744-3746, June 2000, the disclosure of which is incorporated by reference as if set forth fully herein. However, Lai et al. concluded that such treatment deteriorates the interface quality which may be improved with a subsequent wet or dry anneal in O2 which may repair the damage induced by nitridation in N2O. Moreover, even with a subsequent O2 anneal, Lai et al. did not see any significant reduction in interface state density as compared to the case without nitridation in N2O.
In addition to NO and N2O growth and annealing, research has also been conducted on post growth anneals in other environments. For example, Suzuki et al. investigated post oxidation annealing in hydrogen. Suzuki et al, "Effect of Post- oxidation-annealing in Hydrogen on SiO2/4H-SiC Interface," Material Science Forum, Vols. 338-342, pp. 1073-1076, 2000. These researchers reported that flat- band voltage shift and interface state density could be improved by post oxidation annealing in both argon and hydrogen. In this research, 4H-SiC was oxidized in dry O2 at 1200 °C. Post oxidation annealing was then carried out in argon or hydrogen for 30 minutes at 400, 700, 800 and 1000 °C. Other researchers, however, have reported that post oxidation anneals in hydrogen provide no increased benefit over post oxidation anneals in other gases. Mrinal Das, "Fundamental Studies of the Silicon Carbide MOS Structure," Doctoral Thesis, Purdue University, submitted December, 1999.
Summary of the Invention Embodiments of the present invention provide for fabricating a silicon carbide structure by fabricating a nitrided oxide layer on a layer of silicon carbide and annealing the nitrided oxide layer in an environment containing hydrogen. Such a fabrication of the nitrided oxide layer may be provided by forming, annealing or forming and annealing the oxide layer in at least one of nitric oxide, nitrous oxide and/or an ambient containing a reactive nitrogen species. Alternatively, the nitrided oxide layer may be provided by fabricating an oxide layer and fabricating a nitride layer on the oxide layer so as to provide the nitrided oxide layer on which the nitride layer is fabricated. Such a formation of a nitride layer may both provide the nitrided oxide layer and hydrogenate the nitrided oxide layer as hydrogen may be a byproduct of the formation of the nitride layer. Furthermore, in such embodiments, hydrogen annealing the oxide layer may be provided substantially concurrently with the step of fabricating the nitride layer.
In particular embodiments of the present invention, the silicon carbide layer comprises 4H polytype silicon carbide. The silicon carbide layer may be a silicon carbide layer on a non-silicon carbide substrate, a silicon carbide layer on a silicon carbide substrate and/or a portion of a silicon carbide substrate.
In further embodiments of the present invention, annealing the oxide layer is provided by a subsequent processing step which heats the oxide layer to a temperature of greater than about 400 °C in a hydrogen containing environment whether it be a part of a separate anneal step or other such processing step. In other embodiments of the present invention, the oxide layer is annealed at a temperature of greater than about 400 °C in a hydrogen containing environment. The oxide layer may also be annealed at a temperature of between about 400 °C and about 1000 °C in a hydrogen containing environment. In particular embodiments of the present invention, the oxide layer is annealed at a temperature of less than about 900 °C in a hydrogen containing environment. Preferably, the oxide layer is annealed at a temperature of between about 400 °C and about 800 °C in a hydrogen containing environment. Additionally, the anneal may be carried out for a time of greater than about 2 minutes.
In still further embodiments of the present invention, processing steps subsequent to the anneal in a hydrogen containing environment high temperature processing steps are also carried out in a hydrogen containing environment.
In additional embodiments of the present invention, the hydrogen anneal is preceded by forming metallization for a semiconductor device associated with the oxide layer. In such embodiments, the hydrogen anneal of the oxide layer can be provided by annealing the oxide layer at a temperature of less than about 900 °C in a hydrogen containing environment. In such embodiments, the annealing of the oxide layer may be a contact anneal. Additionally, a silicon carbide metal oxide semiconductor device may be formed having the oxide layer as a gate oxide of the metal oxide semiconductor device. In particular embodiments of the present invention, the nitrided oxide is annealed in forming gas having about 4% hydrogen and about 96% inert gases. In still further embodiments of the present invention, an oxide layer on a silicon carbide layer is fabricated by nitriding the oxide layer on the silicon carbide layer with at least one of nitric oxide and nitrous oxide and annealing the nitrided oxide layer at a temperature of between about 400 °C about 900 °C in a hydrogen containing environment for at least about 2 minutes.
Brief Description of the Drawings Figure 1A is a flowchart illustrating processing steps for hydrogen annealing according to embodiments of the present invention;
Figure IB is a flowchart illustrating the incorporation of additional processing steps with hydrogen annealing according to further embodiments of the present invention; Figure 2 is a schematic illustration of a furnace tube suitable for use in embodiments of the present invention;
Figure 3 is a graph of Drr versus energy level from the conduction band for various thermal oxidation, post-growth N2O anneals and N O oxidation;
Figures 4A and 4B are graphs of interface state density for an oxide which has been N2O annealed at 1300 °C measured before and after anneal at 800 °C in a forming gas of 4% hydrogen and 96% inert gases according to embodiments of the present invention;
Figure 5 is a graph of capacitance versus voltage for capacitors having an oxide which has been N2O annealed at 1300 °C measured before and after anneal at 800 °C in a forming gas of 4% hydrogen and 96% inert gases according to embodiments of the present invention; and
Figure 6 is a graph of field effect mobility versus gate voltage for MOSFETs having a gate oxide which has been N2O annealed at 1300 °C measured before and after anneal at 800 °C in a forming gas of 4% hydrogen and 96%) inert gases according to embodiments of the present invention.
Detailed Description of the Invention The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout. It will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.
Embodiments of the present invention provide methods which may improve the interface between an oxide layer and SiC in any device which includes such an interface. These methods are especially advantageous in the fabrication of Metal- Oxide-Semiconductor (MOS) devices created on SiC. Using embodiments of the present invention, interface states with energy levels near the conduction band of SiC may be dramatically reduced. Reduction of such defects may be advantageous, because these defects may limit a MOS device's effective surface channel mobility.
Embodiments of the present invention will now be described with reference to Figures 1A and IB which are flow charts illustrating operations according to particular embodiments of the present invention. As illustrated in Figure 1A, embodiments of the present invention utilize an anneal of a nitrided oxide layer to further reduce interface state densities at the silicon carbide oxide boundary. As used herein, the term nitrided oxide layer refers to oxide layers formed or subsequently annealed (as a separate anneal step and/or as subsequent processing such as the deposition of a nitride or oxynitride layer) in the an atmosphere which yields chemically reactive nitrogen species, such as nitrogen precursors, including nitric oxide (NO) and/or nitrous oxide (N2O), and/or as part of a processing step where a reactive nitrogen species is a byproduct, to thereby introducing nitrogen into the layer. Turning to Figure 1A, a silicon carbide layer is provided (block 70). The SiC layer may be an epitaxial layer and/or a substrate. A nitrided oxide layer is provided on the silicon carbide layer (block 72). The nitridation may be provided, as described herein, by growth and/or anneal in an N2O and/or NO environment. Similarly, nitridation of the oxide layer may be provided by processing steps for deposition of a nitride layer on the oxide layer, for example, in an oxide-nitride (ON) or oxide- nitride-oxide (ONO) structure. ONO and ON structures are described in commonly assigned United States Patent No. 6,246,076, the disclosure of which is incorporated herein by reference as if set forth fully herein. For embodiments where the nitrided oxide layer is provided by an anneal, the oxide layer may be formed by deposition, such as Low Pressure Chemical Vapor Deposition (LPCVD), thermally grown through a thermal oxidation process and/or formed using other techniques. Preferably, the oxide layer is formed utilizing a wet reoxidation process as described in United States Patent No. 5,972,801, the disclosure of which is incorporated herein by reference as if set forth fully herein. The nitrided oxide layer is annealed in a hydrogen containing environment
(block 74). Such an anneal may be a separate processing step or may be part of a subsequent deposition or other such process, for example, the deposition of a nitride layer on an oxide layer in a wet environment may provide both the nitridation and anneal. The anneal is preferably carried out at a temperature of greater than about 400 °C and less than about 1000 °C. Preferably, the anneal is carried out at a temperature of from about 400 °C to about 800 °C. The anneal is preferably carried out for about 2 or more minutes.
The anneal in a hydrogen containing environment may be carried out immediately after nitridation or intervening steps may be performed before the anneal. Thus, as illustrated in Figure IB, the anneal may be provided as a subsequent processing step which provides a contact anneal. As seen in Figure IB, a nitrided oxide layer is provided on a SiC layer (blocks 80 and 82). Further device fabrication may then be performed to provide a silicon carbide semiconductor device (block 84). As part of or separate from the device fabrication, contact metallization is fabricated for the device (block 86). The contact metallization is then subjected to a contact anneal in a hydrogen containing environment (block 88), preferably at a temperature of greater than about 400 °C and less than about 900 °C. Thus, the contact anneal provides at least part of the anneal of the nitrided oxide layer in a hydrogen containing environment. Subsequent high temperature processing steps are then also carried out in a hydrogen containing environment (block 90).
For example, in a silicon carbide metal oxide semiconductor device, the anneal may be provided subsequent to metallization of the device by performing a contact anneal in a hydrogen containing environment at a temperature of less than about 900 °C. Thus, for example, the oxide layer may provide a gate oxide of a metal oxide semiconductor field effect transistor (MOSFET). The contact anneal may anneal the contacts of the device as well as provide the anneal of the nitrided oxide. Whenever in the fabrication process the anneal of the nitrided oxide layer takes place, it may be preferred that subsequent high temperature (i.e. processing at temperatures greater than about 400 °C) processing be conducted in a hydrogen containing environment.
As used herein, the term hydrogen containing environment refers to hydrogen and/or a hydrogen precursor either alone or in combination with other gases. For example, a forming gas of 4% hydrogen and 96% argon may be utilized for the hydrogen anneal. Similarly, the hydrogen may be provided by a hydrogen precursor, such as NH3 and/or may be a byproduct of a processing step. Thus, the present invention should not be construed as limited to pure hydrogen environments but includes hydrogen and/or hydrogen precursors as a constituent gas with other gases as well.
Figure 2 is an illustration of a furnace tube suitable for use in particular embodiments of the present invention to provide the nitrided oxide layer. As seen in Figure 2, the furnace tube 10 has a plurality of wafers 12 of SiC either with an oxide layer, such as SiO2, formed thereon or on which an oxide layer is to be formed. Preferably, the SiC wafer is 4H-SiC. The wafers 12 are placed on a carrier 14 such that the wafers will, typically have a fixed position in the furnace tube 10. The carrier 14 is positioned so that the wafers are a distance L1+L2 from an inlet of the furnace tube 10 and extend for a distance L3 within the furnace tube 10. Input gases 16, which may include N2O and/or NO, are passed into the furnace tube 10 and are heated as they traverse the distance LI based on a predetermined temperature profile so as to provide the heated gases 18. The heated gases 18 may be maintained at temperatures based on the predetermined temperature profile and traverse the distance L2 to reach the first of the wafers 12. The heated gases 18 continue to pass through the furnace tube 10 until they leave the furnace tube 10 through an outlet port as exhaust gases 20. Thus, the heated gases 18 traverse the distance L3. The heated gases 18 are preferably maintained at a substantially constant temperature for the distances L2 and L3, however, as will be appreciated by those of skill in the art in light of the present disclosure, various temperature profiles may also be utilized. Such profiles may include variations in temperature over time and/or distance. However, in embodiments where the nitrided oxide layer is provided by an N O anneal and/or oxidation, the predetermined temperature profile should include either an anneal temperature of greater than about 1100 °C or an oxidation temperature of at least about 1200 °C. As is seen in Figure 2, the heated gases 18 may reach a temperature at which the N2O begins to break down into its constituents at the end of the LI distance. This distance may depend on the physical characteristics of the furnace tube 10, the predetermined temperature profile and the flow rate profile. The heated gases 18 also traverse the distance L2 before reaching the wafers 12. The amount of time that it takes the heated gases to traverse the distance L2 is referred to herein as an "initial residence time." Preferably, the heated gasses are maintained at a substantially constant temperature corresponding to an anneal temperature of greater than about 1100 °C or an oxidation temperature of at least about 1200 °C for the initial residence time. However, as will be appreciated by those of skill in the art, differing heating profiles could be utilized which increase or decrease the initial residence time. It may be preferred, however, that the heating profile be rapid such that the initial residence time is substantially the same as the time that the heated gases 18 are maintained at an anneal temperature of greater than about 1100 °C or an oxidation temperature of at least about 1200 °C before traversing the L3 distance.
The total amount of time that it takes the heated gases 18 to traverse the distance L2+L3 is referred to herein as the "total residence time." As will be appreciated by those of skill in the art in light of the present disclosure, these residence times depend on the velocity of the heated gases 18 through the furnace tube 10 which may be determined based on the flow rates of the heated gases 18 and the cross-sectional area of the furnace tube 10. Such velocities may be average velocities, for example, if turbulent flow is achieved, or may be actual velocities, for example, in laminar flow systems. Thus, the term velocity is used herein to refer to both average and actual velocities. As discussed above, the nitrided oxide layer may be provided by, among other ways, growth and/or anneal in an NO and/or an N2O environment. NO growth and/or annealing as described above may be utilized alone or in combination with N2O growth and/or annealing. If the nitrided oxide layer if provided by growth and/or annealing in an N O environment, it is preferred that such growth and/or annealing be carried out at a predetermined temperature and a predetermined flow rate as described herein.
For N2O annealing, preferably, the oxide is annealed using a predetermined temperature profile which includes an anneal temperature of greater than about 1100 °C in a chamber in which N2O is supplied at a flow rate profile within predetermined flow rate limits. Preferably, the temperature of the anneal is about 1175 °C or higher and more preferably, about 1200 °C may be utilized. The flow rate limits of N O may be selected based on the particular equipment in which the process is used. However, in particular embodiments the flow rate limits of N O may be as low as about 2 Standard Liters per Minute (SLM) or as high as about 8 SLM. In further embodiments, flow rate limits of from about 3 to about 5 SLM may be preferred. For particular furnaces as illustrated in Figure 2, gas velocities as low as about 0.37 cm/sec or as high as about 1.46 cm/sec or velocities of from about 0.55 cm/s to about 0.95 cm s may be suitable. In particular, for an L2 distance of about 12 inches (about 30.48 cm) and an L3 distance of about 18 inches (about 45.72 cm), such velocities result in an initial residence time of from about 11 seconds to about 45 seconds and a total residence of from about 28 seconds to about 112 seconds. In particular preferred embodiments, the initial residence time is from about 16 seconds to about 31 seconds and a total residence time of from about 41 to about 73 seconds. The N2O and/or NO anneal may be carried out for about 3 hours, however, anneals of from about 30 minutes to about 6 hours may also be utilized although longer times may also be utilized.
For N2O growth, preferably the SiC wafers 12 are oxidized using a predetermined temperature profile which includes an oxidation temperature of greater than about 1200 °C in a chamber in which N O is supplied at a flow rate profile within predetermined flow rate limits. Preferably, the temperature of the oxidation is about 1300 °C. The flow rate limits of N2O may be selected based on the particular equipment in which the process is used. However, in particular embodiments, the flow rate limits of N2O may be as low as about 2 Standard Liters per Minute (SLM) or as high as about 6 SLM or higher. In further embodiments, flow rate limits of from about 3.5 SLM to about 4 SLM may be preferred. Thus, for a particular apparatus, gas velocities as low as about 0.37 cm/sec or as high as about 1.11 cm/sec may be utilized, while velocities of from about 0.65 cm/s to about 0.74 cm/s may be preferred. In particular, for an L2 distance of about 12 inches (about 30.48 cm) and an L3 distance of about 18 inches (about 45.72 cm), such velocities result in an initial residence time of from about 11 seconds to about 33 seconds and a total residence time of from about 28 seconds to about 84 seconds. In particular preferred embodiments, the initial residence time is from about 19 second to about 22 seconds and the total residence time is from about 49 to about 56 seconds. The N2O oxidation may be carried out for an amount of time dependent on the desired thickness of the oxide layer. For example, oxidation times of about 3 hours or greater may be utilized. As used herein, N2O refers to pure N2O or N2O in combination with other oxidizing agents, such as steam, O2, and/or inert gases.
Oxidation in an NO and/or N2O environment and/or anneals in an NO and/or N2O environment may be followed by an optional anneal in inert gas or gases, such as argon and/or N2 or combinations thereof with other gases. Such an anneal may be carried out for about 1 hour, however, anneals of up to about 3 hours or longer may also be utilized.
Figures 3 through 6 illustrate results which may be obtained utilizing embodiments of the present invention. Figure 3 illustrates results which were obtained for N2O growth and N2O annealing without subsequent annealing in a hydrogen containing environment. Figures 4A, 4B, 5 and 6 illustrate results obtained with a hydrogen anneal of a nitrided oxide layer.
As shown in Figure 3, the solid line represents a thermally grown oxide without nitridation. At lower temperatures (1100°C), exposing an existing oxide to N2O increases the interface state density, as shown by comparing the heavy solid line representing a thermal oxide to the data for the same thermal oxide exposed to an
1 100°C N2O anneal. At 1200°C, the thermal oxide is significantly improved with the N2O anneal. Thermal oxides processed in a wet ambient may be further improved by the 1200°C N2O anneal, as seen by comparing the solid circle to the open circle data. Further improved results were obtained using a 1300°C N2O anneal process (the DRY-1300 line) and the 1300°C N2O growth process (the 1300 grown line). At this temperature, the oxidation of SiC is significant. So, in addition to annealing existing oxides in N2O, some oxides were grown in the N2O ambient (500 A was grown in 3 hours). Growing the oxide in N2O may save about 9 hours of processing time over annealing an existing oxide in N2O, by eliminating the oxidation step. As is seen in Figure 3 by comparing the Dry-1300 line to the 1300 grown line, substantially the same results were obtained regardless of whether the oxide was grown prior to N O processing or grown in N2O. Figures 4A and 4B are graphs of interface state density for an oxide which has been N2O annealed at 1300 °C measured before and after anneal at 800 °C in a forming gas of 4% hydrogen and 96%) inert gases. As is illustrated in Figure 4A, line 180 illustrates the interface trap density for the oxide before the anneal and line 182 after the anneal. In Figure 4B, line 184 illustrates the interface trap density for the oxide before the anneal and line 186 after the anneal. Lines 180 and 184 may represent the lowest reported values for Drr on the 4H-SiC MOS interface. The 4% hydrogen present in the forming gas further improves this result on both the upper (Figure 4B) and lower (Figure 4A) halves of the bandgap. Figure 5 is a graph of capacitance versus voltage for capacitors having an oxide which has been N2O annealed at 1300 °C measured before and after anneal at 800 °C in a forming gas of 4% hydrogen and 96% inert gases. In Figure 5, line 190 illustrates the capacitance for the oxide before the anneal and line 192 after the anneal. As is seen in Figure 5, the forming gas anneal reduces the flatband voltage by 4.5 Volts, which corresponds to a 1.7E12 cm" reduction in effective oxide charge. Figure 6 is a graph of field effect mobility versus gate voltage for MOSFETs having a gate oxide which has been N2O annealed at 1300 °C measured before and after anneal at 800 °C in a forming gas of 4% hydrogen and 96% inert gases. In Figure 6, line 200 illustrates field effect mobility for MOSFETs with a nitrided gate oxide before the anneal and line 202 after the anneal. As is seen in Figure 6, inversion channel mobility increases by almost 20% and the threshold voltage is reduced by 2 V.
In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.

Claims

That which is claimed is:
1. A method of forming an insulator in a silicon carbide electronic device, comprising: fabricating a nitrided oxide layer on a layer of silicon carbide; and annealing the nitrided oxide layer in an environment containing hydrogen.
2. The method according to Claim 1, wherein the silicon carbide layer comprises 4H polytype silicon carbide.
3. The method according to Claim 1, wherein the silicon carbide layer comprises a silicon carbide layer on a non-silicon carbide substrate.
4. The method according to Claim 1, wherein the silicon carbide layer comprises a portion of a silicon carbide substrate.
5. The method of Claim 1 , wherein the step of fabricating a nitrided oxide layer comprises at least one of forming the oxide layer in at least one of nitric oxide and nitrous oxide and annealing an existing oxide layer in at least one of nitric oxide and nitrous oxide.
6. The method of Claim 1, wherein the step of fabricating a nitrided oxide layer comprises the steps of: fabricating an oxide layer; and fabricating a nitride layer on the oxide layer so as to nitridate the oxide layer on which the nitride layer is fabricated.
7. The method of Claim 6, wherein the step of annealing the oxide layer in an environment containing hydrogen is provided substantially concurrently with the step of fabricating the nitride layer so that the step of fabricating a nitride layer on the oxide layer comprises fabricating a nitride layer on the oxide layer so as to nitridate and hydrogenate the oxide layer on which the nitride layer is fabricated.
8. The method of Claim 1 , wherein the step of annealing the oxide layer comprises heating the oxide layer to a temperature of greater than about 400 °C in a hydrogen containing environment as part of another processing step.
9. The method of Claim 1 , wherein the step of annealing the oxide layer comprises annealing the oxide layer at a temperature of greater than about 400 °C in a hydrogen containing environment.
10. The method of Claim 1 , wherein the step of annealing the oxide layer comprises annealing the oxide layer at a temperature of less than about 900 °C in a hydrogen containing environment.
11. The method of Claim 1 , wherein the step of annealing the oxide layer comprises annealing the oxide layer at a temperature of between about 400 °C and about 1000 °C in a hydrogen containing environment.
12. The method of Claim 1 , wherein the step of annealing the oxide layer comprises annealing the oxide layer at a temperature of between about 400 °C and about 800 °C in a hydrogen containing environment.
13. The method of Claim 1 , further comprising the step of performing subsequent high temperature processing steps in a hydrogen containing environment.
14. The method of Claim 1, wherein the step of annealing is preceded by the step of forming metallization for a semiconductor device associated with the oxide layer.
15. The method of Claim 14, wherein the step of annealing the oxide layer comprises annealing the oxide layer at a temperature of less than about 900 °C in a hydrogen containing environment.
16. The method of Claim 15, wherein the step of annealing the oxide layer comprises a contact anneal.
17. The method of Claim 1 , wherein the step of annealing comprises annealing the oxide layer in forming gas having about 4% hydrogen and 96% inert gases.
18. The method of Claim 1 further comprising forming a silicon carbide metal oxide semiconductor device having the oxide layer as a gate oxide of the metal oxide semiconductor device.
19. The method of Claim 1 , wherein the step of annealing the oxide layer is carried out for at least about 2 minutes.
20. A method of fabricating an oxide layer on a silicon carbide layer, comprising: nitriding the oxide layer on the silicon carbide layer with at least one of nitric oxide and nitrous oxide; and annealing the nitrided oxide layer at a temperature of between about 400 °C about 900 °C in a hydrogen containing environment for at least about 2 minutes.
PCT/US2002/011691 2001-04-12 2002-04-12 Method of fabricating an oxide layer on a silicon carbide layer utilizing an anneal in a hydrogen environment WO2002084727A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP02733980A EP1378006B1 (en) 2001-04-12 2002-04-12 Method of fabricating an oxide layer on a silicon carbide layer utilizing an anneal in a hydrogen environment
JP2002581576A JP4781610B2 (en) 2001-04-12 2002-04-12 Method for producing an oxide layer on a silicon carbide layer by annealing in a hydrogen environment
DE60228695T DE60228695D1 (en) 2001-04-12 2002-04-12 METHOD FOR PRODUCING AN OXYDS LAYER IN A HYDROGEN ENVIRONMENT
CA2442929A CA2442929C (en) 2001-04-12 2002-04-12 Method of fabricating an oxide layer on a silicon carbide layer utilizing an anneal in a hydrogen environment
KR1020037013333A KR100855388B1 (en) 2001-04-12 2002-04-12 Method of fabricating an oxide layer on a silicon carbide layer utilizing an anneal in a hydrogen environment

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US09/834,283 US6610366B2 (en) 2000-10-03 2001-04-12 Method of N2O annealing an oxide layer on a silicon carbide layer
US09/834,283 2001-04-12
US29430701P 2001-05-30 2001-05-30
US60/294,307 2001-05-30
US10/045,542 2001-10-26
US10/045,542 US7067176B2 (en) 2000-10-03 2001-10-26 Method of fabricating an oxide layer on a silicon carbide layer utilizing an anneal in a hydrogen environment

Publications (2)

Publication Number Publication Date
WO2002084727A2 true WO2002084727A2 (en) 2002-10-24
WO2002084727A3 WO2002084727A3 (en) 2003-04-10

Family

ID=27366709

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/011691 WO2002084727A2 (en) 2001-04-12 2002-04-12 Method of fabricating an oxide layer on a silicon carbide layer utilizing an anneal in a hydrogen environment

Country Status (9)

Country Link
US (1) US7067176B2 (en)
EP (3) EP1378006B1 (en)
JP (1) JP4781610B2 (en)
KR (1) KR100855388B1 (en)
CN (1) CN100517607C (en)
AT (1) ATE407449T1 (en)
CA (1) CA2442929C (en)
DE (1) DE60228695D1 (en)
WO (1) WO2002084727A2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004025719A2 (en) * 2002-08-30 2004-03-25 Cree, Inc. Nitrogen passivation of interface states in sio2/sic structures
EP1523032A2 (en) * 2003-10-09 2005-04-13 Matsushita Electric Industrial Co., Ltd. Silicon carbide-oxide layered structure, production method thereof, and semiconductor device
US8686434B2 (en) 2007-12-04 2014-04-01 Sumitomo Electric Industries, Ltd. Silicon carbide semiconductor device and method for manufacturing the same

Families Citing this family (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6956238B2 (en) * 2000-10-03 2005-10-18 Cree, Inc. Silicon carbide power metal-oxide semiconductor field effect transistors having a shorting channel and methods of fabricating silicon carbide metal-oxide semiconductor field effect transistors having a shorting channel
US7431967B2 (en) * 2002-09-19 2008-10-07 Applied Materials, Inc. Limited thermal budget formation of PMD layers
US7141483B2 (en) * 2002-09-19 2006-11-28 Applied Materials, Inc. Nitrous oxide anneal of TEOS/ozone CVD for improved gapfill
US7221010B2 (en) 2002-12-20 2007-05-22 Cree, Inc. Vertical JFET limited silicon carbide power metal-oxide semiconductor field effect transistors
US7074643B2 (en) * 2003-04-24 2006-07-11 Cree, Inc. Silicon carbide power devices with self-aligned source and well regions and methods of fabricating same
US6979863B2 (en) * 2003-04-24 2005-12-27 Cree, Inc. Silicon carbide MOSFETs with integrated antiparallel junction barrier Schottky free wheeling diodes and methods of fabricating the same
US7528051B2 (en) * 2004-05-14 2009-05-05 Applied Materials, Inc. Method of inducing stresses in the channel region of a transistor
US7118970B2 (en) 2004-06-22 2006-10-10 Cree, Inc. Methods of fabricating silicon carbide devices with hybrid well regions
US7682988B2 (en) * 2004-08-31 2010-03-23 Texas Instruments Incorporated Thermal treatment of nitrided oxide to improve negative bias thermal instability
US7414268B2 (en) 2005-05-18 2008-08-19 Cree, Inc. High voltage silicon carbide MOS-bipolar devices having bi-directional blocking capabilities
US20060261346A1 (en) * 2005-05-18 2006-11-23 Sei-Hyung Ryu High voltage silicon carbide devices having bi-directional blocking capabilities and methods of fabricating the same
US7615801B2 (en) * 2005-05-18 2009-11-10 Cree, Inc. High voltage silicon carbide devices having bi-directional blocking capabilities
US7391057B2 (en) * 2005-05-18 2008-06-24 Cree, Inc. High voltage silicon carbide devices having bi-directional blocking capabilities
US7528040B2 (en) 2005-05-24 2009-05-05 Cree, Inc. Methods of fabricating silicon carbide devices having smooth channels
JP5033316B2 (en) * 2005-07-05 2012-09-26 日産自動車株式会社 Manufacturing method of semiconductor device
JP2007096263A (en) * 2005-08-31 2007-04-12 Denso Corp SiC SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME
US7727904B2 (en) 2005-09-16 2010-06-01 Cree, Inc. Methods of forming SiC MOSFETs with high inversion layer mobility
KR100790237B1 (en) * 2005-12-29 2008-01-02 매그나칩 반도체 유한회사 Method for fabricating the same of cmos image sensor in metal layer
US8432012B2 (en) 2006-08-01 2013-04-30 Cree, Inc. Semiconductor devices including schottky diodes having overlapping doped regions and methods of fabricating same
US7728402B2 (en) 2006-08-01 2010-06-01 Cree, Inc. Semiconductor devices including schottky diodes with controlled breakdown
WO2008020911A2 (en) 2006-08-17 2008-02-21 Cree, Inc. High power insulated gate bipolar transistors
ATE531076T1 (en) * 2006-09-01 2011-11-15 Nxp Bv METHOD FOR IMPROVING THE MOBILITY OF AN INVERSION LAYER IN A SILICON CARBIDE MOSFET
US8835987B2 (en) 2007-02-27 2014-09-16 Cree, Inc. Insulated gate bipolar transistors including current suppressing layers
JP2008244455A (en) * 2007-02-28 2008-10-09 Denso Corp Silicon carbide semiconductor device and manufacturing method thereof
TWI335674B (en) * 2007-07-11 2011-01-01 Univ Nat Taiwan Methos for forming an insulating layer over a silicon carbide substrate, silicon carbide transistors and methods for fabricating the same
US8232558B2 (en) 2008-05-21 2012-07-31 Cree, Inc. Junction barrier Schottky diodes with current surge capability
US8217398B2 (en) * 2008-10-15 2012-07-10 General Electric Company Method for the formation of a gate oxide on a SiC substrate and SiC substrates and devices prepared thereby
JP4911263B2 (en) * 2009-03-11 2012-04-04 三菱電機株式会社 Method for manufacturing silicon carbide semiconductor device
US8288220B2 (en) 2009-03-27 2012-10-16 Cree, Inc. Methods of forming semiconductor devices including epitaxial layers and related structures
US8294507B2 (en) 2009-05-08 2012-10-23 Cree, Inc. Wide bandgap bipolar turn-off thyristor having non-negative temperature coefficient and related control circuits
US8629509B2 (en) 2009-06-02 2014-01-14 Cree, Inc. High voltage insulated gate bipolar transistors with minority carrier diverter
US8193848B2 (en) 2009-06-02 2012-06-05 Cree, Inc. Power switching devices having controllable surge current capabilities
US8541787B2 (en) 2009-07-15 2013-09-24 Cree, Inc. High breakdown voltage wide band-gap MOS-gated bipolar junction transistors with avalanche capability
US8354690B2 (en) 2009-08-31 2013-01-15 Cree, Inc. Solid-state pinch off thyristor circuits
US9117739B2 (en) 2010-03-08 2015-08-25 Cree, Inc. Semiconductor devices with heterojunction barrier regions and methods of fabricating same
US8415671B2 (en) 2010-04-16 2013-04-09 Cree, Inc. Wide band-gap MOSFETs having a heterojunction under gate trenches thereof and related methods of forming such devices
JP2012004270A (en) * 2010-06-16 2012-01-05 Sumitomo Electric Ind Ltd Method of cleaning silicon carbide semiconductor, silicon carbide semiconductor, and silicon carbide semiconductor device
JP2012064873A (en) 2010-09-17 2012-03-29 Rohm Co Ltd Semiconductor device and method of manufacturing the same
US9142662B2 (en) 2011-05-06 2015-09-22 Cree, Inc. Field effect transistor devices with low source resistance
US9029945B2 (en) 2011-05-06 2015-05-12 Cree, Inc. Field effect transistor devices with low source resistance
CN102810465B (en) * 2011-06-02 2015-09-30 中国科学院微电子研究所 One grows SiO in SiC material 2the method of passivation layer
US9984894B2 (en) 2011-08-03 2018-05-29 Cree, Inc. Forming SiC MOSFETs with high channel mobility by treating the oxide interface with cesium ions
US8618582B2 (en) 2011-09-11 2013-12-31 Cree, Inc. Edge termination structure employing recesses for edge termination elements
US9373617B2 (en) 2011-09-11 2016-06-21 Cree, Inc. High current, low switching loss SiC power module
US8664665B2 (en) 2011-09-11 2014-03-04 Cree, Inc. Schottky diode employing recesses for elements of junction barrier array
US8680587B2 (en) 2011-09-11 2014-03-25 Cree, Inc. Schottky diode
WO2013036370A1 (en) 2011-09-11 2013-03-14 Cree, Inc. High current density power module comprising transistors with improved layout
US9640617B2 (en) 2011-09-11 2017-05-02 Cree, Inc. High performance power module
US9546420B1 (en) * 2012-10-08 2017-01-17 Sandia Corporation Methods of depositing an alpha-silicon-carbide-containing film at low temperature
US9018108B2 (en) 2013-01-25 2015-04-28 Applied Materials, Inc. Low shrinkage dielectric films
CN103165432B (en) * 2013-03-15 2016-08-03 上海华力微电子有限公司 A kind of preparation method of gate oxide
JP6425950B2 (en) * 2014-09-12 2018-11-21 株式会社Ｓｃｒｅｅｎホールディングス Semiconductor manufacturing method and semiconductor manufacturing apparatus
CN104658903A (en) * 2015-01-30 2015-05-27 株洲南车时代电气股份有限公司 Method for preparing SiC MOSFET gate oxide layer
DE102016112877B4 (en) 2015-09-07 2021-07-15 Fuji Electric Co., Ltd. A method of manufacturing a semiconductor device and a semiconductor manufacturing device used for the method
CN106449392A (en) * 2016-11-29 2017-02-22 东莞市广信知识产权服务有限公司 SiC surface passivation method
DE102018107966B4 (en) 2018-04-04 2022-02-17 Infineon Technologies Ag Method of forming a wide bandgap semiconductor device
CN115295407B (en) * 2022-09-29 2023-07-07 浙江大学杭州国际科创中心 Preparation method of gate oxide structure of SiC power device and gate oxide structure

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5972801A (en) * 1995-11-08 1999-10-26 Cree Research, Inc. Process for reducing defects in oxide layers on silicon carbide
US6165822A (en) * 1998-01-05 2000-12-26 Denso Corporation Silicon carbide semiconductor device and method of manufacturing the same
US20020072247A1 (en) * 2000-10-03 2002-06-13 Lipkin Lori A. Method of N2O growth of an oxide layer on a silicon carbide layer

Family Cites Families (71)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3924024A (en) 1973-04-02 1975-12-02 Ncr Co Process for fabricating MNOS non-volatile memories
CA1075437A (en) * 1975-07-28 1980-04-15 Malcolm E. Washburn Porous silicon oxynitride refractory shapes
US4466172A (en) 1979-01-08 1984-08-21 American Microsystems, Inc. Method for fabricating MOS device with self-aligned contacts
US4875083A (en) 1987-10-26 1989-10-17 North Carolina State University Metal-insulator-semiconductor capacitor formed on silicon carbide
US5030600A (en) * 1988-10-06 1991-07-09 Benchmark Structural Ceramics Corp. Novel sialon composition
JPH0766971B2 (en) 1989-06-07 1995-07-19 シャープ株式会社 Silicon carbide semiconductor device
JPH03157974A (en) 1989-11-15 1991-07-05 Nec Corp Vertical type field effect transistor
JPH0718056B2 (en) * 1990-04-27 1995-03-01 株式会社コロイドリサーチ Method for producing oxynitride ceramic fiber
JP2542448B2 (en) 1990-05-24 1996-10-09 シャープ株式会社 Field effect transistor and method of manufacturing the same
US5170455A (en) 1991-10-30 1992-12-08 At&T Bell Laboratories Optical connective device
US5459107A (en) 1992-06-05 1995-10-17 Cree Research, Inc. Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures
US6344663B1 (en) 1992-06-05 2002-02-05 Cree, Inc. Silicon carbide CMOS devices
US5726463A (en) 1992-08-07 1998-03-10 General Electric Company Silicon carbide MOSFET having self-aligned gate structure
US5587870A (en) 1992-09-17 1996-12-24 Research Foundation Of State University Of New York Nanocrystalline layer thin film capacitors
US5506421A (en) * 1992-11-24 1996-04-09 Cree Research, Inc. Power MOSFET in silicon carbide
KR100305123B1 (en) 1992-12-11 2001-11-22 비센트 비.인그라시아, 알크 엠 아헨 Static Random Access Memory Cells and Semiconductor Devices Containing These
JP2531572B2 (en) * 1993-08-09 1996-09-04 東芝セラミックス株式会社 Method for oxynitriding quartz glass and method for surface treatment
US5479316A (en) 1993-08-24 1995-12-26 Analog Devices, Inc. Integrated circuit metal-oxide-metal capacitor and method of making same
US5510630A (en) 1993-10-18 1996-04-23 Westinghouse Electric Corporation Non-volatile random access memory cell constructed of silicon carbide
JP3521246B2 (en) 1995-03-27 2004-04-19 沖電気工業株式会社 Field effect transistor and method of manufacturing the same
JPH11261061A (en) 1998-03-11 1999-09-24 Denso Corp Silicon carbide semiconductor device and its manufacture
JP4001960B2 (en) 1995-11-03 2007-10-31 フリースケール セミコンダクター インコーポレイテッド Method for manufacturing a semiconductor device having a nitrided oxide dielectric layer
US6136728A (en) 1996-01-05 2000-10-24 Yale University Water vapor annealing process
JPH09205202A (en) 1996-01-26 1997-08-05 Matsushita Electric Works Ltd Semiconductor device
US5877045A (en) 1996-04-10 1999-03-02 Lsi Logic Corporation Method of forming a planar surface during multi-layer interconnect formation by a laser-assisted dielectric deposition
US5763905A (en) 1996-07-09 1998-06-09 Abb Research Ltd. Semiconductor device having a passivation layer
US6002159A (en) 1996-07-16 1999-12-14 Abb Research Ltd. SiC semiconductor device comprising a pn junction with a voltage absorbing edge
US5939763A (en) 1996-09-05 1999-08-17 Advanced Micro Devices, Inc. Ultrathin oxynitride structure and process for VLSI applications
US6091077A (en) * 1996-10-22 2000-07-18 Matsushita Electric Industrial Co., Ltd. MIS SOI semiconductor device with RTD and/or HET
US6028012A (en) * 1996-12-04 2000-02-22 Yale University Process for forming a gate-quality insulating layer on a silicon carbide substrate
US5837572A (en) 1997-01-10 1998-11-17 Advanced Micro Devices, Inc. CMOS integrated circuit formed by using removable spacers to produce asymmetrical NMOS junctions before asymmetrical PMOS junctions for optimizing thermal diffusivity of dopants implanted therein
JP3206727B2 (en) 1997-02-20 2001-09-10 富士電機株式会社 Silicon carbide vertical MOSFET and method of manufacturing the same
DE19809554B4 (en) 1997-03-05 2008-04-03 Denso Corp., Kariya silicon carbide semiconductor device
US6063698A (en) 1997-06-30 2000-05-16 Motorola, Inc. Method for manufacturing a high dielectric constant gate oxide for use in semiconductor integrated circuits
JP3180895B2 (en) 1997-08-18 2001-06-25 富士電機株式会社 Method for manufacturing silicon carbide semiconductor device
EP1010204A1 (en) 1997-08-20 2000-06-21 Siemens Aktiengesellschaft Semiconductor structure comprising an alpha silicon carbide zone, and use of said semiconductor structure
US6239463B1 (en) 1997-08-28 2001-05-29 Siliconix Incorporated Low resistance power MOSFET or other device containing silicon-germanium layer
SE9704150D0 (en) 1997-11-13 1997-11-13 Abb Research Ltd Semiconductor device of SiC with insulating layer a refractory metal nitride layer
JPH11191559A (en) 1997-12-26 1999-07-13 Matsushita Electric Works Ltd Manufacture of mosfet
JP3216804B2 (en) 1998-01-06 2001-10-09 富士電機株式会社 Manufacturing method of silicon carbide vertical FET and silicon carbide vertical FET
JPH11266017A (en) 1998-01-14 1999-09-28 Denso Corp Silicon carbide semiconductor device and manufacture thereof
JPH11238742A (en) 1998-02-23 1999-08-31 Denso Corp Manufacture of silicon carbide semiconductor device
JP3893725B2 (en) 1998-03-25 2007-03-14 株式会社デンソー Method for manufacturing silicon carbide semiconductor device
US6627539B1 (en) 1998-05-29 2003-09-30 Newport Fab, Llc Method of forming dual-damascene interconnect structures employing low-k dielectric materials
US6107142A (en) 1998-06-08 2000-08-22 Cree Research, Inc. Self-aligned methods of fabricating silicon carbide power devices by implantation and lateral diffusion
US6100169A (en) 1998-06-08 2000-08-08 Cree, Inc. Methods of fabricating silicon carbide power devices by controlled annealing
US5960289A (en) 1998-06-22 1999-09-28 Motorola, Inc. Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region
JP4123636B2 (en) 1998-06-22 2008-07-23 株式会社デンソー Silicon carbide semiconductor device and manufacturing method thereof
JP3959856B2 (en) 1998-07-31 2007-08-15 株式会社デンソー Silicon carbide semiconductor device and manufacturing method thereof
US6221700B1 (en) 1998-07-31 2001-04-24 Denso Corporation Method of manufacturing silicon carbide semiconductor device with high activation rate of impurities
JP2000106371A (en) 1998-07-31 2000-04-11 Denso Corp Fabrication of silicon carbide semiconductor device
US6246076B1 (en) 1998-08-28 2001-06-12 Cree, Inc. Layered dielectric on silicon carbide semiconductor structures
JP2000133633A (en) 1998-09-09 2000-05-12 Texas Instr Inc <Ti> Etching of material using hard mask and plasma activating etchant
US6048766A (en) 1998-10-14 2000-04-11 Advanced Micro Devices Flash memory device having high permittivity stacked dielectric and fabrication thereof
US6204203B1 (en) 1998-10-14 2001-03-20 Applied Materials, Inc. Post deposition treatment of dielectric films for interface control
JP2000201050A (en) * 1998-11-02 2000-07-18 Ngk Insulators Ltd Substrate for surface acoustic wave device and manufacture of the same
US6190973B1 (en) 1998-12-18 2001-02-20 Zilog Inc. Method of fabricating a high quality thin oxide
US6228720B1 (en) 1999-02-23 2001-05-08 Matsushita Electric Industrial Co., Ltd. Method for making insulated-gate semiconductor element
JP3443589B2 (en) 1999-03-01 2003-09-02 独立行政法人産業技術総合研究所 Method for manufacturing semiconductor device
US6261976B1 (en) * 1999-03-18 2001-07-17 Chartered Semiconductor Manufacturing Ltd. Method of forming low pressure silicon oxynitride dielectrics having high reliability
US6238967B1 (en) 1999-04-12 2001-05-29 Motorola, Inc. Method of forming embedded DRAM structure
JP2000349081A (en) 1999-06-07 2000-12-15 Sony Corp Method for formation of oxide film
JP4192353B2 (en) 1999-09-21 2008-12-10 株式会社デンソー Silicon carbide semiconductor device and manufacturing method thereof
US6524877B1 (en) * 1999-10-26 2003-02-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, and method of fabricating the same
DE10036208B4 (en) 2000-07-25 2007-04-19 Siced Electronics Development Gmbh & Co. Kg Semiconductor structure with buried island area and contact area
CN1311534C (en) * 2000-10-03 2007-04-18 克里公司 Method of fabricating an oxide layer on a silicon carbide layer utilizing NO2
US6593620B1 (en) 2000-10-06 2003-07-15 General Semiconductor, Inc. Trench DMOS transistor with embedded trench schottky rectifier
US6600138B2 (en) * 2001-04-17 2003-07-29 Mattson Technology, Inc. Rapid thermal processing system for integrated circuits
US6707011B2 (en) * 2001-04-17 2004-03-16 Mattson Technology, Inc. Rapid thermal processing system for integrated circuits
US6632747B2 (en) * 2001-06-20 2003-10-14 Texas Instruments Incorporated Method of ammonia annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile
US7022378B2 (en) * 2002-08-30 2006-04-04 Cree, Inc. Nitrogen passivation of interface states in SiO2/SiC structures

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5972801A (en) * 1995-11-08 1999-10-26 Cree Research, Inc. Process for reducing defects in oxide layers on silicon carbide
US6165822A (en) * 1998-01-05 2000-12-26 Denso Corporation Silicon carbide semiconductor device and method of manufacturing the same
US20020072247A1 (en) * 2000-10-03 2002-06-13 Lipkin Lori A. Method of N2O growth of an oxide layer on a silicon carbide layer

Non-Patent Citations (11)

* Cited by examiner, † Cited by third party
Title
CHANG K C ET AL: "Observation of a non-stoichiometric layer at the silicon dioxide-silicon carbide interface: effect of oxidation temperature and post-oxidation processing conditions" SILICON CARBIDE - MATERIALS, PROCESSING AND DEVICES. SYMPOSIUM (MATERIALS RESEARCH SOCIETY SYMPOSIUM PROCEEDINGS VOL.640), SILICON CARBIDE - MATERIALS, PROCESSING AND DEVICES. SYMPOSIUM, BOSTON, MA, USA, 27-29 NOV. 2000, pages H5.45.1-6, XP008011342 2001, Warrendale, PA, USA, Mater. Res. Soc, USA ISBN: 1-55899-550-1 *
CHO W ET AL: "IMPROVEMENT OF CHARGE TRAPPING BY HYDROGEN POST-OXIDATION ANNEALINGIN GATE OXIDE OF 4H-SIC METAL-OXIDE-SEMICONDUCTOR CAPACITORS" APPLIED PHYSICS LETTERS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 77, no. 8, 21 August 2000 (2000-08-21), pages 1215-1217, XP000963434 ISSN: 0003-6951 *
FUKUDA K ET AL: "IMPROVEMENT OF SIO2/4H-SIC INTERFACE BY USING HIGH TEMPERATURE HYDROGEN ANNEALING AT 1000 DEG C" EXTENDED ABSTRACTS OF THE INTERNATIONAL CONFERENCE ON SOLID STATE DEVICES AND MATERIALS, JAPAN SOCIETY OF APPLIED PHYSICS. TOKYO, JA, September 1998 (1998-09), pages 100-101, XP000823091 *
FUKUDA K ET AL: "IMPROVEMENT OF SIO2/4H-SIC INTERFACE USING HIGH-TEMPERATURE HYDROGEN ANNEALING AT LOW PRESSURE AND VACUUM ANNEALING" JAPANESE JOURNAL OF APPLIED PHYSICS, PUBLICATION OFFICE JAPANESE JOURNAL OF APPLIED PHYSICS. TOKYO, JP, vol. 38, no. 4Bpart 1, April 1999 (1999-04), pages 2306-2309, XP000923619 ISSN: 0021-4922 *
LAI P T ET AL: "Interface properties of N2O-annealed NH3-treated 6H-SiC MOS capacitor" ELECTRON DEVICES MEETING, 1999. PROCEEDINGS. 1999 IEEE HONG KONG SHATIN, HONG KONG 26 JUNE 1999, PISCATAWAY, NJ, USA,IEEE, US, 1999, pages 46-49, XP010377056 ISBN: 0-7803-5648-9 *
LEONHARD C ET AL: "Long term stability of gate-oxides on n- and p-type silicon carbide studied by charge injection techniques" MATERIALS SCIENCE AND ENGINEERING B, ELSEVIER SEQUOIA, LAUSANNE, CH, vol. 46, no. 1-3, 1 April 1997 (1997-04-01), pages 263-266, XP004085324 ISSN: 0921-5107 *
LIPKIN L ET AL: "CHALLENGES AND STATE-OF-THE-ART OF OXIDES ON SIC" MATERIALS RESEARCH SOCIETY SYMPOSIUM PROCEEDINGS, MATERIALS RESEARCH SOCIETY, PITTSBURG, PA, US, no. 640, 27 November 2000 (2000-11-27), pages H3101-H3110, XP008002243 ISSN: 0272-9172 *
See also references of EP1378006A2 *
SUZUKI S ET AL: "Effect of post-oxidation-annealing in hydrogen on SiO/sub 2//4H-SiC interface" INTERNATIONAL CONFERENCE ON SILICON CARBIDE AND RELATED MATERIALS, ICSRM'99, RESEARCH TRIANGLE PARK, NC, USA, 10-15 OCT. 1999, vol. 338-342, pt.2, pages 1073-1076, XP008011299 Materials Science Forum, 2000, Trans Tech Publications, Switzerland ISSN: 0255-5476 *
WANG X W ET AL: "HIGH-TEMPERATURE CHARACTERISTICS OF HIGH-QUALITY SIC MIS CAPACITORS WITH O/N/O GATE DIELECTRIC" IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE INC. NEW YORK, US, vol. 47, no. 2, February 2000 (2000-02), pages 458-462, XP000947257 ISSN: 0018-9383 *
XU J P ET AL: "IMPROVED PERFORMANCE AND RELIABILITY OF N2O-GROWN OXYNITRIDE ON 6H-SIC" IEEE ELECTRON DEVICE LETTERS, IEEE INC. NEW YORK, US, vol. 21, no. 6, June 2000 (2000-06), pages 298-300, XP000951967 ISSN: 0741-3106 cited in the application *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004025719A2 (en) * 2002-08-30 2004-03-25 Cree, Inc. Nitrogen passivation of interface states in sio2/sic structures
WO2004025719A3 (en) * 2002-08-30 2004-06-03 Cree Inc Nitrogen passivation of interface states in sio2/sic structures
US7022378B2 (en) 2002-08-30 2006-04-04 Cree, Inc. Nitrogen passivation of interface states in SiO2/SiC structures
EP1523032A2 (en) * 2003-10-09 2005-04-13 Matsushita Electric Industrial Co., Ltd. Silicon carbide-oxide layered structure, production method thereof, and semiconductor device
EP1523032A3 (en) * 2003-10-09 2007-09-26 Matsushita Electric Industrial Co., Ltd. Silicon carbide-oxide layered structure, production method thereof, and semiconductor device
US7709403B2 (en) 2003-10-09 2010-05-04 Panasonic Corporation Silicon carbide-oxide layered structure, production method thereof, and semiconductor device
US8686434B2 (en) 2007-12-04 2014-04-01 Sumitomo Electric Industries, Ltd. Silicon carbide semiconductor device and method for manufacturing the same

Also Published As

Publication number Publication date
KR20040002908A (en) 2004-01-07
EP2259288A3 (en) 2011-01-05
ATE407449T1 (en) 2008-09-15
CN100517607C (en) 2009-07-22
US7067176B2 (en) 2006-06-27
EP2259288A2 (en) 2010-12-08
CN1531746A (en) 2004-09-22
JP4781610B2 (en) 2011-09-28
EP1378006A2 (en) 2004-01-07
EP1968119B1 (en) 2011-11-23
EP1968119A2 (en) 2008-09-10
EP1378006B1 (en) 2008-09-03
DE60228695D1 (en) 2008-10-16
CA2442929A1 (en) 2002-10-24
EP2259288B1 (en) 2012-12-05
WO2002084727A3 (en) 2003-04-10
CA2442929C (en) 2012-06-26
JP2004532522A (en) 2004-10-21
EP1968119A3 (en) 2008-10-22
KR100855388B1 (en) 2008-09-04
US20020102358A1 (en) 2002-08-01

Similar Documents

Publication Publication Date Title
US7067176B2 (en) Method of fabricating an oxide layer on a silicon carbide layer utilizing an anneal in a hydrogen environment
US6610366B2 (en) Method of N2O annealing an oxide layer on a silicon carbide layer
US6767843B2 (en) Method of N2O growth of an oxide layer on a silicon carbide layer
CA2421003C (en) Method of fabricating an oxide layer on a silicon carbide layer utilizing n2o
EP1532672B1 (en) Nitrogen passivation of interface states in sio 2/sic structures
US8119539B2 (en) Methods of fabricating oxide layers on silicon carbide layers utilizing atomic oxygen
WO2007118031A2 (en) Silicon oxynitride gate dielectric formation using multiple annealing steps

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SD SE SG SI SK SL TJ TM TN TR TT TZ UA UG UZ VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 2002733980

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2442929

Country of ref document: CA

WWE Wipo information: entry into national phase

Ref document number: 028081072

Country of ref document: CN

Ref document number: 1020037013333

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 2002581576

Country of ref document: JP

WWP Wipo information: published in national office

Ref document number: 2002733980

Country of ref document: EP

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642