WO2002095763A1 - Testverfahren zum testen eines datenspeichers - Google Patents
Testverfahren zum testen eines datenspeichers Download PDFInfo
- Publication number
- WO2002095763A1 WO2002095763A1 PCT/EP2002/005358 EP0205358W WO02095763A1 WO 2002095763 A1 WO2002095763 A1 WO 2002095763A1 EP 0205358 W EP0205358 W EP 0205358W WO 02095763 A1 WO02095763 A1 WO 02095763A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- data
- test
- test data
- memory
- bus
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/40—Response verification devices using compression techniques
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
Definitions
- the invention relates to a test method for testing a data memory and a data memory with an integrated test data compression circuit for inexpensive testing of fast semiconductor memories, in particular DRAM memories, SRAM memories, which operate at very high operating clock frequencies.
- a circuit DUT (DUT: device unde test) to be tested is connected to an external test device via a control bus, a data bus and an address bus.
- the external test device generates test data in a test data generator, which are applied to the memory DUT to be tested via data bus lines of a data bus.
- the memory cells to be tested are addressed within the memory to be tested via the address bus.
- the test data are addressed in the
- Memory cells are written in via the data bus and then read out again.
- the external test device compares the written test data with the read data and recognizes from the deviations or data errors whether the addressed memory cells within the memory are functional.
- FIG. 2 shows flowcharts in the test arrangement shown in FIG. 1 according to the prior art.
- the test device transmits the test data over a data line with a high
- the test device receives a test data sequence on each data line of the data bus, which in the example shown in FIG. 2 consists of four test data. Such a test data sequence is also referred to as a data burst.
- the test device generates an internal strobe signal, with each received strobe signal having a received test date with a stored the reference date within the test device is compared so that data deviations can be determined. These data deviations indicate that the addressed memory cell within the data memory is faulty.
- Modern data memories work with ever higher operating clock frequencies, so that the data transmission rates with which the test data are written into the memory cells and subsequently read out again are also becoming ever higher. Therefore, the operating cycle frequency of the external test device in which the evaluation of the read test data takes place must also be increased.
- the clock frequency of the strobe signal corresponds to the data transmission rate of the read test data.
- test device is also adapted accordingly. Due to the ever shorter development cycles for the development of modern data storage devices, which work with ever higher data transfer rates, developed data storage devices can in many cases no longer be used for testing. With very high data transfer rates of the data memory to be tested, test devices are therefore required which are relatively complex in terms of circuit technology and are therefore cost-intensive.
- the invention provides a test method for testing a data memory, in which a plurality of test data of a test data sequence, which are read out serially from the data memory, are compared with reference test data for generating a compressed display date, the display date indicating whether at least one data error has occurred in the test data sequence.
- the test data sequence preferably consists of a predetermined number of test data bits.
- the test data sequence is preferably generated in a test data generator of an external test device and written into a memory cell field of the data memory via a data line of a data bus, the written test data sequence subsequently being read out again from the memory cell field via a data line of the data bus and by a compression circuit integrated in the data memory according to a compression factor is compressed to a display date, the display date being output from the data memory to the external test device for data evaluation via an associated display line of a display data bus.
- the compression factor is preferably equal to the * number of test data bits in a test data sequence.
- test data are preferably written into the memory cell array of the data memory at a first data transfer rate from the external test device and the display data are output from the data memory into the external test device at a second data transfer rate, the ratio of the first data transfer rate to the second data transfer rate corresponding to the compression factor ,
- the read test data of a test data sequence is serially written into a test data register of the compression circuit and compared bit by bit with the reference data, which are stored in a reference register of the compression circuit, by means of a logic comparison circuit for generating a display date.
- the reference data is written into the reference data register of the compression circuit in an initialization operating mode by the external test device.
- the invention also provides a data memory with an integrated test data compression circuit, the data memory comprising: a memory cell array with a multiplicity of addressable memory cells,
- Write / read amplifier for writing and reading data into the memory cells via an internal data bus of the data memory, and a test data compression circuit, which follow several test data, each from the memory cell array in one
- Test operating mode which is read out serially via a data line of the internal data bus, is compressed with stored reference test data sequences in order to generate a respective display date which indicates whether at least one data error has occurred in the read test data sequence.
- the display data generated by the test data compression circuit are each transmitted from the data memory to an external test device for further data evaluation via a display data line of a display data bus.
- the data memory preferably contains a controllable switching unit which is connected between an external data bus for data exchange with the external test device, the internal data bus for data exchange with the memory cell array and the data compression circuit.
- the controllable switching unit can preferably be switched over between control lines by the external test device between a normal operating mode and a test operating mode, wherein in the test operating mode the test data of a test data sequence read out via a data line of the internal data bus are serially transmitted through the switching unit via a data line of an internal test data bus into a test data register of the test data compression circuit be registered.
- the external data bus, the internal data bus, the test data bus and the display data bus preferably have the same bus width.
- the test data compression circuit contains a plurality of test data compression circuit modules, each of which has a test data register for storing a test data sequence read from the memory field via a data line of the test data bus / a reference data register for storing a reference test data sequence, and a logic comparison circuit compare the stored test data sequence with the stored reference test data sequence to generate a display date.
- the logic comparison circuit is preferably an XOR logic circuit.
- test method according to the invention and the data memory according to the invention for explaining features essential to the invention is described below with reference to the attached figures.
- 1 shows a test arrangement according to the prior art
- 2 shows a flowchart to explain the problem on which the invention is based
- FIG. 3 shows a block diagram of a preferred embodiment of the data memory according to the invention.
- FIG. 4 shows a block diagram of a test data compression circuit contained in the data memory according to the invention with a plurality of test data compression modules;
- Fig. 5 is a block diagram of a test data compression circuit module within the test data compression circuit shown in Fig. 4;
- FIG. 6 shows a flow chart of test signals during the execution of the test method according to the invention.
- FIG. 3 shows a block diagram of a data memory 1 according to the invention, which has an external bus 3, an external data bus 3 and a display data bus 4
- the address bus 2 is connected to a column address decoder 6 and a row address decoder 7, which decode the applied addresses and activate memory cells within a memory cell array 10 via lines 8, 9.
- the memory cell array 10 is over
- Read / write amplifier 11 connected to an internal data bus 12 of data memory 1.
- a controllable switching unit 13 is provided between the external data bus 3 and the internal data bus 12 and can be controlled by the external test device 5 via control lines 14.
- a test data compression circuit 16 is connected to the switching unit 13 via an internal test data bus 15.
- test data compression circuit 16 is connected to the switching unit 13 via data lines 15-i.
- the data bus width of the test data bus 15 between the switching tion unit 13 and the integrated test data compression circuit 16 corresponds to the data bus width of the external data bus 3 and the internal data bus 12.
- the test data compression circuit contains D test data compression circuit modules 17-i, each of which generates a display data which is transmitted via a " display data line 4-i the external test device 5 is released for further data evaluation.
- the test data compression circuit module 17 receives, via a data line of the internal test data bus 15, a test data sequence read from the memory cell array 10 and consisting of several test data bits.
- the received test data sequence is written into a clocked test data register 20 in series via a controllable internal switch 18 and a data line 19.
- the test data register contains a memory location 21 for each test data bit in the test data sequence.
- the number M of memory locations 21 corresponds to the number of test data bits within a test data sequence or a test data burst.
- Each test data circuit module 17-i contains a clocked reference data register 22 for storing reference test data.
- the reference data register 22 is also connected via a line 23 to the controllable changeover switch 18, which is controlled by the external test device 5 via a control line 24.
- the clocked reference data register 22 contains a plurality of memory locations 25 for reference data bits.
- the reference data register 22 stores M reference data bits which are written into the reference data register 22 by the external test device 5 during an initialization phase.
- the memory locations 21 within the test data register 20 are connected via lines 26 and the memory locations 25 within the test data register 22 are connected via lines 27 to inputs of XOR gates 28 of a data comparison circuit 29 within the data compression circuit module 17.
- the XOR gates 28 are connected via lines 30 to an XOR circuit 31, which outputs a display date on the output side via a display line 4-i of the display data bus 4 to the external test device 5.
- the data comparison circuit 29 carries out a bit-wise data comparison of the target data or reference data contained in the reference data register 22 with the test data of the test data sequence read out from the memory cell array 10. If a test data bit of the test data sequence written into the test data register 20 deviates from the associated reference data bit stored in the reference data register 22 due to an incorrectly produced memory cell, a display date is generated at the output of the data comparison circuit 29, which indicates that at least one data error in the temporarily stored test data sequence 1 occurred.
- FIG. 6 shows timing diagrams during a test procedure according to the test method according to the invention for testing the data memory 1 shown in FIG. 3.
- the memory cell field 10 of the data memory 1 becomes a test data sequence which, in the example shown in FIG. 6, consists of four test data bits. read out and serially applied via a data line of the internal data bus 12 and the internal test data bus 15 to a test data compression circuit module 17 and there serially written into its test data register 20.
- the data comparison circuit 29 generates a display date or pass fail signal which is output to the external test device for further data evaluation via a display data line of the display data bus 4. The evaluation of the display date by the external test device 5 takes place with the strobe signal.
- the external test device 5 can operate at a clock frequency that is lower by the data compression factor K than in the conventional test arrangement.
- Each test data compression circuit module 17 within the compression circuit 16 carries out a test data compression with a test data compression factor K, which corresponds to the number of test data bits within a test data sequence.
- the test data sequence or the test data burst is four data bits, which are compressed by a test data compression circuit module 17 to a display date, ie the test data compression factor K is four in the example shown in FIG. 6.
- test method it is possible either to reduce the test duration in accordance with the test data compression factor K or to reduce the maximum working frequency of the data input and data outputs required in the external test device in accordance with the test data compression factor K.
- This makes it possible to use existing circuitry-less complex conventional test devices for testing data memories that work at a very high operating clock frequency.
- Test data compression circuit modules 18. Controllable switching device
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE50209927T DE50209927D1 (de) | 2001-05-21 | 2002-05-15 | Testverfahren zum testen eines datenspeichers |
EP02750932A EP1389336B1 (de) | 2001-05-21 | 2002-05-15 | Testverfahren zum testen eines datenspeichers |
KR1020037015152A KR100578293B1 (ko) | 2001-05-21 | 2002-05-15 | 데이터 저장장치를 테스트하기 위한 테스트 방법 |
US10/478,403 US7428662B2 (en) | 2001-05-21 | 2002-05-15 | Testing a data store using an external test unit for generating test sequence and receiving compressed test results |
JP2002592135A JP3924539B2 (ja) | 2001-05-21 | 2002-05-15 | データストアをテストするテスト方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10124923.3 | 2001-05-21 | ||
DE10124923.3A DE10124923B4 (de) | 2001-05-21 | 2001-05-21 | Testverfahren zum Testen eines Datenspeichers und Datenspeicher mit integrierter Testdatenkompressionsschaltung |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2002095763A1 true WO2002095763A1 (de) | 2002-11-28 |
Family
ID=7685725
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2002/005358 WO2002095763A1 (de) | 2001-05-21 | 2002-05-15 | Testverfahren zum testen eines datenspeichers |
Country Status (8)
Country | Link |
---|---|
US (1) | US7428662B2 (de) |
EP (1) | EP1389336B1 (de) |
JP (1) | JP3924539B2 (de) |
KR (1) | KR100578293B1 (de) |
CN (1) | CN100353461C (de) |
DE (2) | DE10124923B4 (de) |
TW (1) | TW594774B (de) |
WO (1) | WO2002095763A1 (de) |
Cited By (2)
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CN100444286C (zh) * | 2003-08-06 | 2008-12-17 | 因芬奈昂技术股份有限公司 | 存储单元信号窗测试方法和设备 |
CN108039190A (zh) * | 2017-12-15 | 2018-05-15 | 北京京存技术有限公司 | 一种测试方法及装置 |
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JP4184036B2 (ja) * | 2002-10-25 | 2008-11-19 | 株式会社ルネサステクノロジ | 半導体記憶装置およびそのテスト方法 |
DE102004040799A1 (de) * | 2004-08-23 | 2006-03-09 | Infineon Technologies Ag | Testverfahren zum Testen eines Datenspeichers mit Baustein interner Speicherung der Testergebnisse |
US20070070740A1 (en) * | 2005-09-28 | 2007-03-29 | Hynix Semiconductor Inc. | Semiconductor memory device having data-compress test mode |
US7549092B2 (en) | 2005-09-29 | 2009-06-16 | Hynix Semiconductor, Inc. | Output controller with test unit |
US20070226553A1 (en) * | 2006-03-21 | 2007-09-27 | Khaled Fekih-Romdhane | Multiple banks read and data compression for back end test |
TWI327732B (en) | 2007-03-03 | 2010-07-21 | Nanya Technology Corp | Memory device and related testing method |
CN100454318C (zh) * | 2007-04-29 | 2009-01-21 | 哈尔滨工业大学 | 适用于多扫描链设计芯核的soc测试数据的压缩方法 |
DE102007049354A1 (de) * | 2007-10-15 | 2009-04-16 | Robert Bosch Gmbh | Verfahren zum Testen eines Adressbusses in einem logischen Baustein |
KR101431272B1 (ko) * | 2008-01-30 | 2014-08-20 | 엘지전자 주식회사 | 외장형 스토리지가 연결 접속된 보안기기에서의 비트레이트 조정 장치 및 방법 |
KR101535228B1 (ko) * | 2009-05-13 | 2015-07-08 | 삼성전자주식회사 | 빌트 오프 테스트 장치 |
CN102609340B (zh) * | 2011-01-25 | 2016-12-07 | 北京百卓网络技术有限公司 | 测试数据整理系统及方法 |
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GB2498980A (en) * | 2012-02-01 | 2013-08-07 | Inside Secure | Device and method to perform a parallel memory test |
TWI459400B (zh) * | 2012-04-17 | 2014-11-01 | Phison Electronics Corp | 記憶體儲存裝置、及其記憶體控制器與電源控制方法 |
KR20130131992A (ko) * | 2012-05-25 | 2013-12-04 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치의 테스트 회로 및 테스트 방법 |
TWI512623B (zh) * | 2013-12-26 | 2015-12-11 | Phison Electronics Corp | 休眠模式啓動方法、記憶體控制電路單元及儲存裝置 |
CN105719702A (zh) * | 2016-01-26 | 2016-06-29 | 中国科学院微电子研究所 | 改进型存储器错误检测方法及装置 |
DE102017210851A1 (de) * | 2017-06-28 | 2019-01-03 | Robert Bosch Gmbh | Integrierte Schaltung und ASIC |
CN110729018B (zh) * | 2019-09-06 | 2021-06-01 | 天津大学 | 基于识别动态故障模式的存储器诊断数据压缩方法 |
CN115312110A (zh) * | 2021-05-08 | 2022-11-08 | 瑞昱半导体股份有限公司 | 芯片验证系统及其验证方法 |
TWI800925B (zh) * | 2021-09-17 | 2023-05-01 | 瑞昱半導體股份有限公司 | 測試系統以及測試方法 |
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- 2001-05-21 DE DE10124923.3A patent/DE10124923B4/de not_active Expired - Fee Related
-
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- 2002-05-15 US US10/478,403 patent/US7428662B2/en not_active Expired - Fee Related
- 2002-05-15 EP EP02750932A patent/EP1389336B1/de not_active Expired - Lifetime
- 2002-05-15 WO PCT/EP2002/005358 patent/WO2002095763A1/de active IP Right Grant
- 2002-05-15 KR KR1020037015152A patent/KR100578293B1/ko not_active IP Right Cessation
- 2002-05-15 JP JP2002592135A patent/JP3924539B2/ja not_active Expired - Fee Related
- 2002-05-15 CN CNB028098463A patent/CN100353461C/zh not_active Expired - Fee Related
- 2002-05-15 DE DE50209927T patent/DE50209927D1/de not_active Expired - Fee Related
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CN108039190A (zh) * | 2017-12-15 | 2018-05-15 | 北京京存技术有限公司 | 一种测试方法及装置 |
Also Published As
Publication number | Publication date |
---|---|
US20040151037A1 (en) | 2004-08-05 |
US7428662B2 (en) | 2008-09-23 |
DE10124923A1 (de) | 2002-12-12 |
EP1389336A1 (de) | 2004-02-18 |
DE50209927D1 (de) | 2007-05-24 |
DE10124923B4 (de) | 2014-02-06 |
JP3924539B2 (ja) | 2007-06-06 |
KR20040008185A (ko) | 2004-01-28 |
JP2004531848A (ja) | 2004-10-14 |
EP1389336B1 (de) | 2007-04-11 |
KR100578293B1 (ko) | 2006-05-11 |
TW594774B (en) | 2004-06-21 |
CN1509478A (zh) | 2004-06-30 |
CN100353461C (zh) | 2007-12-05 |
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