WO2002099661A3 - Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device - Google Patents

Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device Download PDF

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Publication number
WO2002099661A3
WO2002099661A3 PCT/US2002/017849 US0217849W WO02099661A3 WO 2002099661 A3 WO2002099661 A3 WO 2002099661A3 US 0217849 W US0217849 W US 0217849W WO 02099661 A3 WO02099661 A3 WO 02099661A3
Authority
WO
WIPO (PCT)
Prior art keywords
data
memory device
arrival
capture
accurately aligning
Prior art date
Application number
PCT/US2002/017849
Other languages
French (fr)
Other versions
WO2002099661A2 (en
Inventor
Brian Johnson
Brent Keeth
Troy A Manning
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to EP02739714A priority Critical patent/EP1407455A2/en
Priority to KR1020037016031A priority patent/KR100596177B1/en
Priority to AU2002312350A priority patent/AU2002312350A1/en
Priority to JP2003502706A priority patent/JP4672978B2/en
Publication of WO2002099661A2 publication Critical patent/WO2002099661A2/en
Publication of WO2002099661A3 publication Critical patent/WO2002099661A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration

Abstract

A method and apparatus for accurately determining the actual arrival of data at a memory device relative to the write clock to accurately align the start of data capture and the arrival of the data at the memory device is disclosed. The actual time of arrival of data at the inputs to a memory device is determined by sending back-to-back write commands along with the predetermined data pattern to the memory device. The data pattern is stored in a register and any difference between the predicted arrival time of the data and the actual arrival time of the data is determined by logic circuitry. Any determined difference can then be compensated for by delaying the start of the capture of the data at the memory device, thereby accurately aligning the start of the data capture and the arrival of the data at the memory device.
PCT/US2002/017849 2001-06-06 2002-06-06 Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device WO2002099661A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP02739714A EP1407455A2 (en) 2001-06-06 2002-06-06 Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device
KR1020037016031A KR100596177B1 (en) 2001-06-06 2002-06-06 Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device
AU2002312350A AU2002312350A1 (en) 2001-06-06 2002-06-06 Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device
JP2003502706A JP4672978B2 (en) 2001-06-06 2002-06-06 Method and apparatus for measuring actual write latency and accurately aligning start of data capture with arrival of data at memory device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/874,289 2001-06-06
US09/874,289 US6697926B2 (en) 2001-06-06 2001-06-06 Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device

Publications (2)

Publication Number Publication Date
WO2002099661A2 WO2002099661A2 (en) 2002-12-12
WO2002099661A3 true WO2002099661A3 (en) 2003-11-13

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/017849 WO2002099661A2 (en) 2001-06-06 2002-06-06 Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device

Country Status (7)

Country Link
US (1) US6697926B2 (en)
EP (1) EP1407455A2 (en)
JP (2) JP4672978B2 (en)
KR (1) KR100596177B1 (en)
CN (1) CN100565481C (en)
AU (1) AU2002312350A1 (en)
WO (1) WO2002099661A2 (en)

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Also Published As

Publication number Publication date
US6697926B2 (en) 2004-02-24
WO2002099661A2 (en) 2002-12-12
US20020188816A1 (en) 2002-12-12
JP2004529453A (en) 2004-09-24
AU2002312350A1 (en) 2002-12-16
JP4672978B2 (en) 2011-04-20
JP5044805B2 (en) 2012-10-10
CN100565481C (en) 2009-12-02
JP2009104651A (en) 2009-05-14
KR20040016881A (en) 2004-02-25
KR100596177B1 (en) 2006-07-03
CN1636196A (en) 2005-07-06
EP1407455A2 (en) 2004-04-14

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