WO2002103785A2 - Cmos process - Google Patents
Cmos process Download PDFInfo
- Publication number
- WO2002103785A2 WO2002103785A2 PCT/US2002/019074 US0219074W WO02103785A2 WO 2002103785 A2 WO2002103785 A2 WO 2002103785A2 US 0219074 W US0219074 W US 0219074W WO 02103785 A2 WO02103785 A2 WO 02103785A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- conductivity type
- buried
- regions
- silicon
- silicon substrate
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 39
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 189
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 189
- 239000010703 silicon Substances 0.000 claims abstract description 189
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 142
- 239000000758 substrate Substances 0.000 claims abstract description 103
- 229920005591 polysilicon Polymers 0.000 claims description 61
- 238000000151 deposition Methods 0.000 claims description 25
- 230000002441 reversible effect Effects 0.000 description 14
- 239000007943 implant Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000002513 implantation Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000004075 alteration Effects 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000012356 Product development Methods 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000003909 pattern recognition Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/57—Protection from inspection, reverse engineering or tampering
- H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
Definitions
- the present invention relates to the prevention of reverse engineering of integrated circuits, and more particularly to an integrated circuit structure comprising a programmable connector/isolator between polysilicon (i.e. polycrystalline silicon) and source/ drain N+ or P+ regions, to be used in a MOS-type circuit, like nMOS, pMOS or CMOS, and a single or double polysilicon layer CMOS process with buried contact using a programmable connector/isolator.
- a programmable connector/isolator between polysilicon (i.e. polycrystalline silicon) and source/ drain N+ or P+ regions
- transistor sizes and metal connection routings are modified, to eliminate keys by which the reverse engineer can find inputs, outputs, gate lines etc. as keys to the circuit functionality.
- the reverse engineer is forced to examine every transistor within the IC to determine functionality and connectivity, so that he is prevented from making effective progress. In this way, the task for the reverse engineer to discover the entire functionality of an IC containing many tens of thousands transistors is clearly impractical.
- the present invention prevents the above cited automatic, high level taxonomic approaches from working because the apparent routing of the signal to a transistor is broken in a way that is very difficult to detect.
- the protection is applied via the programming of the masks, under instruction from the circuit designer, and fits unobtrusively and cost-effectively within the standard, commercial IC process.
- an integrated circuit structure for MOS-type devices comprising: a silicon substrate of a first conductivity type; first gate insulating regions selectively placed over the silicon substrate of the first conductivity type; a first polycrystalline silicon layer selectively placed over the silicon substrate of the first conductivity type; second gate insulating regions selectively placed over the first gate insulating regions and the first polycrystalline silicon layer; a second polycrystalline silicon layer selectively placed over the second gate insulating regions; first buried silicon regions of a second conductivity type, buried within the silicon substrate of the first conductivity type, placed under the first polycrystalline silicon layer and in contact therewith; and second buried silicon regions of the second conductivity type, buried within the silicon substrate of the first conductivity type, placed under the second gate insulating regions, under the second polycrystalline silicon layer and insulated therefrom.
- a process for forming an integrated circuit structure comprising the steps of: providing a silicon substrate of a first conductivity type; depositing a first insulating layer over the silicon substrate of the first conductivity type; forming first gate insulating regions in the insulating layer; forming first and second buried silicon regions of a second conductivity type within the silicon substrate of the first conductivity type; depositing a first polycrystalline silicon layer, said first polycrystalline silicon layer contacting said first buried silicon regions; depositing a second insulating layer over the first insulating layer, the first polycrystalline silicon layer and the second buried silicon regions; and depositing a second polycrystalline silicon layer over said second insulating layer and said second buried silicon regions of the second conductivity type, said second buried silicon regions of the second conductivity type being insulated from said second polycrystalline silicon layer.
- an arrangement is provided for programmably connecting the buried silicon regions of the second conductivity type to the polysilicon layers or alternatively programmably isolating the buried silicon regions of the second conductivity type from the polysilicon layers.
- a process for forming a programmable multi-level polysilicon device in an integrated MOS-type circuit structure comprising the steps of: providing a silicon substrate of a first conductivity type; forming buried silicon regions of a second conductivity type within the silicon substrate of the first conductivity type; depositing a first polycrystalline silicon layer over the silicon substrate of the first conductivity type; and depositing a second polycrystalline silicon layer over the silicon substrate of the first conductivity type, wherein a first portion of said buried silicon regions of the second conductivity type contacts the first polycrystalline silicon layer and is isolated from the second polycrystalline silicon layer, and a second portion of said buried silicon regions is insulated from the first and the second polycrystalline silicon layer.
- an integrated circuit structure for MOS-type devices comprising: a silicon substrate of a first conductivity type; gate insulating regions selectively placed over the silicon substrate of the first conductivity type; a polycrystalline silicon layer selectively placed over the silicon substrate of the first conductivity type; first buried silicon regions of a second conductivity type, buried within the silicon substrate of the first conductivity type, placed under the polycrystalline silicon layer and in contact therewith; and second buried silicon regions of the second conductivity type, buried within the silicon substrate of the first conductivity type, placed under the gate insulating regions, under the polycrystalline silicon layer and insulated therefrom.
- a process for forming an integrated circuit structure comprising the steps of: providing a silicon substrate of a first conductivity type; depositing an insulating layer over the silicon substrate of the first conductivity type; forming first gate insulating regions in the insulating layer; forming first and second buried silicon regions of a second conductivity type within the silicon substrate of the first conductivity type; and depositing a polycrystalline silicon layer, wherein said polycrystalline silicon layer contacts said first buried silicon regions and said second buried silicon regions are isolated from said polycrystalline silicon layer.
- an arrangement is provided for programmably connecting the buried silicon regions of the second conductivity type to the polysilicon layer or alternatively programmably isolating the buried silicon regions of the second conductivity type from the ' polysilicon layer.
- a process for forming a programmable polysilicon device in an integrated MOS-type circuit structure comprising the steps of: providing a silicon substrate of a first conductivity type; forming buried silicon regions of a second conductivity type within the silicon substrate of the first conductivity type; and depositing a polycrystalline silicon layer over the silicon substrate of the first conductivity type, wherein a first portion of said buried silicon regions of the second conductivity type contacts polycrystalline silicon layer, and a second portion of said buried silicon regions of the second conductivity type is insulated from the polycrystalline silicon layer.
- a buried contact is a known structure in integrated circuit fabrication technology, firstly developed in the late 1970's with nMOS circuits.
- a buried contact provides a direct connection between polysilicon, normally the gate of a first MOS transistor, and the source/drain region of a second MOS transistor.
- contact openings are masked and etched after gate oxide growth and before deposition and patterning of polysilicon. In this way the polysilicon over the source and/or drain regions can make direct contact to the source and/or drain regions by means of the buried contact openings.
- the present invention discloses an integrated circuit structure and a process for preventing reverse engineering of integrated circuits, by use of a buried contact process that provides the opportunity for a programmable connector/isolator.
- the buried contact process employs at least one polysilicon layer.
- the process according to the present invention will make it possible to selectively interrupt the apparent conduction connections at various transistors sources and drains throughout the circuit.
- Polysilicon has long been used to form the gates for MOS transistors, see for example VLSI technology, S.M. Sze, McGraw-Hill, 1983 p. 99. This requires a CMOS process having one level of deposited polysilicon.
- CMOS processes employing two polysilicon layers, the two layers typically being separated by an oxide layer, make possible the formation of capacitors and electrically eraseable read only memories (EEPROMs), see Hodges and Jackson, Analysis and Design of Digital Integrated Circuits, 2d. ed., McGraw-Hill, 1988, p. 353. See also S.M. Sze, supra, pp. 461-465, for a reference to buried contact devices.
- the concept of the buried contact using two levels of polysilicon is preferably being considered for processes having minimum feature sizes approaching or below 0.2 ⁇ m.
- the buried contact can be placed in correspondence of a first or a second level of polysilicon placed thereover, and in this way be programmed to be a connection or isolation.
- the buried contact when the buried contact is placed under the first level of polysilicon, it acts as a connection.
- the buried contact when the buried contact is placed under the second level of polysilicon, it acts as an isolation.
- a thin gate oxide under the second level polysilicon is provided, in order to insulate the second level polysilicon from the buried contact. Therefore, the circuit designer can "program" the use of the buried contact according to different schemes, by provision of a dual deposition of the thin gate oxide, as later explained in detail.
- a reverse engineer will find it very difficult to determine the presence of a thin gate oxide between the polysilicon and the source and /or drain region of a nMOS device, a pMOS device or a CMOS device.
- Figure 1 is a cross section of a first step of a first embodiment for realizing the circuit structure according to the present invention
- Figure 2 is a cross section of a second step of a first embodiment for realizing the circuit structure according to the present invention
- Figure 3 is a cross section of a third step of a first embodiment for realizing the circuit structure according to the present invention
- Figure 4 is a cross section of a fourth step of a first embodiment for realizing the circuit structure according to the present invention.
- Figure 5 is a cross section of a fifth step of a first embodiment for realizing the circuit structure according to the present invention.
- Figure 6 is a cross section of a sixth step of a first embodiment for realizing the circuit structure according to the present invention.
- > ' Figure 7 is a cross section of a seventh step of a first embodiment for realizing the circuit structure according to the present invention.
- Figure 8 is a cross section of a second step of a second embodiment for realizing the circuit structure according to the present invention;
- Figure 9 is a cross section of a third step of a second embodiment for realizing the circuit structure according to the present invention.
- Figure 10 is a cross section of a fourth step of a second embodiment for realizing the circuit structure according to the present invention; and
- Figure 11 is a cross section of a fifth step of a second embodiment for realizing the circuit structure according to the present invention.
- Figures 1 to 7 show the process steps preferably utilized to realize the circuit structure comprising the camouflaged connector/isolator according to the present invention.
- a standard CMOS process proceeds as follows (see also S. M. Sze, supra, p. 447): 1) P- and N-well formation via ion implantation in the substrate; 2) Deposition of the first insulating layer of silicon dioxide and silicon nitride;
- Figure 1 shows the cross section of the P well portion of a CMOS integrated circuit, processed similarly to the foregoing processes through gate oxide.
- the field insulating regions for example field oxide regions
- the first gate insulating regions for example first gate oxide regions
- Numeral 3 indicates a silicon well region of a first conductivity type, in this embodiment a P well silicon region.
- the field oxide shown here can be for example the conventional LOCOS (LOCal Oxidation of Silicon) oxide. Newer technology like the shallow trench field oxide can also be used. However, these techniques will be not described here in detail, both because they are well-known and because they are not important to an understanding of the present invention.
- Figure 2 shows a subsequent step of the process according to the invention.
- surfaces 4 for the subsequent implantation of buried contact regions are opened by masking and etching.
- Figure 3 shows a subsequent step, in which buried regions 5, 15 of a second conductivity type, in this embodiment highly doped N+ regions, are implanted in the P well 3.
- Figure 4 shows the result after a subsequent step of deposition and patterning of a first polysilicon layer 6.
- the first polysilicon layer 6 contacts some of the N+ regions implanted in the previous step. As shown in Figure 4, the first polysilicon layer 6 contacts the N+ region 5, creating a conductive path between the polysilicon layer 6 and the buried N+ region 5.
- Figure 5 shows a subsequent step, in which a second gate oxide layer 7, usually at 100 A to 200 A, is grown or deposited on top, i.e. covering in part the first polysilicon layer 6, in part the first gate insulator 2, and in part buried N+ regions like the buried N+ region 15.
- a second gate oxide layer 7, usually at 100 A to 200 A is grown or deposited on top, i.e. covering in part the first polysilicon layer 6, in part the first gate insulator 2, and in part buried N+ regions like the buried N+ region 15.
- Figure 6 shows a subsequent step, in which a second polysilicon layer 8 is deposited and patterned by etching.
- the second polysilicon layer 8 is also placed over some of the N+ regions previously implanted, without contacting them.
- the second polysilicon layer 8 is for example placed over the N+ region 15, isolated therefrom by means of the second gate oxide 7.
- Figure 7 shows a cross section after a subsequent source /drain implant, where source/drain N+ regions 9 have been created, preferably by implantation.
- the first polysilicon layer 6 makes contact to the N+ source/drain implant 5 while the second polysilicon layer 8 is isolated from the N+ source/drain implant 15 by means of the second gate oxide 7.
- these two structures are virtually undistinguishable from a top plan view. Even in the cross section, it is very hard to detect the presence of the 100 A thick gate oxide 7.
- This contact could be for example a gate to power supply or an input-gate contact.
- what appears to be a normal buried contact namely polysilicon over an N+ implanted area
- the block occurs because the second polysilicon layer 8 and the second gate oxide 7 are used.
- the structure according to the present invention represents a very good candidate for protecting integrated circuit design from reverse engineering. It will be difficult, if not impossible, for the reverse engineer, viewing structures realized according to the present invention, to see that the buried contact insulation is not a normal buried contact. Moreover, it would be inordinately time consuming and expensive for the reverse engineer to make enough cross sections at possible connecting points within the circuit to determine all the times such buried contact insulation is present.
- the polysilicon layer 8' on the left of Figure 7 shows a typical N-channel transistor formed in the process with both the first and second level of gate oxide. This transistor has been put in the drawing of Figure 7 as a reference.
- a single polysilicon process is used.
- the first step of the process according to the second embodiment is identical to the step shown in Figure 1.
- the second step is shown in Figure 8.
- Figure 8 is similar to Figure 2, the only difference being that no surface 4 is opened on the right side of Figure 8.
- Figure 9 shows a subsequent step of the second embodiment, in which buried regions 5', 15', for example highly doped N+ regions, are implanted in the P well 3.
- This step is identical to the step shown in Figure 3, the only difference between the Figures being that no surface 4 is present on the right side of Figure 9.
- Implantation of region 15' is accomplished without problems, given the reduced thickness of the oxide layer 2.
- Figure 10 shows a subsequent step of the second embodiment, in which a polysilicon layer 6 is deposited and patterned over the N+ regions 5', 15'.
- Figure 11 shows a subsequent step of the second embodiment, where source/ drain regions 9' have been created, similarly to what shown in Figure 7.
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2002316261A AU2002316261A1 (en) | 2001-06-15 | 2002-06-13 | Cmos process |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/882,900 US6774413B2 (en) | 2001-06-15 | 2001-06-15 | Integrated circuit structure with programmable connector/isolator |
US09/882,900 | 2001-06-15 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2002103785A2 true WO2002103785A2 (en) | 2002-12-27 |
WO2002103785A3 WO2002103785A3 (en) | 2003-08-14 |
Family
ID=25381566
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2002/019074 WO2002103785A2 (en) | 2001-06-15 | 2002-06-13 | Cmos process |
Country Status (4)
Country | Link |
---|---|
US (2) | US6774413B2 (en) |
AU (1) | AU2002316261A1 (en) |
TW (1) | TW550666B (en) |
WO (1) | WO2002103785A2 (en) |
Families Citing this family (12)
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US6897535B2 (en) * | 2002-05-14 | 2005-05-24 | Hrl Laboratories, Llc | Integrated circuit with reverse engineering protection |
KR20050011317A (en) * | 2003-07-22 | 2005-01-29 | 삼성전자주식회사 | Semiconductor integrated circuit including reverse engineering protecting means and reverse engineering protecting method thereof |
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US10691860B2 (en) | 2009-02-24 | 2020-06-23 | Rambus Inc. | Secure logic locking and configuration with camouflaged programmable micro netlists |
US8418091B2 (en) | 2009-02-24 | 2013-04-09 | Syphermedia International, Inc. | Method and apparatus for camouflaging a standard cell based integrated circuit |
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AU2002316261A1 (en) | 2003-01-02 |
US6774413B2 (en) | 2004-08-10 |
US20020192878A1 (en) | 2002-12-19 |
US6893916B2 (en) | 2005-05-17 |
WO2002103785A3 (en) | 2003-08-14 |
TW550666B (en) | 2003-09-01 |
US20040012067A1 (en) | 2004-01-22 |
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