WO2003017322A2

WO2003017322A2 - A method and system for measurements in patterned structures

Info

Publication number: WO2003017322A2
Application number: PCT/IL2002/000655
Authority: WO
Inventors: Moshe Finarov
Original assignee: Nova Measuring Instruments Ltd.
Priority date: 2001-08-15
Filing date: 2002-08-08
Publication date: 2003-02-27
Also published as: IL144911A0; WO2003017322A3; IL144911A; AU2002324314A8; AU2002324314A1

Abstract

A method and system are presented for measuring in a patterned structure to thereby enabling to control a process. An image of at least a region of patterned structure formed by light returned from the illuminated region is acquired and analysed to determine sites of the structure to which electrical measurements are to be applied. Electrical measurements to the predetermined sites of the structure are applied and measured data indicative of at least one parameter of the structure is generated for adjusting operating conditions of the process.

Description

A method and system for measurements in patterned structures

FIELD OF THE INVENTION

This invention is generally in the field of measurement techniques aimed at confrolling a certain process of the structure manufacture, and relates to a method and system for measurements in patterned structures. The present invention is particularly useful with conductive layer bearing structures for contact or contactless electrical testing.

BACKGROUND OF THE INVENTION

The manufacture of semiconductor devices typically includes a process of depositing a metal layer onto a semiconductor wafer in order to define interconnects. The quality of this process, as well as that of a process of removing the metal from selected regions (e.g., ponshing) that follows the deposition process, should be controlled.

Fig. 1 illustrates a cross section of a stack-like copper-based wafer structure 10 (utilizing copper interconnects patterned with a known dual Damascene process) prior to the appHcation of a CMP process. The structure 10 includes a substrate 11 with an ILD layer 12 thereon, optional so-called "etch stop" layer 14 (e.g., SiN), ILD layer portions 16 and 18, and a copper layer 20. These stack layers define a dense structure 22, which is composed of the ILD layer portions 18 and copper layer 20, and is surrounded by the ILD layer portions 16. Copper is deposited by one of the known techniques, such as CVD, PVD electroplating or electroless plating. Depending on the deposition process, the uppermost copper layer 20 has certain topography, namely, has the topology within the dense structure 22 repeating that of the underlying pattern. It should be noted that, if electroplating is used, a thin copper seed layer 24 (with the thickness of about 1000-5000A) should be deposited onto the structure prior to the deposition of the layer 20 as a prerequisite for electroplating. The thickness of this layer could be measured by optical- or electrical-based techniques. Additionally, although not specifically shown, a barrier layer (TaN or Ta) is typically provided above the ILD layer portions 16 and 18 to prevent copper migration therein.

Copper CMP is a complex process because of the need to completely remove the barrier layers and copper, without the overpohshing of any feature. This is difficult because current copper deposition processes are not as uniform as the oxide deposition process. To this end, the quahty of the copper deposition process should be controlled.

Contact electrical-based measurement techniques have been developed and are disclosed, for example, in US Patents Nos. 4,868,490; 4,703,252 and 4,204,155, wherein a four-probe measurement device is used. Various techniques for measuring the thickness of a metal layer are disclosed in "An Overview of Thickness Measurement Techniques for Metallic Thin Films", S.C. P. Lim and D. Ridley, Solid State Technology, February 1983, pp. 99-103. A technique of integrated plating- process control utilizing electrical measurements is disclosed in US Patent No. 6,110,345.

SUMMARY OF THE INVENTION

There is a need in the art to improve measurements in patterned structures by providing a novel measurement method and system enabling integrated process control by applying measurements over entire patterned structure, e.g. wafer. The technique of the present invention is particularly useful for controlling a process of deposition and/or CMP of layers, such as copper.

The main idea of the present invention consists of providing a compact system of a desired footprint so as to be installable within a processing machine, in particular at an exit station of this machine. The technique according to the invention combines an optical unit and an electrical measurement unit, in order to enable measurements in predetermined sites of a patterned structure.

More specifically, the present invention deals with the control of process of manufacturing semiconductor devices, and is therefore described below with respect to this appHcation. It should, however, be understood that a patterned structure to be measured by the present invention is any structure progressing on a production line and having a pattern in the form of a surface rehef of its uppermost layer made of a conductive material capable of reflecting incident Hght. The pattern may be created by the topology of the uppermost layer defined by a pattern of underneath layer or layers in the structure.

The need for measurements in predetermined sites is essential when measuring in patterned structures, aimed at preventing damages of specific sites in the structure. Hi the case of semiconductor wafers, the pattern is defined by features (dies), and the measurements are preferably apphed to regions between the dies (scribe lines). Hi order to enable measurements in the predetermined sites, an ahgnment system based on pattern recognition is used. Since the surface of a wafer after the deposition of a metal layer (e.g., copper) thereon is typicahy substantiaUy reflective and is characterized by opticaUy uniform properties, the conventional pattern recognition based systems cannot be used. The pattern recognition technique utilized in such systems is based on different contrasts of different regions of the pattern on the surface of a structure (if the uppermost layer is opaque, or on the underneath layers (if the uppermost layer is transparent).

The technique of the present invention consists of the foUowing. At least a portion of the patterned structure is mu inated, an image of the structure formed by Hght returned therefrom is acquired, and pattern recognition is apphed to this image in order to locate the measurement sites. Then, electrical measurements are apphed to the measurement sites.

There is thus provided, according to one aspect of the present invention, a method for measuring in a patterned structure to thereby enabling to control a process, which has been apphed or is to be apphed to the patterned structure, the method comprising the following steps:

(a) acquiring an image of at least a region of patterned structure formed by Hght returned from the muminated region; (b) analyzing said image to determine sites of the structure to which electrical measurements are to be apphed; (c) applying the electrical measurements to the predetermined sites of the structure and generating measured data indicative of at least one parameter of the structure, to be used for adjusting operating conditions of the process.

The term "patterned structure" signifies a structure formed with at least one layer, wherein at least one the two layers has a certain surface reHef. Such a structure may be a stack of layers of different materials that has undergone one or more phoththography processes. The measured parameter is preferably a thickness of an uppermost layer of the structure. The operating conditions of the process to be controlled may, for example, be the rate of a pohshing head (pohsher), the speed or material flow of the layer deposition.

If the method of the present invention is apphed to the processed structure, the measured data can be used for feed back process control, and if the method is apphed to the structure prior to be processed, the measured data is used for feed forward process control. Hence, the measured data is analyzed, and the operating conditions

(parameters) of a processing tool are adjusted.

Preferably, the electrical measurements are apphed to a plurahty of sites within the entire surface of the patterned structure. To this end, an appropriate relative displacement between the structure and an electrical measuring assembly (probe) is provided.

According to another aspect of the present invention, there is provided a method for processing a patterned structure, the method comprising the steps of: - supplying the patterned structure to a measurement system; - ahgning the patterned structure with an electrical measuring unit of the measurement system;

- determining sites on the patterned structure to which the electrical measurements are to be apphed; - applying the electrical measurements to the patterned structure, and generating measured data indicative of at least one parameter of the structure, to be used for adjusting operating conditions of the processing, wherein said electrical measurements are sequentially apphed to said predetermined sites while a relative displacement is provided between the patterned structure and an electrical measuring assembly;

- processing the patterned structure.

It should be understood that the order of implementation of the above steps is not necessarily the same, in which the steps are Hsted, namely, the processing of the patterned structure may be carried out prior to the other steps. The patterned structure may be a semiconductor wafer. In this case, the predetermined measurement sites are preferably located within the scribe lines of the wafer. When dealing with such a circular patterned structure with a two dimensional arrays of features, such as a wafer, the latter is rotatable about a vertical axis (Z-axis), and either the wafer or the electrical measuring assembly (at least one probe unit) is mounted for displacement along at least one axis of the horizontal plane.

If the dimensions of the probe unit are at least sHghtly smaher than the width of the scribe line, the wafer or probe may be displaced along one horizontal axis only (Y-axis). If the electrical measuring assembly utilizes one such probe unit (e.g., 4- probe unit), the displacement for a distance of about the wafer's radius along the Y- axis is sufficient, provided the relative position between the wafer and the probe unit is such that the probe unit is vertically ahgned with the center and edge regions of the wafer at, respectively, two extreme position of the wafer (or probe unit, as the case may be). If the electrical measuring assembly utilizes two such probe units ahgned in a spaced-apart relationship along the Y-axis, the displacement along this axis for a distance up to (Y+ΔY) is required, wherein ΔY is the distance between the probe units. If at least one dimension of the probe unit is larger than the width of the scribe line, the displacement along two mutually perpendicular horizontal axes is provided: for a distance of about the wafer's radius

According to yet another aspect of the present invention, there is provided a method for measuring in a semiconductor wafer progressing on a production line to thereby enabling to control a process, which has been apphed or is to be apphed to the wafer, the method comprising the following steps:

- ahgning the wafer with a measurement system;

- acquiring an image of at least a region of the, wafer formed by Hght returned from the muminated region;

- analyzing said image to determine sites on the wafer to which electrical measurements are to be apphed;

- applying the electrical measurements to the predetermined sites on the wafer and generating measured data indicative of at least one parameter of the wafer, to be used for adjusting operating conditions of the process, wherein said electrical measurements are apphed while the wafer is rotated about a central axis thereof, and a relative displacement between the wafer and an electrical measuring assembly in a plane perpendicular to the central axis of the wafer is provided. According to yet another aspect of the present invention, there is provided a measurement system to be used for conttolling a process, which has been apphed or is to be apphed to a patterned structure by a processing machine, the system comprising an optical unit, an electrical measuring assembly, and a support stage for supporting the patterned structure during measurements, the system being designed so as to be installable within said processing machine.

According to yet another aspect of the present invention, there is provided a measurement system to be used for conttolling a process, which has been apphed or is to be apphed to a patterned structure, the system comprising:

(a) an optical unit operable to acquire an image of at least a region of the patterned structure formed by Hght returned from the uminated region of the structure, to thereby enable to determine sites to which electrical measurements are to be apphed;

(b) an electrical measuring assembly operable to apply said electrical measurements to the predetermined sites on the patterned structure, and generate measured data indicative of at least one parameter of the structure, to be used for adjusting operating conditions of the process; and

(c) a support stage for supporting the patterned structure during the imaging and electrical measurements.

The support stage has a supporting surface of dimensions of about the dimensions of the patterned structure, and is displaceable along a horizontal axis for a distance of about of the structure's dimension.

According to yet another aspect of the present invention, there is provided a processing machine comprising:

- a processing tool for processing a patterned structure within a processing area of the machine;

- a measurement system accommodated adjacent to the processing tool and defining a measurement area outside the processing area, the measurement system comprising an optical unit operable to acquire an image of at least a region of the structure and define predetermine sites on the patterned structure, an electrical measuring assembly operable to apply electrical measurements to the predetermined sites on the structure, and a support stage to support the patterned structure during the imaging and measurements; and a translation assembly for ttanslating the patterned structure between the processing and measurement areas.

BRIEF DESCRIPTION OF THE DRAWINGS

Hi order to understand the invention and to see how it may be carried out in practice, a preferred embodiment will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which: Fig. 1 is a cross-sectional view of a wafer structure, utilizing copper interconnects patterned with a known dual Damascene process;

Fig. 2 schematically iUustrates a processing machine utilizing an integrated system according to the invention;

Fig. 3 schematically illustrates the main constructional parts of the system according to the invention;

Figs. 4 and 5 schematically illustrate two possible examples, respectively, of the wafer's movement within the system according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

Fig. 1 illustrates the stack-like copper-based wafer structure 10 with copper interconnects patterned with the known dual Damascene process, showing that the uppermost copper layer 20 has the topography within the dense structure 22 repeating that of the underlying pattern. Referring to Fig. 2, there is illustrated a processing machine 30 for processing a semiconductor wafer, for example, for the deposition of a metal layer or for poHshing the deposited metal layer. The machine 30 comprises such main constructional parts as a processing tool 32 associated with an interface assembly 34, which typically includes at least one input and at least one output cassettes 36 and 38. According to the invention, the machine 30 also comprises a measurement system 40. As shown, the system 40 is constructed so as to be instaUable in the interface assembly (exit station). Wafers are transferred within the machine 30 to and from the processing tool 32 by means of an internal robot (not shown). It should be understood that, if the processing tool 32 is the copper deposition tool, wafers are suppHed to the system 40 for measurements before and/or after being processed, thereby enabling feed forward and/or feed back process control. To this end, the output of the system 40 is connected to a control unit (not shown) of the processing tool. Fig. 3 illustrates more specifically the construction of the measurement system 40. The system 40 comprises a support stage 42, which is driven along the Z- axis to thereby support the wafer W in a measurement plane (X-Y-plane) during measurements, and is driven for movement along at least one of the X- and Y-axes, as will be described more specificaUy further below. AdditionaUy, the stage 42 is rotatable about the Z-axis. The stage driving assembly 43 (such as a computer controUed step motor or position servo motor) is operable by a suitable control unit 52, which may be located remotely to the system 40. The system 40 further comprises a measuring head 44 composed of an optical unit 46 and an electrical measuring assembly (probe) 48. The optical unit is designed to enable electrical measurements in predetermined sites of the wafer, namely, to muminate the wafer with incident Hght, detect Hght returned from the muminated region, and form the image of the iUuminated region enabling recognition of the measurement sites, to which the electrical measurements are then apphed. The optical unit 46 includes a Hght source, which is preferably a broad-band or monochromatic Hght source (e.g., LED) for dark field umination, and a suitable detector such as CCD camera.

The image obtained on the CCD camera is contour-like (i.e., showing the edges of different regions of the surface relief), and is processed by the control unit 52 to locate features on the wafer surface to thereby enable ahgnment of the wafer. Ahgnment techniques suitable to be used in the present invention may be of the kind based on scribe lines or asymmetrical features within the die, for example as disclosed in US Patents Nos. 5,682,242 and 5,867,590 assigned to the assignee of the present appHcation. Any detectable feature from the dark field edge image could be used for ahgnment. Such dedicated ahgnment techniques are preferred when measurement sites are to be located within the dies. Electrical measurements within the dies are preferably carried out by non-contact methods, in order to avoid damages of the metal layer under measurements. For contact electrical measurements,measurement sites can also be located within the die area. If the electrical contact is soft enough and may cause local destruction of the top metal layer only, it is acceptable because in the CMP process this layer is removed, so the underlying layers remain non-destructed.

In the preferred embodiment of the invention, measurement sites are located within the scribe lines, and contact 2- or 4-probe electrical measuring assembly is used. The optical measurements aimed at locating the measurement sites are based on detection of the scribe lines intersections.

AdditionaUy, the optical unit 40 comprises an auto-focusing sub-system, for example, the dynamic auto-focusing described in U.S. Patent No. 5,604,344 assigned to the assignee of the present appHcation. This patent is therefore incorporated herein by reference with respect to one specific example of the optical unit suitable to be used in the present invention. According to this technique, at least one pattern (grid) is imaged onto the wafer surface along the main optical path trough an objective lens. The image of the pattern is then combined with an image of the wafer and is reflected towards the image plane along the main optical path. The imaging detector (CCD) detects the reflected image and the pattern, a focus analyser determines the extent of sharpness of the pattern by analysing the output of the image detector.

Since the wafer's surface is substantially reflective and has no contrast pattern thereon, the above auto-focusing technique is very effective. In accordance with the so-obtained signal, the stage is moved along the Z-axis, in order to provide the in- focus position thereof. Since the in-focus position of the stage corresponds to the fixed distance ΔZ between the probe and the wafer's surface, this signal can then be used for moving the stage along the Z-axis on this distance to approach the probe. The Z-translation of the stage could be performed on step-like basis, e.g., a 0.1 μm step movement within the distance ΔZ=30μ could be apphed. Additional means for conttolling the distance between the probe and wafer's surface may be used, for example, based on changing capacitance of the probe-wafer system. Alternatively or additionally, one of the electrodes of the probe may be shghtly shifted (e.g., a 0.1 μm shift) along the Z-axis towards the wafer. In that case, contacting of this electrode with wafer surface will result in closing of an electrical circuit and producing appropriate control signal to the control unit. Then, the probe may be brought into contact by relative translation on that shift distance. Thus, the system provides very delicate contact with the measured surface in order to avoid metal layer damages.

It should be noted that other auto-focusing systems used in CD drivers can be used as well. The auto-focusing assists in the image processing, and enables to control a distance between the measuring head and the wafer's surface. Conttolling of this distance is important to provide soft contact between the electrical probe (e.g., four-probe) and the wafer's surface, when contact measurements are used, or to maintain desired distance for non-contact measurements utilizing any suitable contactless probe, for example, that disclosed in U.S. PatentNo. 5,781,018. It should be understood, that generally the probe, as weh as an objective lens of the optical unit, can be moved along the Z-axis with respect to the stage. According to the preferred embodiment of the invention, the probe and optical unit are stationary mounted and the stage is movable.

Also provided in the system 40 is a pre-alignment sensing unit(not shown), which is of any suitable design (e.g., an optical system) capable of providing irrformation about the wafer's orientation based on a notch or flat mark formed in the wafer. Such an optical system may be similar to that disclosed in U.S. Patent 6,038,029 assigned to the assignee of the present appHcation.

Reference is now made to Figs. 4 and 5 illustrating two examples, respectively, of the wafer's movement within the system 40 during measurements, ha both examples, the geometry of the stage and movements are such as to provide measurements within the entire surface of the wafer with the minimal footprint of the system 40. In both examples, the stage is mounted for rotation in the X-Y-plane, sHding movement along the Z-axis, and sHding movement along the Y-axis (generally, along the length of the stage) for a length L equal to or shghtiy higher than the radius r of the wafer. The width h of the stage with a wafer on it is equal to or shghtiy higher than the wafer's diameter. The probe 48 is stationary mounted so as to be ahgned (along the Z-axis) either with the center of the wafer at the two extreme locations of the stage along the Y-axis. In the present examples, a 4-probe assembly is used. According to the example of Fig. 4, the angular orientation of the wafer with respect to the probe 48 is not critical. For example, the electrical measurements are performed on the scribe lines, and the probe's dimensions are less than the width of the scribe line (e.g., about 50μm) at any wafer's orientation. Consequently, the stage movement along the X-axis is not needed. As also shown in Fig. 4, an additional probe 48A can be provided being spaced from the probe 48 a distance AL along the Y-axis. Hi this case, the length of the stage movement along the Y-axis is equal to (L+A ). Thus, by rotating the wafer about the Z-axis and step-by-step movement of the wafer along the Y-axis up to the distance L (or (L+AL), as the case may be), the entire surface of the wafer is measured.

In the example of Fig. 5, one of the probe's dimensions is greater than the width of the scribe line SL, for example the length of the 4-probe assembly is higher than the width of the scribe line. Therefore, the orientation of the scribe lines (grid like pattern) with respect to the probe 48 should be such as to ensure that this longer dimension of the probe assembly is arranged along the scribe line. In this configuration, measurements are carried out along two mutually pe endicular scribe lines in the vicinity of the wafer's center. These measurements are sufficient when dealing with symmetric structures resulting from the deposition process apphed to a rotating structure. Hence, the stage is also mounted for sHding movement along the X-axis. A minimal distance AX equal to at least the die maximal dimension is needed to allow diametric scan over the wafer, where the measurement site may be located at any coordinate along the die dimension. Alternatively, the probe head may be mounted for movement along the X-axis within the range __X equal to at least the die maximal dimension. The angular orientation of the wafer is controUed by the optical system (not shown), which observes the edge of the wafer to detect the position of notch (flat) by utilizing any suitable detector, e.g., an opto-couple detector, CCD camera, etc. It should be noted that the angular orientation of the wafer may be performed on an additional support assembly prior to loading the wafer onto the stage. The system of the present invention is capable of measuring at least one film (layer) characteristic, e.g., thickness, electrical conductivity (resistively), reflectivity (grain structure of layer, chemical composition). The layer reflectivity could be measured by the optical unit 46 using additional spectroscopic channel either included in the system 46 or not combined. Such a combined spectroscopic and imaging system may be the NovaScan, Integrated Thickness Monitoring System, commercially available from the assignee of the present appHcation, and is preferred when integrated within a pohsher. The electrical thickness measurements by means of 4-probe or the non-contact probe of the above-indicated U.S. Patent No. 5,781,018. When one or more additional optical channel combined with the electrical channel are implemented, the system aUows more comprehensive process control, e.g., of the CMP process. For instance, such informative parameters as post- CMP erosion, (hshing and residues may be detected and measured using the technique disclosed in WO 00/54325 assigned to the assignee of the present apphcation.Electrical thickness measurements are performed indirectly by sheet resistance measurements, which, for the 4-probe assembly, consist of the foUowing: An electrical current of the known value / is passed between the two of the four probes, and voltage V between the two other probes is measured. Various correction factors are used to relate the sheet resistance to the ratio V/ϊ, depending inter alia on the probe configuration. The layer thickness t and sheet resistance R_s are related by wherein p is the specific resistivity of the layer material. Hence, by knowing the value of p, e.g., through caHbration measurements, the layer thickness can be determined. Such a technique is weU known per se and therefore need not be more specifically described. The present invention thus presents an integrated measuring tool that may be used with a layer deposition clusters (electrical plating, PVD, CVD, etc.). The system of the present invention additionally equipped with the optical (spectroscopic) channel and integrated within the deposition tool could provide optical thickness measurements of the barrier and seed layers. The measured parameters of the deposited metal layer may be suppHed to the CMP (poHsher) tool for initial thickness estimation.

Those skilled in the art wiU readily appreciate that various modifications and changes can be apphed to the embodiments of the invention as hereinbefore exemplified without departing from its scope defined in and by the appended claims.

Claims

CLAIMS:

1. A method for measuring in a patterned structure to thereby enabling to control a process, which has been apphed or is to be apphed to the patterned structure, the method comprising the foUowing steps: (i) acquiring an image of at least a region of patterned structure formed by

Hght returned from the uminated region; (ii) analyzing said image to determine sites of the structure to which electrical measurements are to be apphed; (Hi) applying the electrical measurements to the predetermined sites of the structure and generating measured data indicative of at least one parameter of the structure, to be used for adjusting operating conditions of the process.

2. The method according to Claim 1, wherein steps (i) to (in) are apphed to the processed structure, the measured data being used for feed back process control.

3. The method according to Claim 1, wherein steps (i) to (in) are apphed to the patterned structure prior to be processed, the measured data being used for feed forward process control.

4. The method according to Claim 1, wherein the electrical measurements are apphed to a plurality of sites within the entire surface of the patterned structure, the method also comprising the step of providing appropriate relative displacement between the structure and an electrical measuring assembly during the electrical measurements.

5. The method according to Claim 1, wherein said process to be controUed is CMP.

6. The method according to Claim 1, wherein said process to be controUed is a layer deposition process.

7. A method for processing a patterned structure, the method comprising the steps of:

- supplying the patterned structure to a measurement system; - ahgning the patterned structure with an electrical measuring unit of the measurement system;

- determirring sites on the patterned structure to which the electrical measurements are to be apphed; - applying the electrical measurements to the patterned structure, and generating measured data indicative of at least one parameter of the structure, to be used for adjusting operating conditions of the processing, wherein said electrical measurements are sequentially apphed to said predetermined sites while a relative displacement is provided between the patterned structure and an electrical measuring assembly;

- processing the patterned structure.

8. The method according to Claim 7, wherein the measured data is used for feed forward process control.

9. The method according to Claim 7, wherein the processing of the patterned structure is carried out prior to performing the other steps, the measured data being used for feed back process control.

10. The method according to Claim 7, wherein said patterned structure has a circular geometry and the pattern is a two dimensional array of features, and said relative displacement between the patterned structure and an electrical measuring assembly including rotating the structure about a central axis thereof and a displacement along at least one axis of a plane perpendicular to the centtal axis of the structure up to a distance equal to or shghtiy higher than the structure's radius.

11. The method according to Claim 10, wherein said relative displacement also includes an additional displacement within said plane along an additional peφendicular axis.

12. The method according to Claim 10, for processing a semiconductor wafer, the predetermined measurement sites being located within the scribe lines of the wafer.

13. The method according to Claim 11, for processing a semiconductor wafer, the predetermined measurement sites being located within the scribe lines of the wafer, the displacement along said additional axis being up to a distance equal to or shghtiy higher than the width of the scribe line.

14. A method for measuring in a semiconductor wafer progressing on a production line to thereby enabling to control a process, which has been apphed or is to be apphed to the wafer, the method comprising the foUowing steps:

- ahgning the wafer with a measurement system;

- acquiring an image of at least a region of the wafer formed by Hght returned from the muminated region;

- applying the electrical measurements to the predetermined sites on the wafer and generating measured data indicative of at least one parameter of the wafer, to be used for adjusting operating conditions of the process, wherein said electrical measurements are apphed while the wafer is rotated about a central axis thereof, and a relative displacement between the wafer and an electrical measuring assembly in a plane perpendicular to the central axis of the wafer is provided.

15. A measurement system to be used for conttolling a process, which has been apphed or is to be apphed to a patterned structure by a processing machine, the system comprising an optical unit, an electrical measuring assembly, and a support stage for supporting the patterned structure during measurements, the system being designed so as to be installable within said processing machine.

16. The system according to Claim 15, wherein said optical unit capable of acquiring an image of at least a region of patterned structure formed by Hght returned from the muminated region.

17. The system according to Claim 16, wherein said electrical measurement assembly comprises a probe unit capable of carrying out contact or contacless electrical measurements.

18. The system according to Claim 16, wherein said support stage has dimensions equal to or shghtiy higher than dimensions of the patterned structure, is rotatable about a central axis of the structure, and is displaceable relative to the electrical measuring assembly along an axis in a plane perpendicular to said central axis up to a distance of about the structure's dimension.

19. The system according to Claim 18, for conttolling the processing of a 5 semiconductor wafer by applying the electrical measurements to predetermined sites on the wafer located within scribe lines, the probe unit having dimensions equal to or smaller than the width of the scribe line.

20. The system according to Claim 187, for conttolling the processing of a semiconductor wafer by applying the electrical measurements to predetermined sites

10 on the wafer located within scribe lines, the probe unit having a dimension higher than the width of the scribe line, the support stage being displaceable within said plane along an additional peφendicular axis.

21. A measurement system to be used for conttolling a process, which has been apphed or is to be apphed to a patterned structure, the system comprising:

15 (a) an optical unit operable to acquire an image of at least a region of the patterned structure formed by Hght returned from the muminated region of the structure, to thereby enable to determine sites to which electrical measurements are to be apphed;

(b) an electrical measuring assembly operable to apply said electrical 20 measurements to the predetermined sites on the patterned structure, and generate measured data indicative of at least one parameter of the structure, to be used for adjusting operating conditions of the process; and

25 22. The system according to Claim 210, wherein said electrical measuring unit comprises a probe unit capable of carrying out contact or contactless measurements.

23. The system according to Claim 221, wherein said support stage with a wafer thereon has dimensions equal to or shghtiy higher than a diameter of the patterned structure, is rotatable about a central axis of the structure, and is displaceable relative to the electrical measuring assembly along an axis in a plane perpendicular to said central axis up to a distance of about the structure's radius.

24. The system according to Claim 22, wherein said electrical measuring unit comprises an additional probe unit capable of carrying out contact or contactless

5 measurements, the two probe unit being ahgned in a spaced-apart relation along an axis peφendicular to a central axis of the structure.

25. The system according to Claim 24, wherein the support stage has dimensions equal to or shghtiy higher than a diameter of the patterned structure, is rotatable about the centtal axis of the structure, and is displaceable relative to the

10 probe units along a Y-axis parallel to said axis of ahgnment of the probe units up to a distance equal to or shghtiy higher than (r+ΔY), wherein r is the radius of the structure and ΔY is the distance between the probe units.

26. The system according to Claim 23, wherein the probe unit has dimensions equal to or shghtiy smaller than the dimension of the predetermined site.

15 27. The system according to Claim 24, wherein each of the probe units has dimensions equal to or shghtiy smaller than the dimension of the predetermined site.

28. The system according to Claim 232, wherein the probe unit has a dimension higher than the dimension of the predetermined site, the support stage being displaceable wilhin said plane along an additional peφendicular axis.

20 29. The system according to Claim 24, wherein the probe unit has a dimension higher than the dimension of the predetermined site and being displaceable within said plane along an additional peφendicular axis.

30. The system according to Claim 28, for conttolling the processing of a semiconductor wafer by applying the electrical measurements to predetermined sites

25 on the wafer located within scribe lines, said additional displacement being up to a distance equal to at least the maximal die dimension in the wafer, thereby allowing diametric scan of the wafer by the probe unit.

31. The system according to Claim 29, for conttolling the processing of a semiconductor wafer by applying the electrical measurements to predetermined sites

30 on the wafer located within scribe lines, said additional displacement being up to a distance equal to at least the maximal die dimension in the wafer, thereby allowing diametric scan of the wafer by the probe units.

32. A processing machine comprising:

- a measurement system accommodated adjacent to the processing tool and defining a measurement area outside the processing area, the measurement system comprising an optical unit operable to acquire an image of at least a region of the structure and define predetermine sites on the patterned structure, an electrical measuring assembly operable to apply electrical measurements to the predetermined sites on the structure, and a support stage to support the patterned structure during the imaging and measurements; and

- a translation assembly for ttanslating the patterned structure between the processing and measurement areas.

33. The machine according to Claim 32, wherein said processing tool is a poHsher operable to perform chemical mechanical planarization of the surface of the patterned structure.

34. The machine according to Claim 32, wherein said processing tool is capable of carrying out a layer deposition process.

35. The machine according to Claim 34, wherein said processing tool is capable of carrying out electrical plating process.