WO2003017330A3 - Forming a semiconductor structure using a combination of planarizing methods and electropolishing - Google Patents

Forming a semiconductor structure using a combination of planarizing methods and electropolishing Download PDF

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Publication number
WO2003017330A3
WO2003017330A3 PCT/US2002/026167 US0226167W WO03017330A3 WO 2003017330 A3 WO2003017330 A3 WO 2003017330A3 US 0226167 W US0226167 W US 0226167W WO 03017330 A3 WO03017330 A3 WO 03017330A3
Authority
WO
WIPO (PCT)
Prior art keywords
electropolishing
semiconductor structure
combination
forming
conductive layer
Prior art date
Application number
PCT/US2002/026167
Other languages
French (fr)
Other versions
WO2003017330A2 (en
Inventor
Xiang Yu Yao
Ru Kao Chang
Peihaur Yih
Hui Wang
Original Assignee
Acm Res Inc
Xiang Yu Yao
Ru Kao Chang
Peihaur Yih
Hui Wang
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Acm Res Inc, Xiang Yu Yao, Ru Kao Chang, Peihaur Yih, Hui Wang filed Critical Acm Res Inc
Priority to AU2002336360A priority Critical patent/AU2002336360A1/en
Priority to EP02773205A priority patent/EP1423868A2/en
Priority to CA002456225A priority patent/CA2456225A1/en
Priority to KR1020047002336A priority patent/KR100899060B1/en
Priority to JP2003522140A priority patent/JP2005500687A/en
Priority to US10/486,982 priority patent/US20040253809A1/en
Publication of WO2003017330A2 publication Critical patent/WO2003017330A2/en
Publication of WO2003017330A3 publication Critical patent/WO2003017330A3/en

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
    • C25F3/00—Electrolytic etching or polishing
    • C25F3/16—Polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23H—WORKING OF METAL BY THE ACTION OF A HIGH CONCENTRATION OF ELECTRIC CURRENT ON A WORKPIECE USING AN ELECTRODE WHICH TAKES THE PLACE OF A TOOL; SUCH WORKING COMBINED WITH OTHER FORMS OF WORKING OF METAL
    • B23H5/00—Combined machining
    • B23H5/06—Electrochemical machining combined with mechanical working, e.g. grinding or honing
    • B23H5/08—Electrolytic grinding
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Mechanical Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method for planarizing and electropolishing a conductive layer on a semiconductor structure includes forming a dielectric layer with recessed areas and non-recessed areas on the semiconductor wafer. A conductive layer is formed over the dielectric layer to cover the recessed areas and non-recessed areas. The surface of the conductive layer is then planarized to reduce variations in the topology of the surface. The planarized conductive layer is then electropolished to expose the non-recessed area.
PCT/US2002/026167 2001-08-17 2002-08-15 Forming a semiconductor structure using a combination of planarizing methods and electropolishing WO2003017330A2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
AU2002336360A AU2002336360A1 (en) 2001-08-17 2002-08-15 Forming a semiconductor structure using a combination of planarizing methods and electropolishing
EP02773205A EP1423868A2 (en) 2001-08-17 2002-08-15 Forming a semiconductor structure using a combination of planarizing methods and electropolishing
CA002456225A CA2456225A1 (en) 2001-08-17 2002-08-15 Forming a semiconductor structure using a combination of planarizing methods and electropolishing
KR1020047002336A KR100899060B1 (en) 2001-08-17 2002-08-15 Forming a semiconductor structure using a combination of planarizing methods and electropolishing
JP2003522140A JP2005500687A (en) 2001-08-17 2002-08-15 Formation of semiconductor structures using a combination of planarization and electropolishing.
US10/486,982 US20040253809A1 (en) 2001-08-18 2002-08-15 Forming a semiconductor structure using a combination of planarizing methods and electropolishing

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US31308601P 2001-08-17 2001-08-17
US60/313,086 2001-08-17

Publications (2)

Publication Number Publication Date
WO2003017330A2 WO2003017330A2 (en) 2003-02-27
WO2003017330A3 true WO2003017330A3 (en) 2003-07-24

Family

ID=23214320

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/026167 WO2003017330A2 (en) 2001-08-17 2002-08-15 Forming a semiconductor structure using a combination of planarizing methods and electropolishing

Country Status (8)

Country Link
EP (1) EP1423868A2 (en)
JP (1) JP2005500687A (en)
KR (1) KR100899060B1 (en)
CN (1) CN100419963C (en)
AU (1) AU2002336360A1 (en)
CA (1) CA2456225A1 (en)
TW (1) TW569330B (en)
WO (1) WO2003017330A2 (en)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6939796B2 (en) * 2003-03-14 2005-09-06 Lam Research Corporation System, method and apparatus for improved global dual-damascene planarization
US6821899B2 (en) * 2003-03-14 2004-11-23 Lam Research Corporation System, method and apparatus for improved local dual-damascene planarization
US7078344B2 (en) * 2003-03-14 2006-07-18 Lam Research Corporation Stress free etch processing in combination with a dynamic liquid meniscus
US20080121529A1 (en) * 2004-12-22 2008-05-29 Yasushi Tohma Flattening Method and Flattening Apparatus
WO2010020092A1 (en) 2008-08-20 2010-02-25 Acm Research (Shanghai) Inc. Barrier layer removal method and apparatus
CN101882595B (en) * 2009-05-08 2014-07-09 盛美半导体设备（上海）有限公司 Method and device for removing barrier layer
CN103692293B (en) * 2012-09-27 2018-01-16 盛美半导体设备（上海）有限公司 non-stress polishing device and polishing method
US8828875B1 (en) 2013-03-08 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for improving CMP planarity
CN104097118A (en) * 2013-04-02 2014-10-15 盛美半导体设备（上海）有限公司 Stress-free polishing integration device
CN105870051B (en) * 2015-01-20 2019-01-11 中芯国际集成电路制造(上海)有限公司 The production method of semiconductor structure
WO2016127424A1 (en) * 2015-02-15 2016-08-18 Acm Research (Shanghai) Inc. Method for optimizing metal planarization process
US10074721B2 (en) * 2016-09-22 2018-09-11 Infineon Technologies Ag Method of fabricating a semiconductor wafer that includes producing a planarised surface having both a mesa surface and an insulating layer surface
CN106672892A (en) * 2016-12-21 2017-05-17 中国电子科技集团公司第五十五研究所 Method for reducing depressed deformation of sacrificial layer in three-dimensional stacking in chemical mechanical polishing
CN108231599B (en) * 2016-12-22 2021-10-08 联华电子股份有限公司 Method for improving evenness of wafer surface
WO2020138976A1 (en) * 2018-12-26 2020-07-02 한양대학교에리카산학협력단 Method for manufacturing semiconductor device
KR102499041B1 (en) 2019-01-10 2023-02-14 삼성전자주식회사 Method of forming semiconductor device
CN111312595A (en) * 2020-03-03 2020-06-19 合肥晶合集成电路有限公司 Manufacturing method of metal interconnection layer
CN113173552B (en) * 2021-04-09 2023-06-23 深圳清华大学研究院 Large-scale super-slip element with conductivity, processing technology thereof and large-scale super-slip system

Citations (4)

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Publication number Priority date Publication date Assignee Title
US6149830A (en) * 1998-09-17 2000-11-21 Siemens Aktiengesellschaft Composition and method for reducing dishing in patterned metal during CMP process
JP2001044195A (en) * 1999-07-28 2001-02-16 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
US6232231B1 (en) * 1998-08-31 2001-05-15 Cypress Semiconductor Corporation Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect
US6315883B1 (en) * 1998-10-26 2001-11-13 Novellus Systems, Inc. Electroplanarization of large and small damascene features using diffusion barriers and electropolishing

Family Cites Families (5)

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JP3557868B2 (en) * 1997-01-14 2004-08-25 セイコーエプソン株式会社 Surface treatment method for decorative articles, decorative articles and electronic equipment
US6121152A (en) * 1998-06-11 2000-09-19 Integrated Process Equipment Corporation Method and apparatus for planarization of metallized semiconductor wafers using a bipolar electrode assembly
US6056864A (en) 1998-10-13 2000-05-02 Advanced Micro Devices, Inc. Electropolishing copper film to enhance CMP throughput
KR100283108B1 (en) * 1998-12-28 2001-04-02 김영환 Copper wiring formation method of semiconductor device
KR100297736B1 (en) * 1999-08-13 2001-11-01 윤종용 Trench isolation method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6232231B1 (en) * 1998-08-31 2001-05-15 Cypress Semiconductor Corporation Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect
US6149830A (en) * 1998-09-17 2000-11-21 Siemens Aktiengesellschaft Composition and method for reducing dishing in patterned metal during CMP process
US6315883B1 (en) * 1998-10-26 2001-11-13 Novellus Systems, Inc. Electroplanarization of large and small damascene features using diffusion barriers and electropolishing
JP2001044195A (en) * 1999-07-28 2001-02-16 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
US6424042B1 (en) * 1999-07-28 2002-07-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
CN1543668A (en) 2004-11-03
TW569330B (en) 2004-01-01
WO2003017330A2 (en) 2003-02-27
AU2002336360A1 (en) 2003-03-03
KR20040030147A (en) 2004-04-08
EP1423868A2 (en) 2004-06-02
KR100899060B1 (en) 2009-05-25
CA2456225A1 (en) 2003-02-27
CN100419963C (en) 2008-09-17
JP2005500687A (en) 2005-01-06

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