WO2003017427A3 - Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication - Google Patents

Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication Download PDF

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Publication number
WO2003017427A3
WO2003017427A3 PCT/US2002/023748 US0223748W WO03017427A3 WO 2003017427 A3 WO2003017427 A3 WO 2003017427A3 US 0223748 W US0223748 W US 0223748W WO 03017427 A3 WO03017427 A3 WO 03017427A3
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WO
WIPO (PCT)
Prior art keywords
programmable
field
fabrication
stacked
nonvolatile memory
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Application number
PCT/US2002/023748
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French (fr)
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WO2003017427A2 (en
Inventor
Mark G Johnson
Original Assignee
Matrix Semiconductor Inc
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Publication date
Application filed by Matrix Semiconductor Inc filed Critical Matrix Semiconductor Inc
Priority to AU2002330921A priority Critical patent/AU2002330921A1/en
Publication of WO2003017427A2 publication Critical patent/WO2003017427A2/en
Publication of WO2003017427A3 publication Critical patent/WO2003017427A3/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links

Abstract

A three-dimensional, field-programmable, non-volatile memory includes multiple layers of first and second crossing conductors(10,11). Pillars(12) are self-aligned at the intersection of adjacent first and second crossing conductors, and each pillar includes at least an anti-fuse layer(16). The pillars form memory cells with the adjacent conductors, and each memory cell includes first and second diode components separated by the anti-fuse layer. The diode components form a diode only after the anti-fuse layer is disrupted.
PCT/US2002/023748 2001-08-13 2002-07-26 Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication WO2003017427A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002330921A AU2002330921A1 (en) 2001-08-13 2002-07-26 Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/928,536 2001-08-13
US09/928,536 US6525953B1 (en) 2001-08-13 2001-08-13 Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication

Publications (2)

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WO2003017427A2 WO2003017427A2 (en) 2003-02-27
WO2003017427A3 true WO2003017427A3 (en) 2003-08-21

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PCT/US2002/023748 WO2003017427A2 (en) 2001-08-13 2002-07-26 Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication

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US (4) US6525953B1 (en)
AU (1) AU2002330921A1 (en)
MY (1) MY122896A (en)
TW (1) TWI268604B (en)
WO (1) WO2003017427A2 (en)

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