WO2003023848A2 - Apparatus and method of surface treatment for electrolytic and electroless plating of metals in integrated circuit manufacturing - Google Patents
Apparatus and method of surface treatment for electrolytic and electroless plating of metals in integrated circuit manufacturing Download PDFInfo
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- WO2003023848A2 WO2003023848A2 PCT/US2002/022314 US0222314W WO03023848A2 WO 2003023848 A2 WO2003023848 A2 WO 2003023848A2 US 0222314 W US0222314 W US 0222314W WO 03023848 A2 WO03023848 A2 WO 03023848A2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1619—Apparatus for electroless plating
- C23C18/1632—Features specific for the apparatus, e.g. layout of cells and of its equipment, multiple cells
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D17/00—Constructional parts, or assemblies thereof, of cells for electrolytic coating
- C25D17/001—Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/34—Pretreatment of metallic surfaces to be electroplated
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76862—Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
Definitions
- the present invention relates to integrated circuit (IC) manufacture and more particularly to an apparatus and method of substrate surface treatment for electrolytic or electroless plating of metals or other conductive materials.
- a damascene technique involves forming a via and an overlying trench in a dielectric to an underlying circuit device, such as a transistor or an interconnection line.
- the via and trench are then lined with a barrier layer of a refractory material.
- the barrier layer typically serves to inhibit the diffusion of the interconnection material that will subsequently be formed in the via into the dielectric.
- a suitable seed material is deposited on the wall or walls and base of the via.
- Suitable seed materials for the deposition of copper interconnection material include copper and nickel.
- the wafer may be cooled down in an atmosphere containing argon or nitrogen.
- interconnection material such as copper, is deposited in a sufficient amount to fill the via and trench using, for example, an electroplating process.
- a chemical-mechanical polishing or etching process is used to remove any interconnection material present outside the trench. If a trench and an underlying via are filled simultaneously with the interconnection metal, the process is known as a dual damascene process.
- FIGS, la is a cross-sectional view of an interconnect structure for a semiconductor device showing a formation of two trenches for laying wiring lines and in which one of the trenches has an underlying via opening for an interconnection to a lower metal layer, which is separated from the trench formation by an inter-layer dielectric (ILD) layer.
- FIG. lb is a cross-sectional view of the structure of FIG. la in which a barrier layer is formed over the ILD and in the trench openings and via opening.
- FIG. lc is a cross-sectional view of the structure of FIG. lb in which a metal seed layer, such as a Cu seed layer, is formed over the barrier layer formed over the ILD and in the trench openings and via opening.
- FIG. Id is a cross-sectional view of the structure of FIG. lc following an in-situ surface treatment of the structure in a barrier-seed tool deposition chamber to passivate a metal seed layer surface.
- FIG. le is a cross-sectional view of the structure of FIG. Id following a seed anneal of the structure in an anneal chamber attached to an electroplating tool to remove any contaminants formed over the metal seed layer.
- FIG. If is a cross-sectional view of the structure of FIG. le following electroless or electrolytic deposition of a metal or other conductive material over the annealed metal seed layer.
- FIG. lg is a cross-sectional view of the structure of FIG. If in which the excess metal, e.g. copper, electrolessly or electrolytically deposited above the ILD is removed.
- the excess metal e.g. copper
- FIG. 2a is a process for treating a patterned and/or bare substrate surface following deposition of a metal seed layer according to an embodiment of this invention.
- FIG. 2b is a process for performing integrated seed anneal and plating of a patterned and/or bare substrate surface following treatment process shown in FIG. 2a according to an embodiment of this invention.
- FIG. 3a schematically illustrates an exemplary embodiment of an apparatus for in situ substrate surface treatment according to this invention.
- FIG. 3b schematically illustrates an exemplary embodiment of an apparatus for integrated seed anneal / electrolytic or electroless plating of metals or other conductive materials according to this invention.
- An apparatus and method to perform substrate surface treatment for electrolytic or electroless plating of metals or other conductive materials are described.
- the apparatus and method of this invention have significant advantages over current Cu-based metallization processes, including for example sharply reducing or eliminating post- electrolytic or electroless plating defects, improving wetting and promoting void-free electrolytic or electroless plating gap-fill in high aspect ratio vias and trenches, reducing IC processing cost by performing in-situ treatment of metal seed layer, and enhancing reliability.
- FIGS, la through lg and by FIGS. 2a and 2b are schematic cross-section representations of the semiconductor structure at various phase during the manufacture process embodiments shown in FIGS. 2a and 2b.
- FIG. 2a which is associated with FIGS.
- FIG. 2b which is associated with FIGS le-lg, shows an embodiment of a process of this invention for performing integrated seed anneal and plating of a patterned and/or bare substrate surface following treatment process shown in FIG. 2a.
- FIG. la shows an exemplary semiconductor substrate structure 10 having a metal layer 11 on a silicon substrate 20 and covered by an ILD layer 12.
- Metal layer 11 is representative of one of the metal layers in a multiple metal level semiconductor device.
- Layer 12 is typical of an ILD layer that is used to separate the different metal layers.
- ILD layer 12, which may be made of a material such as borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), borosilicate glass (BSG), silicon dioxide, fluorine doped oxide, low k dielectric material, or spin-on dielectric material may be formed over the structure 10 by chemical vapor deposition (CVD), physical vapor deposition (PVD) or other suitable means.
- CVD chemical vapor deposition
- PVD physical vapor deposition
- structure 10 is only a portion of many structures present on a semiconductor wafer. Trenches 14 and 15 are formed in structure 10 along with the formation of via opening 13 under trench 14 for interconnection to the lower metal layer 11. Structure 10 or similar can be fabricated utilizing single or dual damascene processes known in the art.
- process begins by providing a substrate structure 10 into a semiconductor device processing first tool 310 (shown in FIG. 3a), such as a copper-barrier seed deposition tool 310 (block 210 in FIG. 2a) to form a barrier layer on the substrate structure.
- a semiconductor device processing first tool 310 shown in FIG. 3a
- the copper-barrier seed deposition tool generally includes several chambers where substrate processing is performed without breaking vacuum.
- the surface of substrate structure 10 may be bare, for example substrate structure 10 may include only substrate 20.
- substrate structure 10 may include a substrate 20 having a metal layer 11 and / or at least a trench 14, 15 and a via 13 patterned on an ILD layer 12.
- Other configurations or arrangements for substrate structure 10 are within the scope of this invention.
- a barrier layer 16 is formed over the ILD layer 12 and in the trench openings 14, 15 and via opening 13 so that the barrier layer 16 overlies the ILD layer 12 and lines the inside of the trenches 14, 15 and via 13 (block 220 of FIG. 2a).
- Barrier layers, such as barrier layer 16 are typically used with metal interconnect material to optimize performance of the interconnects and to prevent diffusion of the metal interconnect material into the substrate.
- Barrier layer 16 may be formed of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten-tantalum (WTa), tantalum silicon nitride, or other ternary compounds.
- the barrier layer 16 is formed using known film deposition techniques, such as CVD, PVD, electrolytic plating or electroless plating. If the barrier layer 16 is TiN, then CVD or PVD can be used for the deposition of TiN. If the barrier layer 16 is Ta, then PVD can be used for the conformal deposition of Ta.
- barrier layer 16 is deposited to a thickness in the range of approximately 150-300 angstroms (A), however, other barrier thickness may be practiced within the scope of this invention. In an embodiment, barrier layer 16 is deposited to a thickness of about 200 A.
- a metal seed layer 17, such as a copper-seed layer 17 over the barrier layer 16 that overlies the ILD layer 12 and lines the inside of the trenches 14, 15 and via 13 (block 230 of FIG. 2a).
- Metal seed layer 17 can be deposited or formed using metals, metal alloys, metal compounds, multiple layers of metal stack or any substrates where a metal that is to be used to form the interconnects in the trench and the via can nucleate and grow.
- the metal seed layer 17 is made of a metal or metal alloy and may include, but is not limited to, copper, copper alloy, nickel, silver, gold, and cobalt.
- the metal seed layer 17 is deposited/formed while the substrate structure 10 is still in the first semiconductor device processing tool 310, e.g., copper barrier-seed deposition tool 310 (shown in FIG. 3a), utilizing a directional deposition technique.
- Directional deposition techniques include collimated sputtering, plasma enhanced chemical vapor deposition, and ionized physical vapor deposition with or without bias voltage.
- seed layer 17 is deposited to a thickness in the range of approximately 1000-3000 angstroms (A). In an embodiment, seed layer 17 is deposited to a thickness of about 2000 A.
- the process continues by physically or chemically treating the metal seed layer prior to electrolytic/electroless plating of conductive material on substrate.
- the physical and/or chemical treatment of metal seed layer 17 may be done in-situ or ex-situ using a liquid or a chemically active or inert gas prior to electrolytic/electroless plating of the conductive material.
- the metal seed layer surface 17 may be exposed to gases, such as argon (Ar), Helium (He), Oxygen (0 2 ), Hydrogen (H ), H 2 and He, H and nitrogen (N 2 ), H 2 and Ar, etc. at a range of temperatures and concentrations known in the art.
- the metal seed layer surface 17 is exposed to liquid media such as acids, bases, solvents, and di-ionized water prior to electrolytic/ electroless plating of the conductive material in trenches 14, 15 and via 13 of substrate structure 10.
- treatment of metal seed layer 17 is done by performing in situ seed surface passivation (or metal seed layer treatment) of the substrate structure 10 having the metal seed layer 17 and the barrier layer 16 thereon to form a seed passivation layer 18, for example a metal oxide layer 18, on the metal seed layer 17 (block 240 in FIG. 2a).
- the in situ seed surface passivation (or seed treatment) is performed while the substrate structure 10 is still within a chamber of the metal barrier-seed deposition tool 310 (shown in FIG. 3a).
- the chamber of the first substrate processing tool e.g. copper-barrier seed deposition tool, having substrate structure 10 therewith is filled with a gas for a first specified period of time, ti.
- the gas environment may include, but is not limited to, inert gases, hydrogen gas, fluorine containing gas, forming gas, oxygen gas, nitrogen gas, etc.
- the substrate structure 10 having the metal seed layer 17 and the barrier layer 16 thereon is then cooled in the gas (e.g. oxygen) environment in the sub-atmospheric chamber at a specified temperature, T, for a second specified period of time, t 2 , to form a passivation layer 18, e.g.
- the sub-atmospheric chamber of the copper-barrier seed deposition tool is filled with pure oxygen gas flowing at a pressure of up to about 2 torr for a first specified period of time ti of about 15-25 seconds, and preferably about 20 seconds.
- the substrate structure 10 having the metal seed layer 17 and the barrier layer 16 thereon is then cooled in the pure oxygen environment flowing into the sub-atmospheric chamber at a pressure of about 2 torr and a specified temperature T in a range of approximately 15-20 °C for a second specified period of time t 2 of about 5- 15 seconds and preferably about 10 seconds.
- a metal oxide layer 18, e.g. copper oxide layer 18, is formed to a thickness in the range of approximately 5-100 angstroms (A).
- first specified period of time, ti, second specified period of time, t 2 , temperature, T, pressure in the copper-barrier seed deposition tool chamber, etc. may be modified according to the type of metal seed layer material used, type of gas introduced in the chamber, equipment specifications, manufacturing preferences, and other considerations.
- the substrate / wafer with is exposed to air while awaiting processing on the electroplating tool.
- in situ seed passivation (or seed surface treatment) of the Cu-seed layer 17 forms a layer of cupric oxide (Cu0 2 ). Since the Cu0 2 layer is formed, e.g. grown, inside a high vacuum chamber in the barrier-seed deposition tool, no contamination is trapped underneath this Cu0 2 layer 18.
- the CuO 2 layer 18 formed under vacuum conditions acts as a protective cover layer for the substrate structure 10 and its metal seed layer 17.
- FIGS le-lg and 2b an embodiment of the process of this invention for performing integrated seed anneal and plating of a patterned and/or substrate surface following substrate surface treatment process shown in FIG. 2a is illustrated.
- the process is integrated since the tasks described in the following paragraphs (and shown in blocks 250-270 of FIG. 2b) are performed in the same processing tool 320, e.g. the electroplating tool 320 (shown in FIG. 3b).
- the substrate structure / wafer 10 having the barrier layer 16, metal seed layer 17, e.g. Cu-seed layer 17, and metal seed passivation layer 18, e.g. Cu-seed oxide layer 18 (Cu0 2 ) formed in trenches 14, 15 and via 13 of structure ILD 12, is provided into a contamination removal chamber 322, e.g. an anneal chamber 322 (shown in FIG. 3b) of second semiconductor device processing tool 320, e.g. electroplating tool 320 (block 250 of FIG.
- the substrate structure 10 While in the contamination removal or anneal chamber of electroplating tool, the substrate structure 10 is annealed in a forming gas to eliminate or reduce the seed passivation layer 18, e.g. metal seed oxide layer 18, as well as to eliminate or reduce any contaminants on the substrate (block 260 of FIG. 2b).
- a forming gas to eliminate or reduce the seed passivation layer 18, e.g. metal seed oxide layer 18, as well as to eliminate or reduce any contaminants on the substrate (block 260 of FIG. 2b).
- the metal seed anneal process includes flowing a forming gas or other gas mixtures into the contamination removal or anneal chamber of the electroplating tool for a third specified period of time t 3 at a specified seed anneal temperature T sced anneal -
- the forming gas used in the seed anneal process comprises 95% nitrogen gas (N 2 ) and 5% hydrogen (H 2 ) flowing into the seed anneal chamber at a specified seed anneal temperature T se ed annea l of about 250° C for a third specified period of time t 3 of about 30 seconds.
- N 2 is provided into the anneal chamber at a flow rate of about 19 standard liters per minute (slm), while H 2 is provided into the anneal chamber at a flow rate of about 1 slm.
- the seed anneal process (block 260 in FIG. 3b) further includes cooling the annealed substrate structure 10 in the forming gas or other gas mixtures for a fourth specified period of time t at a seed anneal cooling temperature T see d annea l coo l ing-
- cooling the substrate structure in the forming gas of 95% N 2 and 5% H 2 includes flowing the forming gas into the seed anneal chamber at a seed anneal cooling temperature T see d anne al cooling of about 15-20° C for a fourth specified period of time t 4 of about 25 seconds.
- N 2 is generally provided into the anneal chamber at a flow rate of about 19 slm, while H 2 is injected into the anneal chamber at a rate of about 1 slm.
- the integrated seed anneal/electroplating process continues by performing electroless or electrolytic plating of substrate structure 10 to deposit a conductive material 19, e.g. metal or alloy, into trenches 14, 15, via 13 and overburden 21 of the substrate structure 10 (block 270 in FIG. 2b).
- the deposited conductive material will form a metal interconnect 22 for interconnection to the lower metal layer 11.
- Electroless and electrolytic plating processes that may be used to form metal interconnect 22 are known in the art. Electrolytic plating includes deposition of metal from an electrolyte solution by cathodic reduction according to the general principle below:
- Electroless plating includes deposition of metal from the electrolyte by chemical reduction.
- the reducing agent e.g. Red
- the substrate / wafer is the catalytic surface on which metal deposition takes place according to the general principle below:
- depositing a conductive material into trenches 14, 15, via 13 and overburden 21 of the substrate structure 10 to form a metal interconnect may be done utilizing an electroplating or an electroless plating technique.
- the plating may be done with a solution of copper sulfate (resulting in a copper plating), silver nitrate (resulting in a silver plating) or gold cyanide (resulting in a gold plating).
- metallic ions in a pH neutral copper-based solution such as a copper sulfate-based solution, may be reduced to a metallic state by applying current between seed material layer 17 and an anode of an electroplating cell in the presence of the solution. Copper metal becomes deposited onto seed material layer 17 to fill trenches 14, 15 and via 13 and form copper interconnection line 22.
- the substrate structure/wafer 10 is exposed to a first plating solution by means such as immersion of the substrate structure/wafer 10 into a plating bath, or by spraying the plating solution onto the structure/wafer 10.
- the first plating solution is an aqueous solution of an acid such as hydrofluoric acid or sulfuric acid, and a metal salt or complex that is soluble in the acid used.
- a redox reaction occurs between the metal ions in the solution, e.g., cupric ions (Cu 2+ ) and a reducing agent leading to reduction of the metal ions and subsequent plating onto the copper seed layer 17.
- the reaction typically proceeds at room temperature for a period of time until the conductive interconnect/level is formed. Time and temperature may be adjusted as necessary to affect the rate of the reaction, and is known in the art.
- a chemical-mechanical polishing (CMP) process or a chemical etch removal process may be performed as an optional task. CMP or chemical etch removal polishes away or removes the excess copper material 19 and the barrier layer 17 above the ILD layer 12, so that the only copper and barrier layer material left will be in trenches 14, 15 and via 13 (as shown in FIG. lg).
- system 310 is a metal barrier seed deposition tool 310, for example a copper-barrier seed deposition tool 310.
- the copper- barrier seed deposition tool 310 may have various configurations and arrangements, depending on the substrate manufacture process used, manufacturing preferences, etc.
- the copper-barrier seed deposition tool 310 includes a plurality of chambers 312, 314, 316, 318 that may be used for various phases of the process illustrated in FIG. 2a.
- chamber 312 of copper-barrier seed deposition tool 310 may be used as barrier layer deposition chamber
- vacuum chamber 314 may be used as a metal seed layer, e.g. Cu seed layer deposition chamber.
- Chamber 316 may be a cooldown chamber in the CBS tool 310, and may be used to perform in situ surface treatment of the seed layer to form a passivation layer, e.g., a metal seed oxide layer, under vacuum conditions.
- Chamber 318 may function as a load lock chamber for the copper barrier seed deposition tool 310.
- system 320 is an electroplating tool 320.
- the electroplating tool 320 also may have various configurations and arrangements, depending on the substrate manufacture process used, manufacturing preferences, etc.
- the electroplating tool 320 includes a plurality of chambers 322, 324, 326 that may be used for various phases of the process illustrated in FIG. 2b.
- chamber 322 of electroplating tool 320 may be a contamination removal chamber, e.g. seed anneal chamber, used to reduce or eliminate the seed passivation layer, e.g. metal seed oxide layer, formed in chamber 316 of the copper barrier seed deposition tool 310.
- a gas delivery system 350 may be coupled to the electroplating tool 320 to introduce a forming gas into the chamber 322 to remove or reduce the seed passivation layer and any absorbed contaminants.
- Chamber 324 may be an exemplary plating chamber while chamber 326 may be used as load/unload wafer cassettes chamber.
- the arrangement of electroplating tool 320 allows performing an integrated metal seed anneal / electroplating process of individual wafers / substrates.
Abstract
Description
Claims
Priority Applications (1)
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EP02750026A EP1417706A2 (en) | 2001-08-14 | 2002-07-12 | Apparatus and method of surface treatment for electrolytic and electroless plating of metals in integrated circuit manufacturing |
Applications Claiming Priority (2)
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US09/929,213 US7070687B2 (en) | 2001-08-14 | 2001-08-14 | Apparatus and method of surface treatment for electrolytic and electroless plating of metals in integrated circuit manufacturing |
US09/929,213 | 2001-08-14 |
Publications (2)
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WO2003023848A2 true WO2003023848A2 (en) | 2003-03-20 |
WO2003023848A3 WO2003023848A3 (en) | 2003-06-19 |
Family
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PCT/US2002/022314 WO2003023848A2 (en) | 2001-08-14 | 2002-07-12 | Apparatus and method of surface treatment for electrolytic and electroless plating of metals in integrated circuit manufacturing |
Country Status (5)
Country | Link |
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US (1) | US7070687B2 (en) |
EP (1) | EP1417706A2 (en) |
CN (1) | CN1319145C (en) |
TW (1) | TW559901B (en) |
WO (1) | WO2003023848A2 (en) |
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Also Published As
Publication number | Publication date |
---|---|
US20030034251A1 (en) | 2003-02-20 |
TW559901B (en) | 2003-11-01 |
EP1417706A2 (en) | 2004-05-12 |
CN1319145C (en) | 2007-05-30 |
CN1524292A (en) | 2004-08-25 |
WO2003023848A3 (en) | 2003-06-19 |
US7070687B2 (en) | 2006-07-04 |
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