WO2003029951A3 - Non-volatile memory control - Google Patents

Non-volatile memory control Download PDF

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Publication number
WO2003029951A3
WO2003029951A3 PCT/GB2002/004393 GB0204393W WO03029951A3 WO 2003029951 A3 WO2003029951 A3 WO 2003029951A3 GB 0204393 W GB0204393 W GB 0204393W WO 03029951 A3 WO03029951 A3 WO 03029951A3
Authority
WO
WIPO (PCT)
Prior art keywords
volatile memory
arrays
memory control
limiting
time
Prior art date
Application number
PCT/GB2002/004393
Other languages
French (fr)
Other versions
WO2003029951A2 (en
Inventor
Sergey Anatolievich Gorobets
Original Assignee
Lexar Media Inc
Sergey Anatolievich Gorobets
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lexar Media Inc, Sergey Anatolievich Gorobets filed Critical Lexar Media Inc
Priority to EP02762590.4A priority Critical patent/EP1451673B1/en
Priority to JP2003533096A priority patent/JP2005504388A/en
Publication of WO2003029951A2 publication Critical patent/WO2003029951A2/en
Publication of WO2003029951A3 publication Critical patent/WO2003029951A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1615—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4239—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0625—Power saving in storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0688—Non-volatile semiconductor memory arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

According to an embodiment of the present invention, there is provided a method and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of non-volatile memory arrays from a plurality of available arrays accessed at one time, wherein the method comprises implementing a pipelining sequence for transferring data to and from the non-volatile memory arrays and limiting the number of active arrays operating at one time, the arrangement being such that the controller waits for the at least one of the arrays to complete before initiating the transfer to and from a further array.
PCT/GB2002/004393 2001-09-28 2002-09-27 Non-volatile memory control WO2003029951A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP02762590.4A EP1451673B1 (en) 2001-09-28 2002-09-27 Non-volatile memory control
JP2003533096A JP2005504388A (en) 2001-09-28 2002-09-27 Nonvolatile memory control

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB0123416.0A GB0123416D0 (en) 2001-09-28 2001-09-28 Non-volatile memory control
GB0123416.0 2001-09-28

Publications (2)

Publication Number Publication Date
WO2003029951A2 WO2003029951A2 (en) 2003-04-10
WO2003029951A3 true WO2003029951A3 (en) 2004-06-03

Family

ID=9922931

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2002/004393 WO2003029951A2 (en) 2001-09-28 2002-09-27 Non-volatile memory control

Country Status (5)

Country Link
US (4) US6751155B2 (en)
EP (2) EP2275914B1 (en)
JP (2) JP2005504388A (en)
GB (2) GB0123416D0 (en)
WO (1) WO2003029951A2 (en)

Cited By (1)

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Publication number Priority date Publication date Assignee Title
US9122591B2 (en) 2004-05-13 2015-09-01 Sandisk Technologies Inc. Pipelined data relocation and improved chip architectures

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