WO2003043078A2

WO2003043078A2 - Preferential corner rounding of trench structures using post-fill oxidation

Info

Publication number: WO2003043078A2
Application number: PCT/US2002/028983
Authority: WO
Inventors: Jeffrey C. Haines
Original assignee: Advanced Micro Devices, Inc.
Priority date: 2001-11-13
Filing date: 2002-09-12
Publication date: 2003-05-22
Also published as: WO2003043078A3

Abstract

A method for fabricating a semiconductor device is disclosed. The method is manifested in several aspects, each involving an isolation structure (410) in an isolation trench (420) in a substrate (430). In one aspect, the method comprises forming (510) a trench (624) in a substrate (620), the trench (624) including a plurality of sidewalls (622), a bottom (623), and a plurality of corners (625); and overfilling the trench (624) with a dielectric material (628), the dielectric material (628) contacting the sidewalls (622), the bottom (623), and the corners; performing an oxidation operation to round the corners (625) of the trench (624) and densify the dielectric material (628).

Description

PREFERENTIAL CORNER ROUNDING OF TRENCH STRUCTURES USING POST-FULL OXD3ATION

TECHNICAL FIELD The present invention is directed to semiconductor manufacturing and, more particularly, to the preferential rounding of trench comers using post-fill oxidation.

BACKGROUND ART Integrated circuits are usually constructed from numerous devices all interacting in a predetermined manner. Various techniques for isolating devices within integrated circuits have been developed. One common isolation technique is known as "trench etch and fill," or "trench isolation." In this technique, a trench is etched into a substrate and is filled with a dielectric material. More technically, a dielectric material is deposited over the substrate using, typically, a chemical vapor deposition ("CVD") operation and a deposited oxide fills the trench. The etched trench may be shallow (depth < 1 μm), moderately deep (1 μm < depth < 3μm), or deep and narrow (depth > 3 μm and width < 2 μm).

However, such trench isolation techniques have some problems. The comers at the top edges of the trenches can produce undesirable parasitic edge transistors. When the comers are sharp, the enhanced electrical fields associated with the sharp comers tend to cause other problems. Still further, subsequent layers deposited on or spun onto a substrate tend to thin over the sharp corners, which causes yet more problems. Finally, sharp top comers also cause problems in filling the trenches — namely, non-uniform deposition that may leave voids or gaps in the trench fill. Many of these problems can be exacerbated by the trenches' "aspect ratio." The aspect ratio is, by definition, the ratio between the depth of the trench and the width of the trench.

Figure 1 shows a conventional isolation trench structure and illustrates some of these problems. Two trenches 124 are formed in a silicon substrate 120. The trenches 124 are filled with a fill oxide 128 to isolate active devices from each other. The fill oxide 128 remains substantially in place for the remainder of the process, although some thinning may occur prior to forming the gate electrode, depending upon the process sequence. An oxide layer 132 is then formed over the substrate 120. A gate polysilicon ("poly") electrode layer 136 is formed on top of the oxide layer 132 and positioned over the substrate 120 to form an active device with the ends of the gate poly electrode 136 extending over a portion of the trenches 124. When the gate oxide layer 132 and the gate poly electrode 136 are added, they recess partially into the trenches 124.

The structure creating the parasitic transistors and the thinness of the gate oxide layer 132 at the comers 125 are apparent from Figure 1. The conventional structure, as shown in Figure 1, forms parasitic edge transistors at the corners 125 of the trenches 124. The recessed portion 140 of the gate poly electrode 136 acts as a gate electrode of the parasitic transistor and the portion of the gate oxide layer 132 between the recessed portion 140 and the side wall 142 of the trench 124 acts as a gate oxide layer of the parasitic transistor. Further problems occur due to a thinning of the gate oxide layer 132 at the comers 125 of the trenches 124 where the gate oxide layer 132 recesses into the trenches 124. The thinned areas 144 of the gate oxide layer 132 can impact reliability from premature breakdown from the corners. One possible approach to reducing parasitic edge transistors involves doping the comer and edge regions of the trench sidewalls. By introducing dopants into the trench sidewalls, the parasitic edge transistors are shut off and the subthreshold kink in the device current (I_d) versus gate voltage (V_g) characteristic curve is suppressed to some extent. Figures 2A-2B illustrate a conventional technique for doping the corners 125 and upper portions of the trench sidewalls 142. After the trench 124 is etched in the substrate 120, a group of ions 214 are implanted into the comers 125 of the trench 124 using a method known as "angle implantation." The path traveled by the ions 214 is illustrated by the arrows. Figure 2B illustrates the trench 124 after the angle implantation is completed, wherein the comers 125 include doped regions 230.

One disadvantage of angle implantation is that it becomes extremely difficult for deep, narrow trenches, i.e., trenches having a high aspect ratio. Figures 2C-2D illustrate the relative difficulty of implanting the ions 214 into the trenches 124 as the aspect ratio increases. It is well known that the difficulty of ion implantation is a function of the incident angle α. The larger the incident angle α, the easier the angled ion implantation becomes. In Figures 2C-2D, the incident angle α is dependent on two independent variables — first, the width of the trenches and second, the thickness (t_m) of the implant blocking layer 205. Figure 2D illustrates the effect of an increase in the thickness (t_m) of the implant blocking layer 205, known as a shadowing effect, on the incident angle α.

Another disadvantage of the above-described conventional method is that the incident angle at which ion implantation is carried out needs to be adjusted in accordance with the trench width. Therefore, the wafer on which the integrated circuit devices are formed must be tilted so that a desired angle of incidence α is achieved with respect to one sidewall of the trench. Thereafter, the wafer must be rotated by 90° three times, so that each sidewall of the trench can be implanted at the same desired angle of incidence.

A second approach to this problem rounds the comers 125 so that they will not be as sharp, which will lessen the enhanced electric field and allow a more uniform deposition of the trench fill oxide. For example, as illustrated in Figures 3A-3B, one such process uses a pre-fill oxide liner 312 to round the top comers 125 of the trench. The pre-fill oxide liner 312 is thermally grown on the trench surfaces 315 at high temperatures. During the oxidation process, the silicon consumed results in rounded trench corners 125. A diffusion inhibiting layer 310, typically silicon nitride, prevents the active silicon surface 320 from oxidizing, allowing only the trench comers and side walls to be oxidized, as illustrated in Figure 3A. The pre-fill oxide liner 312 can either be removed by etch or left in place prior to trench fill. Subsequently, when the trench 124 is filled and the oxide layer 132 is then formed over the rounded comers 125, the magnitude of the electric field generated during device operation as a function of sharp comers is lessened.

The problem associated with using edge rounding techniques, such as the sacrificial oxide technique discussed above, is that while rounding the top comers 125, the trench silicon 315 is also consumed, such that the finished trench 124 will not only have rounded top comers, but the trench silicon surface 315 is recessed under the diffusion inhibiting layer 310. Subsequent processing typically results in a "blivet recess" 326, shown in Figure 3B. Finally, a pre-oxidation liner increases the aspect ratio of the trench, making it more difficult to fill. Some of the rounding techniques sacrifice the critical dimension of the trench. Sacrificial oxide techniques also take a very long time and slow down the overall manufacturing process.

DISCLOSURE OF INVENTION

A method for fabricating a semiconductor device is disclosed. The method is manifested in several aspects, each involving an isolation structure in an isolation trench. In one aspect, the method comprises forming a trench in a substrate, the trench including a plurality of sidewalls, a bottom, and a plurality of corners; overfilling the trench with a dielectric material, the dielectric material contacting the sidewalls, the bottom, and the comers; performing an oxidation operation to round the comers of the trench and densify the dielectric material; and planarizing the dielectric material. Other aspects include various alternative embodiments along these lines and structures created using these processes.

BRIEF DESCRIPTION OF THE DRAWINGS The invention may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:

Figure 1 depicts in cross-section a structure that is a portion of a semiconductor device and illustrates some of the deficiencies arising from current practices in semiconductor fabrication; Figures 2A-2D illustrate a conventional ion implantation approach to mitigating parasitic transistor effects engendered by the deficiencies illustrated in Figure 1;

Figures 3A-3B illustrate a conventional pre-liner approach to mitigating these same parasitic transistor effects;

Figure 4 depicts, in a cross-sectional view, a structure fabricated in accordance with the present invention;

Figure 5 depicts one method for fabricating the structure in Figure 4 in accordance with the present invention;

Figures 6A-6D illustrate the method of Figure 5;

Figure 7 depicts a second method for fabricating the structure of Figure 4 in accordance with the present invention; and

Figures 8A-8C illustrate the method of Figure 7.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

MODE(S) FOR CARRYING OUT THE INVENTION Illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort, even if complex and time-consuming, would be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

The present invention will now be described with reference to the remaining drawings. Although the various regions and structures of a semiconductor device are depicted in the drawings as having very precise, sharp configurations and profiles, those skilled in the art recognize that, in reality, these regions and structures are not as precise as indicated in the drawings. Additionally, the relative sizes of the various features depicted in the drawings may be exaggerated or reduced as compared to the size of those feature sizes on fabricated devices. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present invention.

In general, the present invention is directed to a semiconductor device having improved electrical performance characteristics and a method of making such a device. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the present method is applicable to a variety of technologies, e.g., NMOS, PMOS, CMOS, etc., is readily applicable to a variety of devices, including, but not limited to, logic devices, memory devices, etc. Indeed, the present invention can be used in conjunction with stnicture including stacked active layers over a substrate that may be oxidized, includin — but not limited to — doped, bulk silicon, SOI, etc.

Figure 4 illustrates a structure 400, which is a portion of a semiconductor device after fabrication in accordance with the present invention. The structure 400 comprises an isolation structure 410 formed in an isolation trench 420 in a substrate 430. Note that the isolation structure 410 rises a thickness t above the surface of the substrate 430 and that the comers 425 are well rounded. Thus, the structure 400, when further processed by the formation of a gate poly layer, will not be susceptible to preferential comer leakage as was described above. The structure 400 may be fabricated using any of the processes described below.

Figures 5 and 6A-6D illustrate a first process for use in manufacturing the structure 400 in accordance with the present invention. Figure 5 illustrates the acts of the process 500, and Figures 6A-6C conceptually depict the consequence of the acts set forth in Figure 5 on a structure 600. The process 500 begins by forming a trench 624 in a substrate 620, as set forth in the box 510 and shown in Figure 6A. The trench 624 may be formed by a traditional anisotropic etch in accordance with conventional practice. Note the sharpness of the comers 625 of the trench 624, which is undesirable.

The process 500 continues by forming a isolation structure in the trench 624 immediately after forming the trench 624 in the substrate 620, as set forth in the box 520. "Immediately," as used herein, does not connote any particular lapse of time. Instead, the term "immediately" denotes that the isolation structure formation occurs without any intervening steps directed to forming a pre-liner. Thus, this embodiment obviates a number of problems associated with pre-liners. Namely, increased aspect ratios resulting from pre-liner formation are reduced. Also, the lesser recession of the silicon surface 315 under the diffusion inhibiting layer 310 reduces and/or eliminates the blivet recess. This embodiment also is beneficial in eliminating process steps, since the pre-liner need not be grown or stripped from the trench 624 and there is no need to implant ions in the comers 625. However, in some alternative embodiments, both pre-liners and ion implantation may be used to supplement the present invention.

Referring now to both Figures 5 and 6B-6C, the isolation structure is formed in this embodiment by first overfilling the trench 624 with a dielectric material 628, as set forth in the box 530 and shown in Figure 6B. Note that the dielectric material 628 directly touches the sidewalls 622 and the bottom 623 of the trench 624. The dielectric material 628 is then oxidized, as set forth in the box 540. However, in one variation, the dielectric material 628 is oxidized prior to planarization and in a second variation, the dielectric material 628 is oxidized after planarization. The first variation is illustrated in Figure 6C and the second variation is illustrated in Figure 6D.

In both variations, the dielectric material 628 is oxidized by exposure to an atmosphere containing an oxidizing agent 650. The oxidizing agent 650 attacks the comers 625 of the trench 624, as symbolized by the arrows, and rounds them while densifying the dielectric material 628 to form the isolation structure 410 of the

_" structure 400 in Figure 4. If oxidation occurs before planarization, as in Figure 6C, the oxidizing agent 650 attacks the corners 625 by diffusing through the overfilled, dielectric material 628. The overfilled dielectric material 628 must then be planarized. If the oxidation occurs after planarization, as in Figure 6D, the oxidizing agent 650 attacks the comers 625 more efficiently, since there is very little remaining oxide through which the oxidizing agent must diffuse. When oxidation occurs after planarization, the oxidation yields better rounding and a thicker oxide covering over the comers 615 in less process time and, potentially, at lower temperatures. In either case, planarization may be performed using conventional practices, such as chemical-mechanical polishing ("CMP"), plasma etch, or both.

Figures 7 and 8A-8C illustrate a second process by which the structure 400 may be manufactured in accordance with the present invention. This particular embodiment employs a pre-liner 855 and oxidizes the dielectric material 828 after planarization. Figure 7 illustrates the process 700 more particularly. The process 700 begins, like the process 400, by forming a trench 824 in the substrate 820, as set forth in the box 710. The trench 824 may be formed in accordance with conventional practice such as by anisotropic etch. A pre-liner 855 is then formed in the trench 824, as set forth in the box 720, also using conventional practice.

The process 700 then continues by forming an isolation structure 410 in the trench 824, as set forth in the box 730. In the particular embodiment illustrated, this involves first overfilling the trench 824 with a dielectric material 828, as set forth in the box 740. The dielectric material 828 and the pre-liner 855 are then planarized using conventional planarization techniques. The planarized dielectric material 828 and pre-liner 855 are then oxidized by exposure to an oxidizing agent 850. Since the structure 800 has already been planarized, the oxidizing agent 850 attacks the comers 825 more efficiently because it has less to diffuse through. Since the oxide layer over the silicon trench comers that were previously recessed under the nitride layer will be effectively increased, the blivet recess problems will be lessened. Note that the comers 825 are already slightly rounded at this point by the operation of the pre-liner 855. After oxidation, the pre-liner 855 and the dielectric material 828 may become indistinguishable and together form the isolation structure 410 in Figure 4.

The choice of materials for the various embodiments will be implementation specific and will include traditional considerations of selective chemistry. Most implementation specific aspects of the present invention will be readily apparent to those skilled in the art having the benefit of this disclosure. For example, the substrates 620, 820 may comprise bulk, doped silicon, SOI, or any material that may be oxidized and on which active stacked layers may be formed; the dielectric materials 628, 828 may comprise silicon dioxide (Si0₂) or silicon oxynitride; the oxidizing agents 650, 850 may be wet or dry oxygen at either full or partial pressure conditions, and the pre-liner 855, may be oxide or oxynitride, each depending upon the particular implementation. For example, the choice of materials for the oxidizing agents 650, 850 will depend, at least in part, on the material from which the substrates 620, 820 and the oxides materials 628, 828 are selected, to achieve proper diffusion and oxidation.

The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.

Claims

1. A method for fabricating a semiconductor device, comprising: forming (510) a trench (624) in a substrate (620), the trench (624) including at least two sidewalls

(622) and a bottom (623); and forming (520) an isolation structure (410) in contact with the sidewalls (622) and bottom (623) of the trench (624), including: overfilling (530) the trench (624) with a dielectric material (628); and oxidizing (540) the overfilled trench (624).

2. The method of claim 1, wherein the dielectric material (628) is selected from the group consisting of silicon dioxide, silicon oxynitride.

3. The method of claim 1, wherein the substrate (620) comprises a bulk, doped silicon or SOI.

4. The method of claim 1, wherein the oxidizing agent (650) is selected from the group consisting of wet oxygen and dry oxygen.

5. The method of claim 1, further comprising the planarizing the dielectric material (628).

6. The method of claim 5, wherein planarizing the oxidized dielectric material (628) includes polishing with at least one of a chemical-mechanical polish and a plasma etch.

7. A method for fabricating a semiconductor device including a trench (624) in a substrate (620) overfilled with a dielectric material (628), characterized in that an oxidation is performed after overfilling the trench (624).

8. The method of claim 7, wherein the dielectric material (628) is selected from the group consisting of silicon dioxide, silicon oxynitride.

9. The method of claim 7, wherein the substrate (620) comprises a bulk, doped silicon or SOI.

10. The method of claim 7, wherein the oxidizing agent (650) is selected from the group consisting of wet oxygen and dry oxygen.

11. The method of claim 7, further comprising the planarizing the dielectric material (628).

12. The method of claim 11, wherein planarizing the oxidized dielectric material (628) includes polishing with at least one of a chemical-mechanical polish and a plasma etch.

13. A structure manufactured by the method of any one of claim 1 to claim 12.