WO2003043078A3 - Preferential corner rounding of trench structures using post-fill oxidation - Google Patents

Preferential corner rounding of trench structures using post-fill oxidation Download PDF

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Publication number
WO2003043078A3
WO2003043078A3 PCT/US2002/028983 US0228983W WO03043078A3 WO 2003043078 A3 WO2003043078 A3 WO 2003043078A3 US 0228983 W US0228983 W US 0228983W WO 03043078 A3 WO03043078 A3 WO 03043078A3
Authority
WO
WIPO (PCT)
Prior art keywords
trench
preferential
post
trench structures
corner rounding
Prior art date
Application number
PCT/US2002/028983
Other languages
French (fr)
Other versions
WO2003043078A2 (en
Inventor
Jeffrey C Haines
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of WO2003043078A2 publication Critical patent/WO2003043078A2/en
Publication of WO2003043078A3 publication Critical patent/WO2003043078A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS

Abstract

A method for fabricating a semiconductor device is disclosed. The method is manifested in several aspects, each involving an isolation structure (410) in an isolation trench (420) in a substrate (430). In one aspect, the method comprises forming (510) a trench (624) in a substrate (620), the trench (624) including a plurality of sidewalls (622), a bottom (623), and a plurality of corners (625); and overfilling the trench (624) with a dielectric material (628), the dielectric material (628) contacting the sidewalls (622), the bottom (623), and the corners; performing an oxidation operation to round the corners (625) of the trench (624) and densify the dielectric material (628).
PCT/US2002/028983 2001-11-13 2002-09-12 Preferential corner rounding of trench structures using post-fill oxidation WO2003043078A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US854401A 2001-11-13 2001-11-13
US10/008,544 2001-11-13

Publications (2)

Publication Number Publication Date
WO2003043078A2 WO2003043078A2 (en) 2003-05-22
WO2003043078A3 true WO2003043078A3 (en) 2003-11-06

Family

ID=21732194

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/028983 WO2003043078A2 (en) 2001-11-13 2002-09-12 Preferential corner rounding of trench structures using post-fill oxidation

Country Status (1)

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WO (1) WO2003043078A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8173516B2 (en) * 2010-02-11 2012-05-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming shallow trench isolation structure

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS583247A (en) * 1981-06-30 1983-01-10 Toshiba Corp Manufacture of semiconductor device
US5236861A (en) * 1991-08-16 1993-08-17 Sony Corporation Manufacturing method of metal-insulator-semiconductor device using trench isolation technique
US5518950A (en) * 1994-09-02 1996-05-21 Advanced Micro Devices, Inc. Spin-on-glass filled trench isolation method for semiconductor circuits
US5786262A (en) * 1997-04-09 1998-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Self-planarized gapfilling for shallow trench isolation
JPH1197523A (en) * 1997-07-31 1999-04-09 Lucent Technol Inc Device manufacturing process
US5930620A (en) * 1997-09-12 1999-07-27 Advanced Micro Devices Resistance to gate dielectric breakdown at the edges of shallow trench isolation structures
WO1999062108A2 (en) * 1998-05-22 1999-12-02 Applied Materials, Inc. Methods for forming self-planarized dielectric layer for shallow trench isolation
US6110793A (en) * 1998-06-24 2000-08-29 Taiwan Semiconductor Manufacturing Company Method for making a trench isolation having a conformal liner oxide and top and bottom rounded corners for integrated circuits
EP1049154A2 (en) * 1999-04-28 2000-11-02 Sharp Kabushiki Kaisha Process for forming device isolation region
WO2001013420A1 (en) * 1999-08-16 2001-02-22 Applied Materials, Inc. Integration scheme using self-planarized dielectric layer for shallow trench isolation (sti)

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS583247A (en) * 1981-06-30 1983-01-10 Toshiba Corp Manufacture of semiconductor device
US5236861A (en) * 1991-08-16 1993-08-17 Sony Corporation Manufacturing method of metal-insulator-semiconductor device using trench isolation technique
US5518950A (en) * 1994-09-02 1996-05-21 Advanced Micro Devices, Inc. Spin-on-glass filled trench isolation method for semiconductor circuits
US5786262A (en) * 1997-04-09 1998-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Self-planarized gapfilling for shallow trench isolation
JPH1197523A (en) * 1997-07-31 1999-04-09 Lucent Technol Inc Device manufacturing process
US6566224B1 (en) * 1997-07-31 2003-05-20 Agere Systems, Inc. Process for device fabrication
US5930620A (en) * 1997-09-12 1999-07-27 Advanced Micro Devices Resistance to gate dielectric breakdown at the edges of shallow trench isolation structures
WO1999062108A2 (en) * 1998-05-22 1999-12-02 Applied Materials, Inc. Methods for forming self-planarized dielectric layer for shallow trench isolation
US6110793A (en) * 1998-06-24 2000-08-29 Taiwan Semiconductor Manufacturing Company Method for making a trench isolation having a conformal liner oxide and top and bottom rounded corners for integrated circuits
EP1049154A2 (en) * 1999-04-28 2000-11-02 Sharp Kabushiki Kaisha Process for forming device isolation region
WO2001013420A1 (en) * 1999-08-16 2001-02-22 Applied Materials, Inc. Integration scheme using self-planarized dielectric layer for shallow trench isolation (sti)

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
ELBEL N ET AL: "A new STI process based on selective oxide deposition Yfor CMOS logic", VLSI TECHNOLOGY, 1998. DIGEST OF TECHNICAL PAPERS. 1998 SYMPOSIUM ON HONOLULU, HI, USA 9-11 JUNE 1998, NEW YORK, NY, USA,IEEE, US, 9 June 1998 (1998-06-09), pages 208 - 209, XP010291189, ISBN: 0-7803-4770-6 *
PATENT ABSTRACTS OF JAPAN vol. 007, no. 072 (E - 166) 25 March 1983 (1983-03-25) *
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 09 30 July 1999 (1999-07-30) *

Also Published As

Publication number Publication date
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