WO2003052812A2

WO2003052812A2 - Non volatile memory cell with a trench transistor

Info

Publication number: WO2003052812A2
Application number: PCT/DE2002/004523
Authority: WO
Inventors: Frank Lau; Dezsö TAKACS; Josef Willer
Original assignee: Infineon Technologies Ag
Priority date: 2001-12-18
Filing date: 2002-12-10
Publication date: 2003-06-26
Also published as: KR100554647B1; WO2003052812A3; KR20040065288A; CN1605120A; EP1456876A2; CN100382254C; JP4081445B2; JP2005513778A; TW575960B; TW200302571A

Abstract

A memory cell with a trench transistor which is arranged in a trench embodied on an upper side of a semi-conductor body. An oxide-nitride-layer sequence is provided between the gate-electrode arranged in the trench and between the source area laterally bordering thereon and between the drain area bordering on the other side thereof. Said sequence layer is provided for capturing charge carriers on the source and drain. Said type of transistors are especially suitable for NVM-memory cell devices (Non-Volatile Memory).The depth of the trench is optimised in such a way that the locations for the injection of electrons and holes coincide in the memory layer (11) disposed between the walls of the trench and the gate electrode (4) in defining layers (10,12). The junctions (14) where the doping of the source area (2) and the drain area (3) switches to an opposite polarity sign of conductivity type of the semiconductor body (1), and which define the channel area (5), abut against a curved area of the bottom (7) of the trench or a lower curved area of the side walls (6,8) of the trench.

Description

description

Memory cell with trench transistor

The present invention relates to a memory cell with a memory transistor which has a gate electrode on an upper side of a semiconductor body or a semiconductor layer, which has a gate in a trench formed in the semiconductor material of the semiconductor body or the semiconductor layer and which has cross sections which are at least sectionally identical to a longitudinal direction, is arranged between a source region and a drain region, a dielectric layer provided as a storage medium, preferably an ONO layer, being present between the gate electrode and the semiconductor material.

DE 100 39 441 A1 describes a memory cell with a trench transistor which is arranged in a trench formed on an upper side of a semiconductor body. An oxide-nitride-oxide layer sequence is present between the gate electrode introduced into the trench and the source region adjoining it on the side and the drain region adjoining it on the other side, which is used for trapping charge carriers at the source and drain is provided. Such transistors are particularly for NVM

Memory cell arrangements (non-volatile memory) suitable. The areas which each have the necessary electric field strengths for programming and erasing are generally at different positions with these transistors. As a result, once programmed, loads on the

It is difficult to completely quench nitride. An injection of electrons is necessary for the programming process. For this purpose, the electrons have to penetrate the boundary layer made of oxide in order to reach the nitride layer provided as the storage layer. Therefore, the electrons are required to have high kinetic energy; they are so-called hot electrons. Such electrons are only present where the electrical field strength is very large in the channel formed on the top of the semiconductor material under the gate electrode.

In the accompanying FIG. 5, a diagram is shown for explanation, which shows the gate electrode 4, the gate dielectric 9, which can in particular be an ONO storage layer, and the semiconductor material adjacent to it with the channel region 5 from left to right. The energy that increases in the direction of the arrow is plotted in the vertical direction marked with the arrow. The entered curves a and b indicate the upper limit of the valence band and the lower limit of the conduction band. Two Fermi energy levels Efi and E _{f2 are} shown. Up to these energy levels, the states that can only be occupied according to the Pauli principle are filled with electrons. If the Fermi energy level E _f ι is lower, there are only a few electrons in the conduction band at the boundary of the semiconductor material, as is indicated in FIG. 5 by the hatched area. It can be seen that in

In the case of a higher Fermi energy level E _{f2, there are} more electrons in the conduction band and also higher energy electrons are present. It is therefore easier for the higher-energy electrons to tunnel through the oxide layer delimiting the nitride storage layer.

FIG. 6 shows a typical transistor structure in cross section, in which a source region 2, a drain region 3, a gate electrode 4, a gate dielectric 9 and the channel region 5 are shown. A space charge zone of the channel which forms is delimited by dashed lines. When the intended voltages required for programming such a transistor are applied, the electrons are accelerated in the direction of the arrows drawn through the channel region. The length of the arrows is intended to indicate the mean kinetic energy of the electrons without scale accuracy. It can be seen here that the mean kinetic Energy of the electrons increases very strongly towards the drain region 3. This increase is strongly disproportionate, since the electric field strength increases sharply towards the drain region 3 up to shortly before the drain region. When the electrons reach the end of the channel region 5, their energy is so high that they can get into the storage layer.

In the case of a memory transistor arranged in a trench, the region in which the electrons have an energy suitable for programming is also located at the end of the channel region, which here on one side of the trench bottom directly below the transition of the p-type doped substrate into the n ⁺ conductive doped drain region ends. In a cross section with the source area on the left and the drain area on the right, this area of preferred programming is located at the bottom of the trench approximately at the bottom right.

Injection of holes (charge carriers of opposite signs) is necessary for the extinguishing process, which can only be achieved in an n-MOSFET through the GIDL effect (gate-induced drain leakage). This effect only occurs in the vicinity of the drain area. The places where electron injection and hole injection take place are therefore not necessarily identical. Such a memory cell can therefore only be erased with a high applied voltage and / or very long erase times.

The object of the present invention is to provide a memory cell with a trench transistor in which the programming and

Erase times are significantly reduced compared to conventional memory cells of this type.

This object is achieved with the memory cell with the features of claims 1, 3, 7 and 8. Refinements result from the dependent claims. According to the invention, the depth of the trench in relation to an area in which charge carriers of the storage layer are neutralized during a deletion process is selected so that during a programming process one is parallel to the tangent to a wall or to the bottom of the trench and perpendicular to component in the longitudinal direction of the trench of an electric field acting on the charge carriers is maximal in the same area. In this way, the trench depth is optimized in such a way that the locations for electron and hole injections coincide. The junctions, in which the doping of the source region and the drain region changes into the opposite sign of the conductivity type of the substrate or semiconductor body, abut against a curved region of the trench bottom or a curved lower region of the lateral trench walls.

A more detailed description of the memory cell follows with reference to FIGS. 1 to 6.

Figure 1 shows a cross section through two adjacent trenches in the diagram as a schematic diagram.

FIG. 2 shows the cross section according to FIG. 1 for two trenches simulated on the basis of a model calculation with a drawn-in course of the downward facing E-

Field component.

FIGS. 3 and 4 show corresponding cross sections for memory cells designed according to the invention.

FIGS. 5 and 6 show the representations explained in the introduction to the description.

FIG. 1 shows a cross section in which two trenches produced in a semiconductor body 1 as a substrate or in a semiconductor layer applied to a substrate are shown. At least in sections, the transverse cuts of the trenches in the longitudinal direction of the trenches are the same. The representation of FIG. 1 would therefore look the same for a cut in front of and behind the plane of the drawing. In the description and in the claims, the longitudinal direction of the trenches is to be understood as this direction, along which a perpendicular cut does not change.

In a region on the relevant top side of the semiconductor body 1 or the semiconductor layer, a source region 2 and a drain region 3 are formed by introducing dopant, here referred to as an example of the left trench transistor. The semiconductor body 1 is, for. B. doped p-type; the source region 2 and the drain region 3 are then designed to be n ⁺ -conducting. The generally clearly defined boundaries between the regions doped in opposite directions are referred to below as junctions 14; their position within the semiconductor material is detectable (for example with SIMS). In the trench is a gate electrode 4, z. B. made of polysilicon. A channel region 5 is formed below the source and drain regions opposite the gate electrode at the interface of the semiconductor material.

The side walls 6, 8 and the bottom 7 of the trench are understood to be the surface of the semiconductor material facing the trench. Between the gate electrode 4 and the semiconductor material there is a dielectric layer 9 as a gate dielectric, which covers the walls and the bottom of the trench. This dielectric layer 9 is designed as a storage medium. For this purpose, the dielectric

Layer 9 preferably has multiple layers and comprises at least one storage layer 11 which, in the example shown in FIG. 1, is arranged between boundary layers 10, 12. The boundary layers 10, 12 are, for. B. oxides, here especially silicon dioxide, while the storage layer 11 can be nitride, here Si ₃ N ₄ . During operation of the memory cell, for example, on the source region, a voltage of 0 V to the gate electrode 4, a ^■ voltage of 9 V and the drain region 3, a voltage of 6 V for programming at; for deletion there is, for example, -8 V at the gate electrode and 5 V at the drain region. In the trench of the memory cell shown on the left, the dielectric layer 9 in the bottom region of the trench is omitted in the drawing, which is indicated by corresponding break lines. For a more detailed explanation of the following, a horizontal arrow 22 to indicate the lateral direction from source to drain and a vertical arrow 23 to indicate the vertical direction into the depth of the trench are shown. There is also the distance 24 between the walls of the trench at the height of the junctions 14 and the depth 25 of the trench below the height of the junctions 14, that is to say the total vertical dimension of the trench from a junction 14 to the lowest point of the Grabens, drawn.

The electrical voltage is applied to the source regions 2 and the drain regions 3 via contacts mounted thereon in front of and behind the plane of the drawing, while the gate voltage is connected across the transverse, i.e. H. word line 13 extending in the drawing plane is supplied. When programming, the voltage values drawn in for a trench with a bottom in the form of the shell of a half cylinder result in a distribution of the electrical field strength, the component of which, in the cross-sectional plane shown, tangentially to the bottom or to the wall of the trench to the right below the junction is maximum.

These relationships are shown in FIG. 2, in which the cross section shown in FIG. 1 as a schematic diagram for the model calculation for trenches with a semi-cylindrical bottom is shown. The curves drawn represent the lines of the cross-section on which the component E _{y of} the electric field designated by the arrow each has the same value. Certain can be derived from this Draw conclusions about the magnitude of the component of the electric field that runs tangentially to the trench wall or to the trench bottom within this cross section.

It can be seen here that in the case of the left memory cell which is biased for programming with the corresponding voltages according to FIG. 1, a maximum of the field component running in the longitudinal direction of the channel occurs approximately in the direction of the arrow 22 turned down by 30 ° when this arrow (now 22 ') through the axis A of the half cylinder forming the bottom. The efficient programming of the memory cell takes place at this point, while the hole injection during the erasing process takes place in the area directly above the junction 14 of the drain area 3.

FIG. 3 shows a memory cell of this type which has been optimized in accordance with the invention, in which the relevant region of the bottom curvature of the trench is arranged in the vicinity of the pn junction between the drain region 3 and the semiconductor material doped in the opposite direction. The exact dimensions of the memory cell optimized in this regard can be found for a respective exemplary embodiment on the basis of model calculations and simulations familiar to the person skilled in the art and / or experimentally on the basis of implemented components without fundamental difficulties. However, it is not possible to provide corresponding numerical data for all of the embodiments within the scope of the invention. Therefore, it will be explained in detail below what the principle of the invention consists of. This is the technical

Teaching is given to the extent of what is required to enable those skilled in the art to manufacture such a memory cell.

First of all, the knowledge that not the channel length alone, but essentially the type of curvature of the trench bottom and the lower area of the lateral trench contributes to this. walls is decisive for the course of the field component directed tangentially to the trench wall. Contrary to the previous assumption that the trench must be formed so deep into the semiconductor material that a substantial portion of the wall of the trench is below the area of the source and drain, the storage cell according to the invention ensures that a lateral curvature lies between the actual floor and the essentially vertical side wall of the trench in the area in which the hole injection takes place during the deletion process. The areas intended for programming and deleting by injecting load carriers are thus covered directly above the pn junction. The trench depth is reduced accordingly.

This is shown in cross section in FIG. 3, in which the reference symbols have the same meaning as in the previous figures. The vertical dimension of the source region 2 and the drain region 3 between the upper side of the semiconductor body 1 or the semiconductor layer and the junction 14 between the source region 2 or the drain region 3 and the semiconductor material doped in the opposite direction in practical configurations, however, it does not have to form a flat surface, but rather can be somewhat irregular, is only slightly smaller than the entire vertical dimension of the trench in the storage cell. When determining the position of the junction using SIMS, averaging is carried out over a certain area.

The vertical dimension of the trench has an overhang downwards beyond the junctions 14, which is referred to below as the depth 25 of the trench. Here, from the height of the junctions 14 in the trench to the lowest point of the trench bottom in the vertical direction, that is to say perpendicularly from the level of the upper main side of the semiconductor body or the semiconductor layer. lent the plane of the top of the semiconductor body or the semiconductor layer.

In preferred exemplary embodiments, this depth 25 is at most half as large as the distance 24 of the walls of the trench (trench width) at the height of the junctions 14. The depth 25 is selected depending on the relevant geometric shape of the trench cross section such that the junctions 14 meet the wall touch the trench in an area in which the curve of the wall of the trench in a cross section oriented transversely to the longitudinal direction has a radius of curvature which is at most two thirds as large as the distance 24 of the walls of the trench at the height of the junctions 14.

If the bottom of the trench has the shape of the shell of a half cylinder with a radius r, the distance 24 of the walls of the trench at the level of the junctions 14 is at most twice as large as this radius, namely at most 2r. The radius of curvature of the trench floor is everywhere r in this example; accordingly, the depth 25 is preferably at most equal to r, better somewhat smaller.

If the radius r of said half-cylinder is 55 nm, for example, the depth is 55 nm or slightly less. Since the channel length should not be too short, a value of 30 nm can be specified as the lower limit for the depth 25 that should be observed if possible. The arc of the trench bottom visible in cross section below the junctions 14, which approximately represents the length of the channel, is at this depth 25 of 30 nm approximately 120.88 nm for the specified radius r of 55 nm and approximately 134.76 nm for a radius r of 70 nm; the distance 24 of the walls of the trench at the height of the junctions 14 is 97.98 nm for r = 55 nm and 114.89 nm for r = 70 nm, so in both cases the radius of curvature is at the point where the junctions 14 abut the walls of the trench, less than two thirds of the distance 24 of the walls of the trench at the level of the junctions 14. If the vertical dimension of the source region 2 and the drain region 3 is 150 nm, for example, the optimal total trench depth measured from the plane of the top of the semiconductor body or the semiconductor layer is in the range from 180 nm to 205 nm for a radius r from 55 nm and from 180 nm to 220 nm for a radius r of 70 nm. In this example, the bottom of the trench need not have the shape of the shell of a complete half cylinder; the trench walls on the side can directly or at a short distance above the junctions essentially evenly adjoin the curved bottom, so that there only the jacket of a segment of a half cylinder, that is, the jacket of a cylinder sector with a central angle below 180 °, is present on the ground.

The trench depth is to be adapted accordingly to other radii of curvature of the trench floor or other forms of the trench floor. The level of the dopant concentrations also plays a role, a possible additional implantation of the channel region 5 also having to be taken into account. An implantation to increase the conductivity of the channel and to reduce the electric field at the points of greater trench curvature makes it possible to provide a somewhat stronger curvature even in those areas of the trench bottom in which no charge carrier injection into the storage layer is to take place. It is therefore within the scope of the invention to provide a somewhat tapered trench bottom and in the region of the deepest point of the trench bottom an implantation of dopant into the semiconductor material present underneath. It can be advantageous here to provide a longer channel length by choosing the depth 25 to be greater than half the distance 24 between the walls of the trench at the height of the junctions 14. But also in this example, in the cross section perpendicular to the longitudinal direction of the trench, the curve of the wall where the junctions 14 abut the trench walls, have a radius of curvature of at most two thirds of the distance 24.

In some embodiments, it may be advantageous if the depth 25 of the trench is significantly less than half the distance 24 of the walls of the trench at the level of the junctions 14, in particular if the trench has a bottom with a less curved or flat inner portion and has more curved lateral portions and the far predominant portions of the walls run at least almost vertically, so that a substantial curvature is only present on the lower sides of the floor. In these embodiments, however, it must be taken into account that the channel length may not be sufficient with a very shallow depth 25 and a fairly shallow trench bottom, or at least a part of the optimization sought according to the invention will be compensated for because of the short channel length.

The upper side of the side walls of the trenches can be inclined to the vertical (arrow 23 in FIG. 1). FIG. 4 shows a corresponding cross section of a further exemplary embodiment, in which the lateral walls of the trenches are arranged in a clearly oblique manner in the upper regions with an angle of inclination of approximately 5 ° to the vertical. In this exemplary embodiment, the lateral walls 6, 8 have narrow regions 15, 17 which extend somewhat above the trench floor 7 in the longitudinal direction of the trenches and in which the direction of the lateral walls bends slightly within the cross section. In the lower regions 16, 18 of the side walls, the directions of the tangents to the walls lie within the cross section in larger angular ranges of up to 10 ° to the vertical. The bottom 7 of the trench is here curved relatively weakly, so that between the lower regions 16, 18 of the side walls and the bottom 7 of the trench there are areas of markedly greater curvature of the trench wall. In this exemplary embodiment, the depth 25 of the trench is selected approximately such that the pn junction (junction 14) between the source region and the oppositely doped semiconductor material or between the drain region and the oppositely doped semiconductor material is approximately at the level of the latter Curvature or just above it. It can also be assumed here that the programming takes place in the area of the trench wall just above the area with the greatest curvature.

For further explanation, the dielectric layer 9 in the lower region is omitted in the cross section of the right trench in FIG. 4, which is also indicated here by corresponding break lines. There radii of curvature 19, 20 and 21 are entered with lengths that are not to scale without any claim to precision. The lengths shown are only intended to illustrate that the radius of curvature 19 is very small in the areas present to the side of the actual floor. The adjoining regions 16, 18 of the side walls have a substantially larger radius of curvature 20. The radius of curvature 21 of the base 7 is also relatively large.

If one looks at the tangent to the trench wall in the plane of the drawing transverse to the longitudinal direction of the trench, the proportion of the wall that is formed by side walls can be defined by the relatively small angle of inclination of at most 10 ° to the vertical (arrow 23) , In the trench of the embodiment according to FIG. 4, portions of the wall of the trench are located between these side walls and a deepest point of the ground, each of which has a radius of curvature which is at most half as large at each point within the cross section perpendicular to the longitudinal direction of FIG. 4 is like the distance 24 of the walls of the trench at the level of the junctions 14. The junctions 14 abut the lateral walls of the trenches in these areas. It can be assumed that the area in which the hole injection takes place during extinguishing coincides at least approximately with the area of greatest curvature of the wall of the trench. It can therefore be advantageous if the junctions 14 abut the lateral trench walls in a region in which the radius of curvature is at most 10% larger than its smallest value assumed on the trench wall.

The memory cell preferably has the mirror-symmetrical design shown in the figures, since in this case, by reversing the applied voltages, the programming and deletion can also take place in the area of the memory layer which is located on the left in the figures.

LIST OF REFERENCE NUMBERS

1 semiconductor body

2 source area 3 drain area

4 gate electrode

5 channel area

6 side wall

7 floor 8 side wall

9 dielectric layer

10 boundary layer

11 storage layer

12 boundary layer 13 word line

14 junction

15 narrow area

16 lower area

17 narrow area 18 lower area

19 radius of curvature

20 radius of curvature

21 radius of curvature

22 Arrow in the lateral direction 23 Arrow in the vertical direction

24 Distance between the trench walls

25 depth of the trench below the junctions

Claims

claims

1. Memory cell with a memory transistor which has a gate electrode (4) on an upper side of a semiconductor body (1) or a semiconductor layer, said gate electrode being in a trench formed in the semiconductor material of the semiconductor body or the semiconductor layer and at least transverse to a longitudinal direction has the same cross sections in sections, is arranged between a source region (2) and a drain region (3), the source region (2) and the drain region (3) in the semiconductor material by doping from the top to are formed into a respective junction (14) and the gate electrode is separated from the semiconductor material by a dielectric layer (9) which is designed as a storage medium, characterized in that the junctions (14) abut the walls of the trench in one area , in which the walls of the trench have a bend in each point in a cross section perpendicular to the longitudinal direction Mung radius that is at most two thirds as large as the distance (24) of the walls of the trench at the height of the junctions (14).

2. The memory cell as claimed in claim 1, in which the trench has lateral walls (6, 8) with respect to the longitudinal direction which are aligned in the vertical direction perpendicular to a plane of the upper side of the semiconductor body (1) or the semiconductor layer or at most by 10 ° of deviate from the vertical direction, between the side walls (6, 8) and a deepest point of the trench with respect to the plane of the upper side there are areas in which the walls of the trench have a radius of curvature at each point within a cross section perpendicular to the longitudinal direction, which is at most half the distance (24) between the walls of the trench at the level of the junctions (14), and butt the junctions (14) against the walls of the trench within these areas.

3. Memory cell with a memory transistor, which has a gate electrode (4) on an upper side of a semiconductor body (1) or a semiconductor layer, the gate electrode (4) being formed in a trench formed in the semiconductor material of the semiconductor body or the semiconductor layer, which trench is at least sectionally identical to a longitudinal direction Has cross sections, see between a source region (2) and a drain region (3) is arranged, the source region (2) and the drain region (3) in the semiconductor material by doping from the top to are formed into a junction (14) and the gate electrode is separated from the semiconductor material by a dielectric layer (9) which is designed as a storage medium, characterized in that the trench extends in a plane to the top of the semiconductor body ( 1) or the vertical vertical direction between the junctions (14) and one with respect to the plane of the semiconductor layer Upper side of the deepest point of the trench has measured depth (25) which is at most half as large as the distance (24) between the walls of the trench at the height of the junctions (14).

4. Storage cell according to claim 3, in which the junctions (14) abut the walls of the trench in an area in which the walls of the trench have a radius of curvature in each point in a cross section perpendicular to the longitudinal direction, which is at most two thirds is as large as the distance (24) 'between the walls of the trench at the level of the junctions (14).

5. Memory cell according to one of claims 1 to 4, wherein the bottom of the trench has the shape of a shell of a half cylinder or a cylinder sector, and the junctions (14) abut against this bottom.

6. Memory cell according to one of claims 1 to 5, wherein the distance (24) of the walls of the trench at the height of the junctions (14) is between 100 nm and 150 nm and the trench in one to a plane of the top of the semiconductor body (1) or the vertical vertical direction between the junctions (14) and a deepest point of the trench has a measured depth (25) of at least 30 nm and at most half of said distance (24).

7. Memory cell with a memory transistor, which has a gate electrode (4) on an upper side of a semiconductor body (1) or a semiconductor layer, the gate electrode (4) being formed in a trench formed in the semiconductor material of the semiconductor body or the semiconductor layer, the trench being at least partially identical to a longitudinal direction Has cross sections, is arranged between a source region (2) and a drain region (3), the source region (2) and the drain region (3) in the semiconductor material by doping the

Are formed up to a respective junction (14) and the gate electrode is separated from the semiconductor material by a dielectric layer (9) which is designed as a storage medium, characterized in that the junctions (14) on the walls of the Initiate trenching in an area in which the walls of the trench within a cross section perpendicular to the longitudinal direction have a radius of curvature which is at most 10% larger than a minimum value which is assumed by the radius of curvature on the trench wall.

8. Memory cell with a memory transistor, which has a gate electrode (4) on an upper side of a semiconductor body (1) or a semiconductor layer, which gate is formed in a trench formed in the semiconductor material of the semiconductor body or the semiconductor layer and is transverse to a longitudinal direction Has at least sections of the same cross section, is arranged between a source region (2) and a drain region (3), the source region (2) and the drain region (3) being formed in the semiconductor material by doping and the gate electrode is separated from the semiconductor material by a dielectric layer (9), which has a storage layer (11) between boundary layers (10, 12), characterized in that the depth of the trench with respect to an area in which one Deletion process charge carriers of the storage layer (11) are neutralized in such a way that during a programming process a component of an electrical field acting on the charge carriers is directed parallel to the tangent to a wall or to the bottom of the trench and perpendicular to the longitudinal direction is maximum.

9. The memory cell as claimed in claim 8, in which the dimensions are selected such that charge carriers penetrate a boundary layer (10) during programming and when deleting in a region which adjoins that region in the drain region (3) towards the top, in which the drain region (3) in semiconductor material merges with the opposite sign of the conductivity.