WO2003063167A2 - System and method for programming ono dual bit memory cells - Google Patents
System and method for programming ono dual bit memory cells Download PDFInfo
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- WO2003063167A2 WO2003063167A2 PCT/US2002/040775 US0240775W WO03063167A2 WO 2003063167 A2 WO2003063167 A2 WO 2003063167A2 US 0240775 W US0240775 W US 0240775W WO 03063167 A2 WO03063167 A2 WO 03063167A2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
- G11C16/3409—Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5657—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using ferroelectric storage elements
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
- G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
- G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
Definitions
- the present invention relates generally to memory systems and in particular to a system and method for programming and erasing sectors of bits in an electronic flash memory device having dual bit memory transistor cells using virtual ground architecture.
- Flash memory is a type of electronic memory media which can be rewritten and hold its content without power. Flash memory devices generally have life spans from 100K to 300K write cycles. Unlike dynamic random access memory (DRAM) and static random access memory (SRAM) memory chips, in which a single byte can be erased, flash memory is typically erased and written in fixed multi-bit blocks or sectors. Evolving out of electrically erasable read only memory (EEPROM) chip technology, which can be erased in place, flash memory is less expensive and more dense. This new category of EEPROMs has emerged as an important non- volatile memory which combines the advantages of EPROM density with EEPROM electrical erasability.
- DRAM dynamic random access memory
- SRAM static random access memory
- each cell typically includes a metal oxide semiconductor (MOS) transistor structure having a source, a drain, and a channel in a substrate or P-well, as well as a stacked gate structure overlying the channel.
- MOS metal oxide semiconductor
- the stacked gate may further include a thin gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the P-well.
- the stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate.
- the interpoly dielectric layer is often a multilayer insulator such as an oxide- nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer.
- ONO oxide- nitride-oxide
- a polysilicon control gate overlies the interpoly dielectric layer.
- the control gate is connected to a word line associated with a row of such cells to form sectors of such cells in a typical NOR configuration.
- the drain regions of the cells are connected together by a conductive bit line.
- the channel of the cell conducts current between the source and the drain in accordance with an electric field developed in the channel by the stacked gate structure.
- each drain terminal of the transistors within a single column is connected to the same bit line.
- each flash cell has its stacked gate terminal connected to a different word line, while all the flash cells in the array have their source terminals connected to a common source terminal.
- individual flash cells are addressed via the respective bit line and word line using peripheral decoder and control circuitry for programming (writing), reading or erasing functions.
- Such a single bit stacked gate flash memory cell is programmed by applying a voltage to the control gate and connecting the source to ground and the drain to a predetermined potential above the source.
- a resulting high electric field across the tunnel oxide leads to a phenomena called "Fowler-Nordheim" tunneling.
- electrons in the core cell channel region tunnel through the gate oxide into the floating gate and become trapped in the floating gate since the floating gate is surrounded by the interpoly dielectric and the tunnel oxide.
- the threshold voltage of the cell increases. This change in the threshold voltage (and thereby the channel conductance) of the cell created by the trapped- electrons is what causes the cell to be programmed.
- a voltage is applied to the source, and the control gate is held at a negative potential, while the drain is allowed to float. Under these conditions, an electric field is developed across the tunnel oxide between the floating gate and the source. The electrons that are trapped in the floating gate flow toward and cluster at the portion of the floating gate overlying the source region and are extracted from the floating gate and into the source region by way of Fowler-Nordheim tunneling through the tunnel oxide. As the electrons are removed from the floating gate, the cell is erased.
- an erase verification is performed to determine whether each cell in a block or set of such cells has been properly erased.
- Current single bit erase verification methodologies provide for verification of bit or cell erasure, and application of supplemental erase pulses to individual cells, which fail the initial verification. Thereafter, the erased status of the cell is again verified, and the process continues until the cell or bit is successfully erased or the cell is marked as unusable.
- dual bit flash memory cells have been introduced, which allow the storage of two bits of information in a single memory cell.
- the conventional programming and erase verification methods employed with single bit stacked gate architectures are not adequate for such dual bit devices.
- dual bit flash memory structures have been introduced that do not utilize a floating polysilicon gate, such as an ONO flash memory device that employs a polysilicon layer over the ONO layer for providing wordline connections.
- Conventional techniques do not address the characteristics associated with these types of devices. Therefore, there is an unmet need in the art for new and improved programming and erase methods and systems, which ensure proper programming and erasure of data bits in a dual bit memory virtual ground architecture, and which account for the structural characteristics thereof.
- a system and methodology for programming first and second bits of a memory array of dual bit memory cells at a substantially high delta VT.
- the substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time.
- programming of the first bit of the memory cell causes the second bit to program harder and faster due to the shorter channel length. Therefore, the present invention employs selected gate and drain voltages and programming pulse widths during programming of the first and second bit that assures a controlled first bit VT and slows down programming of the second bit. Furthermore, the selected programming parameters keep the programming times short without degrading charge loss.
- the present invention allows for efficient and thorough programming, erasure and verification, which minimizes data retention and over-erase issues similar to those caused in an ONO dual bit cell architecture.
- the invention provides significant advantages when employed in association with dual bit memory cells formed from an ONO architecture. However, it will be recognized that the invention finds utility in association with dual bit memory cell architectures generally, and that the invention is thus not limited to any particular dual bit cell usage implementation or configuration.
- charge associated with programming of a single bit in the dual bit memory cell is isolated, it causes the associated cell to program harder making it more difficult to erase. For example, residual charge can be accumulated into the central region of the cell, which cannot be erased by a normal erasure of the bit by itself.
- the system and methodology includes programming, verifying and erasure of both a normal bit and a complimentary bit of the cell, which are opposite sides of the same ONO transistor.
- the erasure includes applying a set of erase pulses to the normal bit and complimentary bit in a single dual bit cell.
- the set of erase pulses is comprised of a two sided erase pulse to both sides of the transistor followed by a single sided erase pulse to one side and a single sided erase pulse to the other side.
- a system and method for verify erasure of a memory array of dual bit flash memory cells.
- the system and method include preprogramming of bits in both normal column locations and complimentary column locations and then verify erasure of both bits in normal and complimentary bit column locations.
- the verify erasure requires that each bit address location pass the erase verify before moving to the next address.
- the erase verify can be performed on a I/O or word of bits such that the normal bits and complimentary bits of an I/O have to pass before moving on to the next I/O or word. If an address location is not below a maximum VT defining a blank state, a set of erase pulses is applied.
- the set of erase pulses include a two sided erase pulse to bits in normal and complimentary column locations for a specified duration (e.g., 10 ms) followed by a first single sided erase pulse to bits in one of the normal column locations and complimentary column locations for a specified duration (e.g., 1 ms) and a second single sided erase pulse to bits in the other of the normal column locations and complimentary column locations for a specified duration (e.g., 1 ms).
- the steps of verifying and erasure are repeated until each normal bit and complimentary bit in a sector are below the maximum VT defining a blank cell. The steps are then repeated for each sector.
- the bits are then evaluated to determine if the bits have been over-erased or fall below a minimum VT defining a blank cell.
- a soft program pulse is provided for the bits determined to have been over-erased.
- the soft program verify should include a low level source voltage to shutoff the leakage from other cells on the same column.
- a second or final routine of verify erasure is performed on both the bits in the normal column locations and the complimentary column locations to assure that the soft program pulse did not cause the bits to rise above the maximum VT defining a blank cell.
- Fig. 1 is a side cross-sectional view of an exemplary dual bit memory cell in which various aspects of the present invention may be implemented;
- Fig. 2 is a side cross sectional view of the dual bit memory cell illustrating the storing of a programmed charge in a normal region and a complimentary region of the dual bit memory cell
- Fig. 3 is a side cross sectional view of the dual bit memory cell illustrating non-uniform charge accumulation into a central region of the cell due to the over-programming of the second bit programmed of the dual bit memory cell;
- Fig. 4 is a side cross sectional view of the dual bit memory cell illustrating residual charge remaining in the central region of the cells near the array edges after erasure of the cell using only the one sided or two sided erase;
- Fig. 5 is a side cross sectional view of the dual bit memory cell illustrating removal of the residual charge remaining in the central region of the cell near the array edges after erasure of the dual bit memory cell in accordance with the present invention
- Fig. 6 illustrates a block schematic diagram of a system adapted to carry out various aspects of the invention
- Fig. 7 illustrates a partial top view of a 64K sector of an array of dual bit flash memory having 16 words of 16 bit memory in accordance with the present invention
- Fig. 8 illustrates a schematic view of a portion of a row of dual bit memory cells in accordance with the present invention
- Fig. 9 illustrates a graph of a first bit delta VT versus a second bit programming time in accordance with one aspect of the present invention
- Fig. 10 illustrates a graph of delta VT charge loss versus program and erase cycles in accordance with one aspect of the present invention
- Fig. 11 is a flow diagram illustrating a methodology for determining a substantially high delta VT and selected programming parameters for programming first and second bits of dual bit memory cells in accordance with an aspect of the invention
- Fig. 12 is a flow diagram illustrating a methodology for erase verifying of an array of dual bit memory cells in accordance with an aspect of the invention
- Fig. 13 is a flow diagram illustrating a methodology for soft programming of cells in the array of dual bit memory cells after the erasure verifying method of Fig. 12 in accordance with an aspect of the invention.
- Fig. 14 is a flow diagram illustrating a methodology for verify erasure of cells in the array of dual bit memory cells after the soft programming method of Fig. 13 in accordance with an aspect of the invention.
- the invention provides methodologies and a system for programming (writing), verifying (reading) and proper erasure of dual bit memory cells operating in a double or dual bit mode.
- the present invention may be used in conjunction with a chip erase or sector erase operation in a flash memory device.
- the present invention provides methodologies and a system for proper arrangement and maintenance of dual bit memory cells in an array operating in double bit mode.
- the memory cell 10 comprises a silicon nitride layer 16 sandwiched between a top silicon dioxide layer 14 and a bottom silicon dioxide layer 18 forming an ONO layer 30.
- a polysilicon layer 12 resides over the ONO layer 30 and provides a wordline connection to the memory cell 10.
- a first bitline 32 runs underneath the ONO layer 30 under a first region 4 and a second bitline 34 runs underneath the ONO layer 30 under a second region 6.
- the bitlines 32 and 34 are formed of a conductive portion 24 and an optional oxide portion 22. Boron core implants 20 are provided on both ends of each bitline 32 and 34 where the biltines meets the bottom silicon dioxide layer 18 or along the entire transistor.
- the boron core implants are more heavily doped than the P-type substrate and assist in control of the VT of the memory cell 10.
- the cell 10 resides on a P-type substrate 9 with the conductive portion 24 of the bitlines 32 and 34 being formed from an N + arsenic implant, such that a channel 8 is formed between across the P-type substrate.
- the memory cell 10 is comprised of a single transistor having interchangeable source and drain components formed from the N + arsenic implant portions 24 residing on the P-type substrate region 9 with a gate formed as part of a polysilicon wordline 12.
- first and second bitlines 32 and 34 are illustrated with respect to a conductive portion 24 and an optional oxide portion 22, it is appreciated that the bitlines can be formed from a conductive portion only.
- drawing of Fig. 1 illustrates gaps in the silicon nitride layer 16, it is to be appreciated that the silicon nitride layer 16 may be fabricated with out gaps as a single strip or layer.
- the silicon nitride layer 16 forms a charge trapping layer. Programming of the cell is accomplished by applying voltages to the drain and the gate while grounding the source. The voltages generate electrical fields along the channel causing electrons to accelerate and jump from the substrate layer 9 into the nitride which is known as hot electron injection. Since the electrons gain the most energy at the drain, these electrons become trapped and remain stored in the nitride layer near the drain.
- the cell 10 is generally uniform and the drain and source are interchangeable.
- a first charge 26 can be injected into the nitride 16 near a first end of the central region 5 and a second charge 28 can be injected into the nitride 16 near a second end of the central region 5. Therefore, if the charge does not move then there can be two bits per cell instead of one bit.
- the first charge 26 can be stored in the nitride layer 16 at the first end of the central region 5 and the second charge 28 can be stored at the second end of the central region 5 such that two bits can reside per memory cell 10.
- the dual bit memory cell 10 is generally symmetrical, thus the drain and the source are interchangeable.
- the first bitline 32 may serve as the drain terminal and the second bitline 34 as the source terminal when programming the left bit CO.
- the second bitline 34 may serve as the drain terminal and the first bitline 32 as the source terminal for programming the right bit Cl.
- Table 1 illustrates one particular set of voltage parameters for performing reading, programming and single sided erases of the dual bit memory cell 10 having the first bit CO and the second bit Cl. TABLE I
- dual bit memory cell architecture may be achieved according to one or more aspects of the present invention.
- the invention is applicable to memory devices wherein both bits in a dual bit cell are used for data or information storage.
- the inventors of the present invention have found that program and erasure of one bit (e.g., bit CO) in such a cell effects the programming and/or erasure of its associated bit (e.g., bit Cl).
- bit CO programming and/or erasure of its associated bit
- repeated programming of bit Cl of cell 10 may cause charge accumulation in bit CO and vice versa.
- repeated application of erase voltage pulses to bit Cl may cause over erasure of bit CO.
- These phenomena in the associated bit CO may in turn cause degradation with respect to the operation of the bits during normal operation (e.g.
- the invention addresses these problems with respect to dual bit memory cell technology by selectively programming, verifying, erasing, and re-verifying the individual bits of such memory cells in order to further ensure the proper erasure of the memory cell, for example, in a block or sector erase operation in a flash memory device.
- Fig. 2 illustrates the programming of both bits in the memory cell 10.
- one bit will be referred to as the normal bit (NB), while the associated bit will be referred to as the complimentary bit (CB).
- NB normal bit
- CB complimentary bit
- the junction nearest the cell being read is the ground terminal and the other side of the transistor is the drain. This is called reverse read.
- the drain is switched during programming and erase back to the nearest junction being the drain voltage instead of ground, which is used for read and verify operations.
- the dual bit memory cell 10 may be considered as three individual pieces acting together which are a complimentary bit region 40, a central region 42 and a normal bit region 44.
- the complimentary bit region 40 and the normal bit region 42 are near the drain/source junctions and the local VT can be modified during programming and erase operations.
- the central region 42 should be close to the natural VT generated in the fabrication process of the memory cell 10.
- the silicon nitride 16 from the ONO stack 30 is used to store a first charge 38 in the normal region 44 and a second charge 39 in the complimentary bit region 40. Since nitride is not a conductor, the charge added or removed during the program and erase operations should not redistribute itself but should remain where it is originally injected.
- each side of the transistor can have different charge and different VT almost independent of the other side.
- the natural or erase/blank VT of the CB and NB is approximately 1.2V and if the NB is programmed to a VT of approximately 3.8V, the CB should still be close to the blank state.
- both bits are programmed to a VT of 3.8V and then the NB is erased then the CB should be at approximately 3.8V and the NB at approximately 1.2V.
- part of the charge near the CB bitline should be covered by a drain depletion region since the source (ground) is always on the junction nearest the cell being verified. This is called reverse read operation since the verified cell's junction is grounded.
- the reverse read method covers up some of the charge near the other bits 's junction, any charge in the center of the channel will modify the effective VT of both the CB and the NB. As one of the areas becomes higher or lower in VT, the other regions can also be effected since they are all part of the same transistor. Fig.
- FIG 3 illustrates how programming of the NB with programming charge 38 into the NB region 44, after the CB has already been programmed with similar program parameters, can cause a buildup of charge 46 to escape partially into the central region 42.
- the effective shorter channel is due to the charge stored on the first bit near the junction, which is grounded during programming of the second bit.
- the second bit programs much faster than the first bit due to the shorter channel length caused by the first bit being charged. Since the second bit is programmed harder, the second bit erase is slower than the first bit.
- the present invention solves the problem with harder programming of the second bit by selecting programming parameters that allow for consistent programming and erasure of both bits and eliminating residual charge buildup during programming and erase cycles.
- the buildup of charge 46 may remain in the cell 10 and change the programming and erase characteristics of the cell 10 during each cycle.
- the location of the additional second bit programmed charge 46 changes the effective VT of the CB region 40 and the NB region 44 and causes the erase time to increase as the number of program and erase cycles increase.
- the combination of two sided and one sided erase steps provide a stable method to control the dual bit erase for the typical and outer most bits of the array populations.
- the outer most bits of the array population are usually different in channel length or width and erase much slower using the two sided only method, but typical cells erase best with the two sided erase pulses. Therefore, a one sided erase was added to maintain the erase speed of the outer most bits of the population.
- the process of monitoring and controlling the VT of the CB and NB occurs during erase (hereinafter referred to as "the doubled bit erase"). Therefore, in the present invention the programming parameters are selected to ensure that the bits are not over programmed due to residual charge and the erase is performed to ensure that the residual charge in the central region 42 is controlled.
- the VT distributions during program and erase both the erase and program times remain stable during program and erase cycling.
- Fig. 5 illustrates the memory cell 10 after a programming and erase cycle employing the double bit program and erase methodology of the present invention.
- a static random access memory (SRAM) module component may include the programs implemented by a micro-controller for use in controlling the operations of command logic and the memory system. These programs are typically loaded into an SRAM when a system is powered up.
- a bus can be used to send control commands from a processor to the command logic device and to exchange the data read from or written to the flash memory device with the command logic and a host processor.
- the embedded state machines of the flash device generate the command logic controls for detailed operations such as the various individual steps necessary for carrying out programming, reading and erasing operations. The state machine thus functions to reduce the overhead required of a processor (not depicted) typically used in association with a microchip containing the flash memory.
- a system 60 is provided for performing programming, verifying, soft programming and erasing of a memory array 68 employing the dual bit memory cells of the present invention.
- the memory array 68 is comprised of a plurality of 64K sectors 69.
- a sector of the flash memory array 69 includes a portion of the memory array 68 consisting of all the memory cells grouped together via all the wordlines that share the same sector address.
- the sector address is typically the n (e.g., six) most significant address bits of the address bit signals used to address one or more cells in the memory device where n is an integer.
- each 64K sector 69 can be comprised of 8 IOs where an 10 is a row of 4 cells or 4 dual bit memory cells having 4 normal bits and 4 complimentary. It is to be appreciated that the memory array 68 could be any number of different configurations, for example, 128K sectors comprised of 8 normal bits and 8 complimentary bits on 8 cells. In addition any number of sectors may be employed only limited by the size of the application and the size of the device employing the flash memory array 68.
- the system 60 includes an address decoder 62 connected to the flash memory array 68 for decoding IOs during various operations that are performed on the array 68 (e.g., programming, reading, verifying, erasing).
- the address decoder receives address bus information from a system controller (not shown) or the like.
- a command logic component 64 includes an internal state machine 65.
- the command logic component 64 is connected to the address memory array 68.
- the command logic and state machine receive commands or instructions from a databus connected to a system controller or the like.
- the commands or instructions invoke algorithms embedded in the command logic 64 and state machine 65.
- the algorithms perform the various methodologies of programming, reading, erasing, soft programming and verifying to be described herein.
- a voltage generator component 66 is also connected to the memory array 68 and the command logic 64 and state machine 65.
- the voltage generator component 66 is controlled by the command logic 64 and state machine 65.
- the voltage generator component 66 is operable to generate the necessary voltages for programming, reading, erasing, soft programming and verifying of the memory cells of the memory array 68.
- Fig. 7 illustrates a partial memory cell layout from a top or plan view of an example of a 64K block 70.
- the present example is illustrated with respect to a 64K block of 16 bit I/Os. It is to be appreciated that blocks may be 8 bit, 32 bit, 64 bit or more I/Os and are not limited to 64K (e.g., 128K, 256K, etc.).
- the 64K block 70 can be a sector or a portion of a sector. For example, one or more blocks with the contacts connecting common metal bitlines can form a sector.
- An ONO stack strip or layer 72 extends the length of the memory array and includes the block 70.
- the block 70 includes 16 I/Os or groups of columns 79.
- Each "word" or group of IO's is comprised of eight transistors or eight normal bits and eight complimentary bits.
- Each I/O includes a polysilicon wordline 74 for addressing the rows of cells.
- a plurality of bit lines run underneath the ONO stack strip layer 72 for enabling reading, writing and erasing of individual bits of the memory cells.
- Each bitline is connected to a first contact 78 and metal bitlines (not shown) at one end of a group of sixteen rows and a second contact 79 at the other end of the group.
- five bit lines are illustrated such that a bitline is tied to an end of every other transistor in a column and two select transitors are used to select between four bits of two transistors for reading, writing and erasing.
- FIG. 8 illustrates a schematic diagram of addressing of the first four dual bit memory cells in a row utilizing selection transistors and three bitlines for reading, writing and erasing bits.
- a first dual bit memory cell 82 includes a first bit CO and a second bit Cl
- a second dual bit memory cell 84 includes a first bit C2 and a second bit C3
- a third dual bit memory cell 86 includes a first bit C4 and a second bit C5
- a fourth dual bit memory cell 88 includes a first bit C6 and a second bit C7.
- the four dual bit memory cells could form an 8-bit word.
- a select gate 88 (SelO) and a select gate 90 (Sell) are provided to enable reading, writing and erasing of the bits CO, Cl of dual bit memory 82 and bits C2 and C3 of dual bit memory 84.
- a select gate 92 (Sel2) and a select gate 94 (Sel3) are provided to enable reading, writing and erasing of the bits C4, C5 of dual bit memory 86 and bits C6 and C7 of dual bit memory 88.
- a first switch 96 is connected to a first bitline BLO
- a second switch 98 is connected to a second bitline BL1
- a third switch 100 is connected to a third bitline BL2.
- the first, second and third switches couple the corresponding bitline between power (VDD) and ground (GND).
- VDD power
- GND ground
- Any bit of the dual bit memory cells can be read by providing different voltage configurations as illustrated in Table 2 below. In the example illustrated in Fig. 8, cell CO of dual bit memory cell 82 is being read.
- a higher delta VT is selected to compensate for post cycling charge loss.
- the first bit on a transistor programs at a much slower rate than the second bit. This is not the case at much lower program VT's.
- Fig. 9 illustrates a graph 110 of the second bit program time versus the first bit delta VT. Since the second bit appears to program harder and faster, the second bit determines the double bit erase time and the methods that can be used for erase on double bit. It is important to select conditions for programming that keep the VT of second bit programmed near the first bit or double bit erase can be very slow and the first bits programmed will over-erase.
- the drain voltage during programming of the first bit is selected to be about 9.25 to about 9.5 volts
- the drain voltage is selected to be about 5.0 to about 5.5 volts
- the pulse width of the program pulse is lowered to 0.5 microseconds ( ⁇ s).
- FIG. 10 illustrates a graph 120 of the charge loss in voltages versus the number of program and erase (PE) cycles.
- PE program and erase
- a methodology which may be implemented in accordance with the present invention, will be better appreciated with reference to the flow diagrams of Figs. 11 and 14. While, for purposes of simplicity of explanation, the methodologies of Figs. 11 and 14 are shown and described as executing serially, it is to be understood and appreciated that the present invention is not limited by the illustrated order, as some blocks may, in accordance with the present invention, occur in different orders and/or concurrently with other blocks from that shown and described herein. Moreover, not all illustrated blocks may be required to implement a methodology in accordance with the present invention.
- a key characteristic of the dual bit memory cells in the flash memory array of the present invention is that the charge loss during accelerated high temperature bake (75-250 DC) is a strong function of the number of program and erase cycles. This presents a possible reliability issue since the amount of charge loss increases with cycling up to 10,000 program and erase cycles.
- the single bit one-zero or zero-one state (which occurs when one sides of the transistor is programmed and the other is blank or un-programmed) of the transistor shows this problem with increased charge loss with larger number of cycles.
- the cell transistor behavior is not Gaussian.
- the cell transistors near larger wordline (poly gates in core) gaps losses more charge due to redistribution of the charge in the nitride and the locally enhanced trapped nitride charge near the larger poly gaps.
- the charge loss distribution was found to be repeatable from die to die for the same data pattern for all devices cycled over the same number of cycles.
- the program and erase conditions during cycling appear to have little impact on the relationship of the charge loss verses number of cycles for cycling over 1000 cycles.
- Fig. 11 illustrates one particular methodology for determining a delta VT voltage for a dual bit memory cell of a memory array operating in double bit mode in accordance with one aspect of the present invention.
- the method begins at step 200 were a normal blank or un-programmed VT of the memory cells in an array for a lot is determined.
- a number of program and erase cycles are performed on the array in the lot with various delta VT's for programming followed by a high temperature accelerated bake (100-250 DC).
- the charge loss of the cells is then determined, at step 210.
- the delta programming VT is increased based on the amount of charge loss.
- program and erase cycles are performed on another array in the lot using the selected programming parameters followed by an accelerated bake.
- the method determines if the results of the programming and erase cycles utilized in step 225 are acceptable. If the results of the programming and erase cycles are not acceptable (NO), the method returns to step 220. If the results of the programming and erase cycles are acceptable (YES), the command logic and state machine are programmed to program both bits of the dual bit memory cells utilizing the delta VT and the selected drain and gate potentials.
- extended cycling e.g. 100,000 program and erase (PE) cycles).
- Fig. 12 illustrates an erase methodology utilizing hot hole injection near the high voltage drain junction for both the normal and complimentary bit.
- the process of heavy programming on one bit causes a build up of residual charge that cannot be reached during the single sided or classical erase over acceptable voltage levels and/or acceptable erase times.
- the double bit erase method ensures control of both the normal and complimentary bit blank VT by a verification and modified method erase with each cycle. Therefore, the double bit erase methodology applies a series of erase conditions or sequences during each pulse to both the complimentary bit(s) and its associated normal bit(s) within a single cell(s).
- the first erase sequence of each pulse is a two sided or two drain erase pulse which brings both the source and drain of all cell transistors to high voltage (e.g., 4-7v).
- the complimentary bit and its associated normal bit is allowed to discharge. Then a single sided erase pulse is applied to the complimentary bit (e.g., complimentary drain goes to high voltage with the other transistor junction floated) followed by a single sided erase pulse to the normal bit (e.g., normal drain goes to high voltage with the other transistor junction floated).
- the order of the single sided pulses may be interchangeable regardless of the bit being verified. Significant improved results are achieved in the ONO double bit architecture when the two sided erase pulse is about 75%-95% of the total erase pulse time.
- Fig. 12 illustrates one particular methodology for performing a programming and erase of a flash memory array having dual bit memory cells in accordance with one aspect of the present invention.
- the method begins at step 300 where the erase routine is invoked.
- the erase routine may be invoked, for example, by a command from a controller to a state machine residing on a flash device. Both the bits in normal column locations and complimentary column locations are programmed to a delta VT at step 305.
- the method then advances to step 310 where an address counter pointing to the memory address of the array is set to the first address.
- step 315 the method performs a verify erase for an address location in a sector.
- the address location can be a memory address of a single bit location or a memory address of an I/O or word location of the sector. If the verify erase of the address location fails, the methodology proceeds to step 320.
- step 320 the methodology determines if the maximum pulse count has been reached. If the maximum pulse count has been reached (YES), the methodology proceeds to step 325 where a true failure of the device is indicated. If the maximum pulse count has not been reached (NO), the methodology advances to step 330 to apply erase pulses.
- the methodology applies a two sided erase pulse to both complimentary column and normal column locations of the sector for a duration of 8 to 12 ms (e.g., a 10ms pulse).
- a first single sided pulse is applied to the bits in the complimentary column location for a duration of 0.5 to 2 ms (e.g., 1 ms) followed by a second single sided pulse to bits in the normal column locations for a duration of 0.5 to 2 ms (e.g., 1 ms).
- the methodology then returns to step 315 for a verification of the erase of the current address location. If the verify erase of the current address locations passes, the methodology proceeds to step 335 to determine if the current bit or I/O address is the maximum address location.
- the address location of the address counter is incremented to the next address location at step 340.
- the method then returns to step 315 to perform a verification of the erase of the next address location. If the maximum address has been reached (YES) at step 335, the method advances to the soft program routine in Fig. 13 to ensure that the memory cells have not been over-erased.
- a methodology of soft programming is utilized to control the minimum (over-erased) normal and complimentary bit VT's of a blank state after the erase methodology of Fig. 12.
- Over-erased cells are any VT under the minimum value for a blank state and are not classical column leakage bits.
- the electrical fields used to erase the memory cells are very high and the local VT of the cells can be reduced below the natural state.
- the soft programming methodology of Fig. 13 is performed to eliminate over-erased cells and maintain stable programming times during cycling.
- Fig. 13 illustrates one particular methodology for performing soft programming of the flash memory array to ensure that the memory cells of the flash memory have not been over-erased.
- the soft programming routine begins.
- the soft programming routine may be invoked, for example, by a command from a controller to a state machine residing on a flash device.
- the soft program routine may be part of the overall erase routine and begin after completion of the methodology of Fig. 12.
- the method then advances to step 405 where the address counter is set to the first address.
- the methodology then proceeds to step 410.
- the method performs a verify of the soft program for the first address location. The verify should include a slight source voltage to repress any subthreshold leakage currents.
- step 415 determines if the maximum pulse count (e.g., 5 pulses) has been reached. If the maximum pulse count has been reached (YES), a true failure is indicated at step 425. If the maximum pulse count has not been reached (NO), the method advances to step 420 to apply a soft program pulse to the address location and returns to step 410 to verify if the address location has passed the soft programming verify condition. If the address location of the sector passes at step 410, the method proceeds to step 430 and determines if the maximum address of the sector has been reached.
- the maximum pulse count e.g., 5 pulses
- the address location of the address counter is moved to the next address location at step 435 and the method returns to step 410 to repeat the steps of soft programming verify of the next address location in the memory array. If the maximum address location has been reached (YES) at step 430, the method advances to the second erase block of Fig. 14.
- Fig. 14 illustrates one particular methodology for performing a second erase block of the flash memory array to ensure that the soft programming routine did not over program the memory cells in accordance with one aspect of the present invention.
- the method begins at step 500 at the second erase block.
- the second erase routine may be invoked, for example, by a command from a controller to a state machine residing on a flash device.
- the second erase routine may be part of the overall erase routine and begin after completion of the methodologies illustrated in Figs. 12 and 13.
- the method then advances to step 505 where the address counter is set to the first address location.
- the methodology then proceeds to step 510.
- the method performs a verify erase for an address location in a sector of the memory array.
- the address location can be a memory address of a single bit location or a memory address of an I/O or word location of the sector. If the verify erase of the address location fails, the methodology proceeds to step 520. At step 520, the methodology determines if the maximum pulse count has been reached. If the maximum pulse count has been reached (YES), the methodology proceeds to step 530 where a true failure of the device is indicated. If the maximum pulse count has not been reached (NO), the methodology advances to step 525to apply erase pulses.
- the methodology applies an erase pulse to both complimentary column locations and normal column locations of the sector for a duration of 8 to 12 ms (e.g., a 10ms pulse).
- a single sided pulse is applied to the bits in the complimentary column location for a duration of 0.5 to 2 ms (e.g., 1 ms) followed by a single sided pulse to bits in the normal column locations for a duration of 0.5 to 2 ms (e.g., 1 ms).
- the methodology then returns to step 510 for a verification of the erase of the current address location. If the verify erase of the current address locations passes, the methodology proceeds to step 535 to determine if the current bit or I/O address is the maximum address location.
- the address location of the address counter is incremented to the next address location at step 540.
- the method then returns to step 510 to perform a verification of the erase of the next address location. If the maximum address has been reached (YES) at step 535, the method is finished and the device returns to normal operation.
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2004-7011031A KR20040071322A (en) | 2002-01-16 | 2002-12-17 | Charge injection |
AU2002367512A AU2002367512A1 (en) | 2002-01-16 | 2002-12-17 | System and method for programming ono dual bit memory cells |
GB0417770A GB2400709B (en) | 2002-01-16 | 2002-12-17 | System and method for programming ONO dual bit memory cells |
DE10297641T DE10297641T5 (en) | 2002-01-16 | 2002-12-17 | charge injection |
JP2003562936A JP2005516330A (en) | 2002-01-16 | 2002-12-17 | Charge injection |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US10/050,483 | 2002-01-16 | ||
US10/050,483 US6567303B1 (en) | 2001-01-31 | 2002-01-16 | Charge injection |
Publications (2)
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WO2003063167A2 true WO2003063167A2 (en) | 2003-07-31 |
WO2003063167A3 WO2003063167A3 (en) | 2003-12-04 |
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PCT/US2002/040775 WO2003063167A2 (en) | 2002-01-16 | 2002-12-17 | System and method for programming ono dual bit memory cells |
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JP (1) | JP2005516330A (en) |
KR (1) | KR20040071322A (en) |
CN (1) | CN100433193C (en) |
AU (1) | AU2002367512A1 (en) |
DE (1) | DE10297641T5 (en) |
GB (1) | GB2400709B (en) |
TW (1) | TWI260639B (en) |
WO (1) | WO2003063167A2 (en) |
Cited By (6)
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WO2005038815A1 (en) * | 2003-10-02 | 2005-04-28 | Advanced Micro Devices, Inc. | Memory device and method using positive gate stress to recover overerased cell |
WO2007035278A2 (en) * | 2005-09-20 | 2007-03-29 | Spansion Llc | Multi - bit flash memory device having improved program rate |
US7307878B1 (en) | 2005-08-29 | 2007-12-11 | Spansion Llc | Flash memory device having improved program rate |
US7957204B1 (en) | 2005-09-20 | 2011-06-07 | Spansion Llc | Flash memory programming power reduction |
US8358543B1 (en) | 2005-09-20 | 2013-01-22 | Spansion Llc | Flash memory programming with data dependent control of source lines |
CN111863086A (en) * | 2019-04-29 | 2020-10-30 | 北京兆易创新科技股份有限公司 | Method and device for controlling programming performance |
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KR100666223B1 (en) * | 2006-02-22 | 2007-01-09 | 삼성전자주식회사 | Three-level nonvolatile semiconductor memory device for decreasing noise between memory cells and operating method therefor |
US7969788B2 (en) * | 2007-08-21 | 2011-06-28 | Micron Technology, Inc. | Charge loss compensation methods and apparatus |
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2002
- 2002-12-17 DE DE10297641T patent/DE10297641T5/en not_active Withdrawn
- 2002-12-17 CN CNB028272501A patent/CN100433193C/en not_active Expired - Lifetime
- 2002-12-17 AU AU2002367512A patent/AU2002367512A1/en not_active Abandoned
- 2002-12-17 WO PCT/US2002/040775 patent/WO2003063167A2/en active Application Filing
- 2002-12-17 JP JP2003562936A patent/JP2005516330A/en active Pending
- 2002-12-17 GB GB0417770A patent/GB2400709B/en not_active Expired - Fee Related
- 2002-12-17 KR KR10-2004-7011031A patent/KR20040071322A/en not_active Application Discontinuation
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2003
- 2003-01-08 TW TW092100296A patent/TWI260639B/en not_active IP Right Cessation
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WO2005038815A1 (en) * | 2003-10-02 | 2005-04-28 | Advanced Micro Devices, Inc. | Memory device and method using positive gate stress to recover overerased cell |
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JP2007507830A (en) * | 2003-10-02 | 2007-03-29 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Memory device using positive gate stress to recover over-erased cells and method therefor |
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WO2007035278A3 (en) * | 2005-09-20 | 2008-08-07 | Spansion Llc | Multi - bit flash memory device having improved program rate |
WO2007035278A2 (en) * | 2005-09-20 | 2007-03-29 | Spansion Llc | Multi - bit flash memory device having improved program rate |
US7957204B1 (en) | 2005-09-20 | 2011-06-07 | Spansion Llc | Flash memory programming power reduction |
US8358543B1 (en) | 2005-09-20 | 2013-01-22 | Spansion Llc | Flash memory programming with data dependent control of source lines |
US8462564B1 (en) | 2005-09-20 | 2013-06-11 | Spansion Llc | Flash memory programming power reduction |
CN111863086A (en) * | 2019-04-29 | 2020-10-30 | 北京兆易创新科技股份有限公司 | Method and device for controlling programming performance |
CN111863086B (en) * | 2019-04-29 | 2022-07-05 | 北京兆易创新科技股份有限公司 | Method and device for controlling programming performance |
Also Published As
Publication number | Publication date |
---|---|
GB0417770D0 (en) | 2004-09-15 |
CN100433193C (en) | 2008-11-12 |
TWI260639B (en) | 2006-08-21 |
TW200302486A (en) | 2003-08-01 |
KR20040071322A (en) | 2004-08-11 |
WO2003063167A3 (en) | 2003-12-04 |
DE10297641T5 (en) | 2005-01-05 |
CN1628358A (en) | 2005-06-15 |
JP2005516330A (en) | 2005-06-02 |
AU2002367512A1 (en) | 2003-09-02 |
GB2400709A (en) | 2004-10-20 |
GB2400709B (en) | 2005-12-28 |
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