WO2003063211A1 - Apparatus incorporating small-feature-size and large-feature-size components and method for making same - Google Patents

Apparatus incorporating small-feature-size and large-feature-size components and method for making same Download PDF

Info

Publication number
WO2003063211A1
WO2003063211A1 PCT/US2003/002115 US0302115W WO03063211A1 WO 2003063211 A1 WO2003063211 A1 WO 2003063211A1 US 0302115 W US0302115 W US 0302115W WO 03063211 A1 WO03063211 A1 WO 03063211A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductive medium
integrated circuit
substrate
scale component
conductive
Prior art date
Application number
PCT/US2003/002115
Other languages
French (fr)
Inventor
Glenn W. Gengel
Mark A. Hadley
Randolph W. Eisenhardt
Susan Swindlehurst
Paul S Drzaic
Frederick J. Vicentini
John Moon Hemingway
Original Assignee
Alien Technology Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alien Technology Corporation filed Critical Alien Technology Corporation
Priority to JP2003562978A priority Critical patent/JP2006504251A/en
Priority to KR10-2004-7011487A priority patent/KR20040105705A/en
Priority to EP03703985A priority patent/EP1468443A1/en
Priority to CA002474054A priority patent/CA2474054A1/en
Priority to AU2003205307A priority patent/AU2003205307B2/en
Publication of WO2003063211A1 publication Critical patent/WO2003063211A1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/0775Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
    • G06K19/07752Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna using an interposer
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00Nanotechnology for materials or surface science, e.g. nanocomposites
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/76Apparatus for connecting with build-up interconnects
    • H01L2224/7615Means for depositing
    • H01L2224/76151Means for direct writing
    • H01L2224/76155Jetting means, e.g. ink jet
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821Forming a build-up interconnect
    • H01L2224/82101Forming a build-up interconnect by additive methods, e.g. direct writing
    • H01L2224/82102Forming a build-up interconnect by additive methods, e.g. direct writing using jetting, e.g. ink jet
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/95053Bonding environment
    • H01L2224/95085Bonding environment being a liquid, e.g. for fluidic self-assembly
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/9512Aligning the plurality of semiconductor or solid-state bodies
    • H01L2224/95136Aligning the plurality of semiconductor or solid-state bodies involving guiding structures, e.g. shape matching, spacers or supporting members
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01061Promethium [Pm]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01077Iridium [Ir]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/10155Shape being other than a cuboid
    • H01L2924/10158Shape being other than a cuboid at the passive surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/15165Monolayer substrate

Definitions

  • the field of the invention generally relates to apparatuses having both large-feature-size components and small-feature-size components, and methods of making such apparatuses.
  • the invention more particularly relates to combination of VLSI integrated circuits and macro-scale components to form a single device.
  • VLSI provides many effective methods for creation of microscopic-scale and smaller components. Such miniaturization provides many advantages in terms of speed of operation, size of footprint, amount of necessary resources, and speed of manufacture for electronic devices.
  • this may involve use of packaging for the integrated circuit, conductors on a printed circuit board, a connector attached to the printed circuit board, and an antenna attached to the connector.
  • This approach is simple enough for a device having rigid packaging and flexible size constraints.
  • other applications may have more demanding requirements for size and materials cost.
  • Prior techniques can be generally divided into two types: deterministic methods or random methods.
  • Deterministic methods such as pick and place, use a human or robot arm to pick each element and place it into its corresponding location in a different substrate.
  • Pick and place methods place devices generally one at a time, and are generally not applicable to very small or numerous elements such as those needed for large arrays, such as an active matrix liquid crystal display. Random placement techniques are more effective and result in high yields if the elements to be placed have the right shape.
  • U.S. Patent No. 5,545,291 and U.S. Patent No. 5,904,545 describe methods that use random placement.
  • microstructures are assembled onto a different substrate through fluid transport.
  • This is sometimes referred to as fluidic self assembly (FSA).
  • FSA fluidic self assembly
  • various integrated circuits each containing a functional component, may be fabricated on one substrate and then separated from that substrate and assembled onto a separate substrate through the fluidic self assembly process.
  • the process involves combining the integrated circuits with a fluid, and dispensing the fluid and integrated circuits over the surface of a receiving substrate that has receptor regions (e.g., openings).
  • receptor regions e.g., openings
  • the remainder of the device can be assembled. Typically, this involves coating the substrate with a planarization layer to provide electrical insulation and physical retention for the integrated circuits.
  • the planarization layer creates a level surface on top of the substrate by filling in the portions of the receptor regions that are not filled by integrated circuits.
  • other elements including pixel electrodes and traces for example, may be installed.
  • the functional components of the device can be manufactured and tested separately from the rest of the device.
  • the present invention relates generally to the field of fabricating elements on a substrate.
  • the invention is an apparatus.
  • the apparatus includes a substrate having embedded therein an integrated circuit, the integrated circuit having a conductive pad.
  • the apparatus further includes a conductive medium attached to the conductive pad of the integrated circuit.
  • the apparatus also includes a large-scale component attached to the conductive medium, the large-scale component electrically coupled to the integrated circuit.
  • the invention is a method.
  • the method includes attaching a conductive medium to a substrate having embedded therein an integrated circuit such that the conductive medium is connected electrically to the integrated circuit.
  • the method also includes attaching a large-scale component to the conductive medium such that the large-scale component is electrically connected to the conductive medium.
  • the invention is an apparatus.
  • the apparatus includes an integrated circuit embedded within a substrate.
  • the apparatus also includes a thin-film dielectric layer formed over a portion of the integrated circuit and a portion of the substrate.
  • the apparatus further includes a conductive medium formed over a portion of the thin-film dielectric layer, the conductive medium having direct electrical connection with the integrated circuit.
  • the invention is a method.
  • the method includes forming a thin-film insulator on a portion of an integrated circuit and a portion of a substrate, the integrated circuit being embedded within the substrate.
  • the method also includes attaching a conductive medium to the thin-film insulator and to the integrated circuit, the conductive medium electrically connected to the integrated circuit.
  • the invention is an apparatus.
  • the apparatus includes a strap comprising a substrate with an embedded integrated circuit, the integrated circuit having a conductive pad, and a conductive medium attached to the conductive pad of the integrated circuit.
  • Figure 1 illustrates a side view of an embodiment of a strap.
  • Figure 2 illustrates a side view of an embodiment of the strap of Figure 1 as attached to a large-scale component.
  • Figure 3A illustrates a view of an embodiment of the apparatus of Figure 1 along the line A-A in the direction indicated.
  • Figure 3B illustrates a view of an embodiment of the apparatus of Figure 2 along the line B-B in the direction indicated.
  • Figure 4 illustrates an embodiment of an antenna.
  • Figure 5 illustrates an embodiment of a tape spool having adhered thereon straps including Nanoblock ICs.
  • Figure 6 illustrates an embodiment of a method of forming an apparatus including both small-feature-size and large-feature-size components.
  • Figure 7 illustrates an alternate embodiment of a method of forming an apparatus including both small-feature-size and large- feature-size components.
  • Figure 8 illustrates an alternate embodiment of a strap from a side view.
  • Figure 9 illustrates yet another alternate embodiment of a strap from a side view.
  • Figure 10 illustrates a side view of still another alternate embodiment of a strap.
  • Figure 11 illustrates another alternate embodiment of a method of forming an apparatus including both small-feature-size and large-feature-size components.
  • Figure 12A illustrates a top view of another embodiment of a substrate.
  • Figure 12B illustrates a side view of another embodiment of a substrate.
  • Figure 13 illustrates a side view of yet another embodiment of a substrate.
  • Figure 14 illustrates a side view of still another embodiment of a substrate.
  • the present invention relates generally to the field of fabricating elements on a substrate.
  • the invention is an apparatus.
  • the apparatus includes a strap, including a substrate with an embedded integrated circuit, , and a conductive medium attached to the conductive pad of the IC.
  • the apparatus also includes a large-scale component attached to the conductive medium, the large- scale component electrically coupled to the integrated circuit.
  • the invention is a method.
  • the method includes creating a strap by attaching a conductive medium to a substrate with an embedded integrated circuit such that the conductive medium is connected electrically to the integrated circuit.
  • the method also includes attaching a large-scale component to the conductive medium such that the large-scale component is electrically connected to the integrated circuit.
  • the conductive medium may be applied by screen, stencil, or ink jet printing, laminating, hot pressing, laser assisted chemical vapor deposition, physical vapor deposition, shadow masking, evaporating, extrusion coating, curtain coating, electroplating, or other additive techniques.
  • the conductive medium may be a fluid, silver ink, electrically conductive tape (thermoplastic or thermosetting polymer with conductive filler), electrically conductive paste (solder paste or conductive filler in a polymer matrix), solder, metal film, metal particles suspended in a carrier, conductive polymer, carbon-based conductor, or other thick-film material for example.
  • electrically conductive tape thermoplastic or thermosetting polymer with conductive filler
  • electrically conductive paste solder
  • metal film metal particles suspended in a carrier, conductive polymer, carbon-based conductor, or other thick-film material for example.
  • One exemplary conductive medium product is Acheson Colloids Electrodag 4795.
  • the invention is an apparatus.
  • the apparatus includes an integrated circuit embedded within a substrate.
  • the apparatus also includes a thin-film dielectric layer formed over a portion of the integrated circuit and a portion of the substrate.
  • the apparatus further includes a conductive medium formed over a portion of the thin-film dielectric layer, the conductive medium having direct electrical connection with the integrated circuit.
  • the apparatus is called a strap.
  • the invention is a method.
  • the method includes forming a thin-film insulator on a portion of an integrated circuit and a portion of a substrate, the integrated circuit embedded within the substrate.
  • the method also includes attaching a conductive medium to the thin-film insulator and to the integrated circuit, the conductive medium electrically connected to the integrated circuit.
  • the invention is an apparatus.
  • the apparatus includes a substrate having embedded therein an integrated circuit, the integrated circuit having a conductive pad.
  • the apparatus also includes a conductive medium attached to the conductive pad of the integrated circuit. This apparatus is referred to as a strap.
  • the invention is an apparatus.
  • the apparatus includes a strap having embedded therein a NanoblockTM IC (Nanoblock is a trademark of ALIEN Technology Corporation) and a conductor electrically coupled to the Nanoblock IC.
  • the Nanoblock IC may have been produced using conventional VLSI procedures and embedded using fluidic self-assembly (FSA) for example.
  • the substrate has attached thereon a conductive medium, allowing for electrical coupling between the Nanoblock IC and the conductor. Attached to the conductive medium is a substrate including an antenna, allowing for electrical coupling between the antenna and the Nanoblock IC.
  • the invention is a method.
  • the method includes attaching a conductive medium to a substrate having embedded therein a Nanoblock IC such that the conductive medium is coupled electrically to the Nanoblock IC, thereby forming a strap.
  • the method further includes attaching a large-scale component to the conductive medium such that the large-scale component is electrically connected or coupled to the conductive medium.
  • the method may further include fabricating the Nanoblock IC and performing FSA to embed the Nanoblock IC in the substrate.
  • the method may also involve a large-scale component which may be an antenna, a power source such as a battery or a button cell, or a thick- film cell printed on the strap or other substrate; a display electrode or a display; a logic device, or a sensor; among other examples.
  • the invention is an apparatus.
  • the apparatus includes a substrate having embedded therein a Nanoblock IC.
  • the substrate has attached thereto a conductive medium , allowing for electrical connection between the Nanoblock IC and the conductive medium.
  • Attached to the conductive medium is a substrate such as an antenna, allowing for electrical coupling between the antenna and the Nanoblock IC.
  • Figure 1 illustrates a side view of an embodiment of a strap, including a substrate with an embedded Nanoblock IC, planarizing layer.and conductive medium that contacts the pad on the NanoBlockTM IC.
  • the substrate 110 has an opening in it to contain the Nanoblock IC, and may be a flexible plastic substrate for example.
  • Nanoblock IC 120 is a Nanoblock IC formed via conventional VLSI.
  • the Nanoblock IC 120 may be embedded in the opening of the substrate 110 through FSA for example.
  • Nanoblock IC 120 may have a variety of functions or structures consistent with an integrated circuit.
  • Nanoblock IC 120 includes circuitry suitable for receiving radio signals from an external antenna and sending radio signals via the external antenna.
  • Nanoblock IC 120 may receive power from an external source via an external antenna, and use such power to send a radio signal via the external antenna.
  • Nanoblock IC 120 Formed above Nanoblock IC 120 is planarization layer 130, which may be formed through a conventional thin-film deposition, pattern and etch or other similar method, and which may be formed of an insulating material such as silicon dioxide for example.
  • planarization layer 130 Formed above planarization layer 130 are two conductors 140, which may be formed from a screen-printed electrically conductive paste for example, and which occupy two contact holes in the planarization layer 130.
  • the two conductors 140 attach to conductive pads of Nanoblock IC 120, and the two conductors 140 preferably do not directly connect to each other.
  • insulating layer 150 which may be formed through a thin-film or thick-film process for example, and may fill in space between the two conductors 140.
  • a conductor may in some instances connect to multiple pads of an integrated circuit by design. One example of such a situation is connecting all ground pads of an IC to a single conductor to achieve a common ground potential.
  • Nanoblock IC 120 may be formed with sufficiently large pads as to allow for direct connection between the two conductors and the Nanoblock IC, thereby avoiding the requirement of an intervening conductor.
  • such a structure will, in some embodiments, require direct (vertical) connection between any large-scale component and the Nanoblock IC through the conductive medium, as some conductive media have isotropic conductivity.
  • conductive media may include metal particles suspended in a carrier, conductive polymers, paste, silver ink, carbon-based conductors, solder, and other conductors.
  • the large-scale component discussed in this application may be an antenna, an electronic display or display electrode, a sensor, a power source such as a battery or solar cell, or another logic or memory device (such as but not limited to microprocessors, memory, and other logic devices), for example.
  • Figure 2 illustrates a side view of an embodiment of the strap of Figure 1 as attached to a large-scale component.
  • Conductors 270 each have a direct connection to one of the conductors 140, and potentially having a connection to one or more of insulation layer 150, planarization layer 130, and substrate 110. Attached to each of conductors 270 are one of conductors 280, which may be conductive pads of an antenna or conductive ends of an antenna for example. Thus, as illustrated, each of conductors 280 may be said to be coupled (electrically) to Nanoblock IC 120.
  • Substrate 290 is the material in which conductors 280 are embedded or to which conductors 280 are attached, and is preferably insulating in nature.
  • Space 260 is a space between the two conductors 270, which may be occupied by substrate 290 and/or insulator 150, or may be left as a void in the structure. It is important to note that in most applications, each of the two conductors 270 would not be connected directly to the other conductor 270, and a similar statement may be made with respect to the two conductors 280.
  • the conductive medium 270 is an electrically conductive tape (such as those available from the Sony Corporation, including Sony DP1122, for example).
  • the conductive tape may be isotropically or anisotropically conductive.
  • Such a conductive tape may be applied (adhered) by rolling the tape along a row of straps, applying sufficient pressure and possibly heat to adhere the tape to the straps, and then cutting the tape to separate the individual straps. This may be done in various manners.
  • the conductive medium 270 or 140 may be a conductive paste (such as those available from Ablestick, including Ablebond 8175A for example) which is put on the strap(s) through a screen printing process for example. Such a paste may be screened on to the straps at moderate resolutions relative to overall manufacturing tolerances, thereby allowing for useful connection to conductors 140.
  • a conductive medium 270 may also be a metal particles suspended in a carrier, a conductive polymer, a carbon- based conductor, a solder, or other conductive medium as will be appreciated by those skilled in the art.
  • Figure 3A illustrates a view of an embodiment of the strap of Figure 1 along the line A-A in the direction indicated.
  • the various overlaps between substrate 110, Nanoblock IC 120, planarization layer 130, conductors 140 and insulation layer 150 are all illustrated.
  • contact holes 315 in the planarization layer 130 are illustrated, thus making apparent the connection between conductors 140 and Nanoblock IC 120.
  • Figure 3B illustrates a view of an embodiment of the apparatus of Figure 2 along the line B-B in the direction indicated. Illustrated are overlaps between conductive layers 140, insulation layer 150, and conductors 280. For clarity, substrate 110 is also shown and substrate 290 is not shown.
  • FIG. 4 illustrates an embodiment of an antenna.
  • Each arm 455 is connected to antenna conductor pads 280.
  • arms 455 may simply form conductor pads 280, making them a single unitary structure of both arm and pad.
  • FIG. 5 illustrates an embodiment of a tape spool having adhered thereon straps including Nanoblock ICs.
  • Each strap 505 (of which one exemplary strap 505 is labeled) is adhered to a pair of electrically conductive tape strips 515.
  • the tape strips 515 form part of a larger spool which also includes through-holes 525 for purposes of spooling.
  • the tape strips 515 may be anisotropically conductive film (ACF), with the conductors of the straps 505 adhered to the ACF.
  • the conductive medium may be on a surface of the straps 505 opposite the surface adhered to by tape strips 515.
  • the tape spools of either embodiment may be formed with gaps between columns of straps allowing for slitting the tape through the gap to produce a single column of straps.
  • Figure 6 illustrates an embodiment of a method of forming an apparatus including both small-feature-size and large-feature-size components.
  • the integrated circuits are fabricated, such as through a conventional VLSI method.
  • the integrated circuits are embedded into substrate(s).
  • processing for purposes of forming planarization and insulation layers occurs, and a thick-film insulator is formed (one skilled in the art will appreciate that a thin-film insulation layer may also be formed).
  • conductive medium is applied to the substrate, such as by screen printing on paste or through other additive processes.
  • a large-scale component is attached to the conductive medium.
  • the tape spool of Figure 5 may be used to attach a large volume of straps to large-scale components by attaching each strap individually and then cutting the tape after attachment.
  • the conductive medium 640 is applied directly to the substrate embedded with ICs 620, omitting the insulating layer.
  • FIG. 7 illustrates an alternate embodiment of a method of forming an apparatus including both small-feature-size and large- feature-size components, with particular reference to fabrication of RF- ID tags using Nanoblock ICs.
  • the Nanoblock ICs are fabricated, such as through conventional VLSI methods.
  • the Nanoblock ICs are embedded in substrates through FSA.
  • any necessary post-FSA processing for purposes of forming planarization layers, and/or insulation layers occurs.
  • at least one thin-film dielectric is formed. As will be appreciated by one skilled in the art, the thin-film dielectric may not be necessary in alternative embodiments.
  • FIG. 740 a first conductive medium is applied to the substrates, such as in the form of a paste screened on to the substrates for example, thus creating straps.
  • electrically conductive tape is adhered to the conductive medium on the straps.
  • antennas are attached to the straps, such that the antennas are electrically coupled to the Nanoblock ICs of the corresponding straps.
  • Figure 8 illustrates an alternate embodiment of a strap from a side view. As will be appreciated, the embodiment of Figure 8 is similar to the embodiment of Figure 1. However, Figure 8 illustrates a substrate 810, having embedded therein (in an opening) an integrated circuit 820, with pads 825.
  • Each pad has deposited thereon through use of an additive process a conductive medium 840, such as a silver ink for example.
  • a conductive medium 840 such as a silver ink for example.
  • the conductive medium 840 is deposited such that it contacts one and only one pad 825 directly, thus allowing for separate conductors for each electrical contact of a circuit.
  • the size of the pads 825 may be greater than the size of similar pads on an integrated circuit such as Nanoblock IC 120 of Figure 1 , in that the pads 825 must interface directly with material (the conductive medium 840) having a much larger feature size than is common for VLSI devices.
  • the conductive medium 840 may be expected to have an as-deposited thickness of approximately 10-15 ⁇ ms and a final thickness on the order of 1 ⁇ m or less, and that pads 825 may have minimum dimensions on the order of 20 x 20 ⁇ ms or more.
  • Figure 9 illustrates yet another alternate embodiment of a strap from a side view.
  • Figure 9 illustrates a similar embodiment to that of Figure 8, which further incorporates an insulator.
  • Substrate 910 includes integrated circuit 920 embedded therein.
  • Pads 925 are a part of integrated circuit 920, and may be expected to have similar dimensions to pads 825.
  • Insulator (dielectric) 930 is deposited on integrated circuit 920 through use of a thick film process. Insulator 930 may be expected to have a thickness on the order of 10 (microns).
  • a conductive medium 940 which covers both an insulator 930 and some portion of a pad 925, that thereby allows for electrical contact between the integrated circuit 920 and a large scale component.
  • Conductive medium 940 may be expected to have similar characteristics to conductive medium 840.
  • Figure 10 illustrates a side view of still another alternate embodiment of a strap.
  • the insulator (1030) is a thin-film insulator patterned with vias through which the conductive medium (1040) may achieve contact with the pads (1025) of the integrated circuit (1020).
  • the vias require greater precision in patterning than do any of the insulators of conductor components of Figures 8 and 9.
  • the substrate 1010 may have insulator 1030 covering nearly its whole surface, rather than the limited areas of Figure 9. Additionally, it will be appreciated that the pads 1025 may be smaller on integrated circuit 1020 than similar pads of integrated circuits 920 and 820.
  • FIG. 11 illustrates another alternate embodiment of a method of forming an apparatus including both small-feature-size and large-feature-size components.
  • an integrated circuit is embedded within a supporting substrate.
  • a thin-film insulator is applied to the substrate.
  • the insulator is patterned such as through a photolithographic thin-film process, whereby portions of the insulator are removed to expose portions of the substrate or integrated circuit, such as bond or conductive pads. Further cleaning, such as washing away photoresist for example, may be involved as part of application, patterning, or even in a post-etch phase.
  • a photosensitive insulator or dielectric may be used, thereby eliminating the need for photoresist for example.
  • a conductive medium is applied to the substrate, coating all or part of the insulator.
  • the conductive medium is processed (such as by heat curing, for example) as necessary to form a proper conductor.
  • curing of silver ink is known in the art to be possible at 90-100°C for some formulations with a reasonable cure time for various manufacturing processes. It will be appreciated that cure times do vary, and that those skilled in the art may adapt cure processes to the needs of a surrounding manufacturing process and the devices to be produced.
  • the large-scale component is attached to the conductive medium, thereby achieving electrical coupling with the integrated circuit. Also note that the final processing of the conductive medium of block 1160 may be performed after the large scale component is attached at block 1170.
  • a large-feature-size component may be incorporated as part of the strap, such as an embedded conductor acting as an antenna, or may be formed on the strap as illustrated in Figures 12a and 12b. Printing or otherwise using additive processing technology to form an antenna 1240 of the conductive medium on the strap is one option.
  • Nanoblock IC with such large-feature-size components on the strap may be accomplished through use of conductive medium 1440, allowing for electrical coupling between the large-feature-size components 1460 and the small-feature-size (Nanoblock IC for example) components 1420, as in Figure 14.
  • a conductive medium 1340 may be used to interconnect two or more small-feature- size components embedded in a single substrate, such as two Nanoblock ICs for example, as illustrated in Figure 13.
  • FIG. 12A illustrates a top view of another embodiment of a substrate.
  • Substrate 1210 may be a substrate such as those discussed previously, including a flexible or rigid material.
  • Integrated circuit (IC) 1220 is embedded in an opening in substrate 1210.
  • Insulator 1230 is a layer of insulating material (or a dielectric layer) on top of both substrate 1210 and IC 1220 and may have planarizing properties.
  • Contact holes 1215 are holes in the insulator 1230 above contact pads of IC 1220, allowing for physical contact and electrical connection between IC 1220 and conductive media 1240.
  • Layer 1250 is another insulator or dielectric above portions of conductive media 1240, insulator 1220 and substrate 1210, and above all of IC 1220.
  • conductive media 1240 is formed into two arms of an antenna, such as may be useful for radio frequency applications.
  • batteries, sensors, power supplies, button cells, and displays and display electrodes may also be formed through use of conductive media and other materials.
  • Figure 12B illustrates a side view of another embodiment of a substrate.
  • conductive media 1240 occupies the contact holes 1215 of Figure 12A to contact directly with IC 1220.
  • the segments illustrated with respect to conductive media 1240 correspond to the various segments of the antenna as it traces its path along the surface of the insulator 1230.
  • Figure 13 illustrates a side view of yet another embodiment of a substrate.
  • Substrate 1310 includes first integrated circuit (IC) 1320 and second integrated circuit (IC) 1325. Insulator 1330 is formed above IC 1320, IC 1325 and substrate 1310.
  • Conductive media 1340 is formed above insulator 1330, and contacts both IC 1320 and IC 1325. One portion of conductive media 1340 forms an electrical connection between IC 1320 and IC 1325, thereby electrically coupling IC 1320 to IC 1325. Above both IC 1320 and IC 1325 are formed insulator layers 1350.
  • FIG. 14 illustrates a side view of still another embodiment of a substrate.
  • Substrate 1410 has embedded in an opening therein an IC 1420.
  • IC 1420 Formed above substrate 1410 and IC 1420 is insulator 1430.
  • conductive media 1440 Formed above insulator 1430 and connected to IC 1420 is conductive media 1440, a portion of which is connected to sensor 1460, thereby electrically coupling IC 1420 to sensor 1460.
  • insulator 1450 Formed above a portion of conductive media 1440 and insulator 1430 is insulator 1450, which may or may not be of the same material as insulator 1430.

Abstract

The present invention relates to the field of fabricating elements on a substrate. In one embodiment, the invention is an apparatus. The apparatus includes a strap having embedded therein an integrated circuit, the integrated circuit having a conductive pad. The apparatus also includes a conductive medium attached to the conductive pad of the integrated circuit. In an alternate embodiment, the invention is a method. The method includes attaching a conductive medium to a strap having embedded therein an integrated circuit such that the conductive medium is connected electrically to the integrated circuit. The method also includes attaching a large-scale component to the conductive medium such that the large-scale component is electrically connected to the conductive medium. The apparatus can also include a thin-film dielectric layer formed over a portion of the integrated circuit and a portion of the substrate.

Description

APPARATUS INCORPORATING SMALL-FEATURE-SIZE AND LARGE- FEATURE-SIZE COMPONENTS AND METHOD FOR MAKING SAME
BACKGROUND OF THE INVENTION
Field of the Invention
[001] The field of the invention generally relates to apparatuses having both large-feature-size components and small-feature-size components, and methods of making such apparatuses. The invention more particularly relates to combination of VLSI integrated circuits and macro-scale components to form a single device.
Description of the Related Art
[002] VLSI provides many effective methods for creation of microscopic-scale and smaller components. Such miniaturization provides many advantages in terms of speed of operation, size of footprint, amount of necessary resources, and speed of manufacture for electronic devices.
[003] Unfortunately, some components of electronic devices are not well-suited to formation through well-known VLSI processes. These components often are necessarily very large (macroscopic- scale) relative to devices or components of devices formed through VLSI. One such component is an antenna, which may need to have a characteristic length to allow for adequate transmission on a preferred frequency, and for which the characteristic length in question may be appropriately measured in centimeters or meters for example. Formation of a conductor for use as an antenna using VLSI tends to waste time and material resources, as a 30 cm conductor (for example) can easily be formed through less expensive processes. [004] Thus, the problem then becomes a matter of combining a large-scale component such as an antenna with a small-scale component such as an integrated circuit. For a conventional radio, this may involve use of packaging for the integrated circuit, conductors on a printed circuit board, a connector attached to the printed circuit board, and an antenna attached to the connector. This approach is simple enough for a device having rigid packaging and flexible size constraints. However, other applications may have more demanding requirements for size and materials cost.
[005] In particular, it may be useful to have a small radio- transmitter with flexible materials allowing for bending and other abusive actions without degradation in functionality. Similarly, such a small radio-transmitter may need to be producible rapidly in quantities of millions or billions, thus requiring ease of assembly and relatively inexpensive materials on a per-unit basis. Using a printed-circuit board approach for such a radio-transmitter will likely not succeed. Moreover, avoiding such time (and/or space) consuming processing operations as thermal cure may be advantageous.
[006] It is possible to separately produce elements, such as integrated circuits and then place them where desired on a different and perhaps larger substrate. Prior techniques can be generally divided into two types: deterministic methods or random methods. Deterministic methods, such as pick and place, use a human or robot arm to pick each element and place it into its corresponding location in a different substrate. Pick and place methods place devices generally one at a time, and are generally not applicable to very small or numerous elements such as those needed for large arrays, such as an active matrix liquid crystal display. Random placement techniques are more effective and result in high yields if the elements to be placed have the right shape. U.S. Patent No. 5,545,291 and U.S. Patent No. 5,904,545 describe methods that use random placement. In this method, microstructures are assembled onto a different substrate through fluid transport. This is sometimes referred to as fluidic self assembly (FSA). Using this technique, various integrated circuits, each containing a functional component, may be fabricated on one substrate and then separated from that substrate and assembled onto a separate substrate through the fluidic self assembly process. The process involves combining the integrated circuits with a fluid, and dispensing the fluid and integrated circuits over the surface of a receiving substrate that has receptor regions (e.g., openings). The integrated circuits flow in the fluid over the surface and randomly align onto receptor regions, thereby becoming embedded in the substrate.
[007] Once the integrated circuits have been deposited into the receptor regions, the remainder of the device can be assembled. Typically, this involves coating the substrate with a planarization layer to provide electrical insulation and physical retention for the integrated circuits. The planarization layer creates a level surface on top of the substrate by filling in the portions of the receptor regions that are not filled by integrated circuits. After the planarization layer has been deposited, other elements, including pixel electrodes and traces for example, may be installed.
[008] Using FSA, the functional components of the device can be manufactured and tested separately from the rest of the device.
SUMMARY OF THE INVENTION
[009] The present invention relates generally to the field of fabricating elements on a substrate. In one embodiment, the invention is an apparatus. The apparatus includes a substrate having embedded therein an integrated circuit, the integrated circuit having a conductive pad. The apparatus further includes a conductive medium attached to the conductive pad of the integrated circuit. The apparatus also includes a large-scale component attached to the conductive medium, the large-scale component electrically coupled to the integrated circuit.
[010] In an alternate embodiment, the invention is a method. The method includes attaching a conductive medium to a substrate having embedded therein an integrated circuit such that the conductive medium is connected electrically to the integrated circuit. The method also includes attaching a large-scale component to the conductive medium such that the large-scale component is electrically connected to the conductive medium.
[011] In another alternate embodiment, the invention is an apparatus. The apparatus includes an integrated circuit embedded within a substrate. The apparatus also includes a thin-film dielectric layer formed over a portion of the integrated circuit and a portion of the substrate. The apparatus further includes a conductive medium formed over a portion of the thin-film dielectric layer, the conductive medium having direct electrical connection with the integrated circuit.
[012] In yet another alternate embodiment, the invention is a method. The method includes forming a thin-film insulator on a portion of an integrated circuit and a portion of a substrate, the integrated circuit being embedded within the substrate. The method also includes attaching a conductive medium to the thin-film insulator and to the integrated circuit, the conductive medium electrically connected to the integrated circuit.
[013] In still another alternate embodiment, the invention is an apparatus. The apparatus includes a strap comprising a substrate with an embedded integrated circuit, the integrated circuit having a conductive pad, and a conductive medium attached to the conductive pad of the integrated circuit.
BRIEF DESCRIPTION OF THE DRAWINGS
[014] The present invention is illustrated by way of example and not limitation in the accompanying figures.
[015] Figure 1 illustrates a side view of an embodiment of a strap.
[016] Figure 2 illustrates a side view of an embodiment of the strap of Figure 1 as attached to a large-scale component.
[017] Figure 3A illustrates a view of an embodiment of the apparatus of Figure 1 along the line A-A in the direction indicated.
[018] Figure 3B illustrates a view of an embodiment of the apparatus of Figure 2 along the line B-B in the direction indicated.
[019] Figure 4 illustrates an embodiment of an antenna.
[020] Figure 5 illustrates an embodiment of a tape spool having adhered thereon straps including Nanoblock ICs.
[021] Figure 6 illustrates an embodiment of a method of forming an apparatus including both small-feature-size and large-feature-size components.
[022] Figure 7 illustrates an alternate embodiment of a method of forming an apparatus including both small-feature-size and large- feature-size components.
[023] Figure 8 illustrates an alternate embodiment of a strap from a side view.
[024] Figure 9 illustrates yet another alternate embodiment of a strap from a side view. [025] Figure 10 illustrates a side view of still another alternate embodiment of a strap.
[026] Figure 11 illustrates another alternate embodiment of a method of forming an apparatus including both small-feature-size and large-feature-size components.
[027] Figure 12A illustrates a top view of another embodiment of a substrate.
[028] Figure 12B illustrates a side view of another embodiment of a substrate.
[029] Figure 13 illustrates a side view of yet another embodiment of a substrate.
[030] Figure 14 illustrates a side view of still another embodiment of a substrate.
DETAILED DESCRIPTION
[031] An apparatus incorporating small-feature-size and large- feature-size components and method for making same is described. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent to one skilled in the art, however, that the invention can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form to avoid obscuring the invention.
[032] Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.
[033] The present invention relates generally to the field of fabricating elements on a substrate. In one embodiment, the invention is an apparatus. The apparatus includes a strap, including a substrate with an embedded integrated circuit, , and a conductive medium attached to the conductive pad of the IC. The apparatus also includes a large-scale component attached to the conductive medium, the large- scale component electrically coupled to the integrated circuit.
[034] In an alternate embodiment, the invention is a method. The method includes creating a strap by attaching a conductive medium to a substrate with an embedded integrated circuit such that the conductive medium is connected electrically to the integrated circuit. The method also includes attaching a large-scale component to the conductive medium such that the large-scale component is electrically connected to the integrated circuit. The conductive medium may be applied by screen, stencil, or ink jet printing, laminating, hot pressing, laser assisted chemical vapor deposition, physical vapor deposition, shadow masking, evaporating, extrusion coating, curtain coating, electroplating, or other additive techniques. The conductive medium may be a fluid, silver ink, electrically conductive tape (thermoplastic or thermosetting polymer with conductive filler), electrically conductive paste (solder paste or conductive filler in a polymer matrix), solder, metal film, metal particles suspended in a carrier, conductive polymer, carbon-based conductor, or other thick-film material for example. One exemplary conductive medium product is Acheson Colloids Electrodag 4795.
[035] In another alternate embodiment, the invention is an apparatus. The apparatus includes an integrated circuit embedded within a substrate. The apparatus also includes a thin-film dielectric layer formed over a portion of the integrated circuit and a portion of the substrate. The apparatus further includes a conductive medium formed over a portion of the thin-film dielectric layer, the conductive medium having direct electrical connection with the integrated circuit. The apparatus is called a strap.
[036] In yet another alternate embodiment, the invention is a method. The method includes forming a thin-film insulator on a portion of an integrated circuit and a portion of a substrate, the integrated circuit embedded within the substrate. The method also includes attaching a conductive medium to the thin-film insulator and to the integrated circuit, the conductive medium electrically connected to the integrated circuit.
[037] In still another alternate embodiment, the invention is an apparatus. The apparatus includes a substrate having embedded therein an integrated circuit, the integrated circuit having a conductive pad. The apparatus also includes a conductive medium attached to the conductive pad of the integrated circuit. This apparatus is referred to as a strap.
[038] In yet another alternate embodiment, the invention is an apparatus. The apparatus includes a strap having embedded therein a Nanoblock™ IC (Nanoblock is a trademark of ALIEN Technology Corporation) and a conductor electrically coupled to the Nanoblock IC. The Nanoblock IC may have been produced using conventional VLSI procedures and embedded using fluidic self-assembly (FSA) for example. The substrate has attached thereon a conductive medium, allowing for electrical coupling between the Nanoblock IC and the conductor. Attached to the conductive medium is a substrate including an antenna, allowing for electrical coupling between the antenna and the Nanoblock IC. [039] In still another alternate embodiment, the invention is a method. The method includes attaching a conductive medium to a substrate having embedded therein a Nanoblock IC such that the conductive medium is coupled electrically to the Nanoblock IC, thereby forming a strap. The method further includes attaching a large-scale component to the conductive medium such that the large-scale component is electrically connected or coupled to the conductive medium. The method may further include fabricating the Nanoblock IC and performing FSA to embed the Nanoblock IC in the substrate. The method may also involve a large-scale component which may be an antenna, a power source such as a battery or a button cell, or a thick- film cell printed on the strap or other substrate; a display electrode or a display; a logic device, or a sensor; among other examples.
[040] In a further alternate embodiment, the invention is an apparatus. The apparatus includes a substrate having embedded therein a Nanoblock IC. The substrate has attached thereto a conductive medium , allowing for electrical connection between the Nanoblock IC and the conductive medium. Attached to the conductive medium is a substrate such as an antenna, allowing for electrical coupling between the antenna and the Nanoblock IC.
[041] For purposes of the discussion in this document, both the previous statements and following statements, a distinction must be made between thin film and thick film processes. Thin films are applied through use of vacuum or low-pressure processes. Thick films are applied using non-vacuum processes, typically at or near atmospheric pressure. One having skill in the art will appreciate that exact magnitudes of ambient pressure for low-pressure of vacuum as opposed to atmospheric pressure may be difficult to state. However, one having skill in the art will also appreciate that the differences between low-pressure and atmospheric pressure are relatively large compared to atmospheric pressure.
[042] Figure 1 illustrates a side view of an embodiment of a strap, including a substrate with an embedded Nanoblock IC, planarizing layer.and conductive medium that contacts the pad on the NanoBlock™ IC. The substrate 110 has an opening in it to contain the Nanoblock IC, and may be a flexible plastic substrate for example. Nanoblock IC 120 is a Nanoblock IC formed via conventional VLSI. The Nanoblock IC 120 may be embedded in the opening of the substrate 110 through FSA for example. Nanoblock IC 120 may have a variety of functions or structures consistent with an integrated circuit. In one embodiment, Nanoblock IC 120 includes circuitry suitable for receiving radio signals from an external antenna and sending radio signals via the external antenna. Moreover, in one embodiment, Nanoblock IC 120 may receive power from an external source via an external antenna, and use such power to send a radio signal via the external antenna.
[043] Formed above Nanoblock IC 120 is planarization layer 130, which may be formed through a conventional thin-film deposition, pattern and etch or other similar method, and which may be formed of an insulating material such as silicon dioxide for example. Formed above planarization layer 130 are two conductors 140, which may be formed from a screen-printed electrically conductive paste for example, and which occupy two contact holes in the planarization layer 130. Preferably, the two conductors 140 attach to conductive pads of Nanoblock IC 120, and the two conductors 140 preferably do not directly connect to each other. Formed above conductors 140 is insulating layer 150 which may be formed through a thin-film or thick-film process for example, and may fill in space between the two conductors 140. As will be appreciated, a conductor may in some instances connect to multiple pads of an integrated circuit by design. One example of such a situation is connecting all ground pads of an IC to a single conductor to achieve a common ground potential.
[044] As will be appreciated, Nanoblock IC 120 may be formed with sufficiently large pads as to allow for direct connection between the two conductors and the Nanoblock IC, thereby avoiding the requirement of an intervening conductor. As will also be appreciated, such a structure will, in some embodiments, require direct (vertical) connection between any large-scale component and the Nanoblock IC through the conductive medium, as some conductive media have isotropic conductivity. Furthermore, note that conductive media may include metal particles suspended in a carrier, conductive polymers, paste, silver ink, carbon-based conductors, solder, and other conductors. Also, note that the large-scale component discussed in this application may be an antenna, an electronic display or display electrode, a sensor, a power source such as a battery or solar cell, or another logic or memory device (such as but not limited to microprocessors, memory, and other logic devices), for example.
[045] Figure 2 illustrates a side view of an embodiment of the strap of Figure 1 as attached to a large-scale component. Conductors 270 each have a direct connection to one of the conductors 140, and potentially having a connection to one or more of insulation layer 150, planarization layer 130, and substrate 110. Attached to each of conductors 270 are one of conductors 280, which may be conductive pads of an antenna or conductive ends of an antenna for example. Thus, as illustrated, each of conductors 280 may be said to be coupled (electrically) to Nanoblock IC 120. Substrate 290 is the material in which conductors 280 are embedded or to which conductors 280 are attached, and is preferably insulating in nature. [046] Space 260 is a space between the two conductors 270, which may be occupied by substrate 290 and/or insulator 150, or may be left as a void in the structure. It is important to note that in most applications, each of the two conductors 270 would not be connected directly to the other conductor 270, and a similar statement may be made with respect to the two conductors 280.
[047] In one embodiment, the conductive medium 270 is an electrically conductive tape (such as those available from the Sony Corporation, including Sony DP1122, for example). Moreover, the conductive tape may be isotropically or anisotropically conductive. Such a conductive tape may be applied (adhered) by rolling the tape along a row of straps, applying sufficient pressure and possibly heat to adhere the tape to the straps, and then cutting the tape to separate the individual straps. This may be done in various manners.
[048] Alternatively, the conductive medium 270 or 140 may be a conductive paste (such as those available from Ablestick, including Ablebond 8175A for example) which is put on the strap(s) through a screen printing process for example. Such a paste may be screened on to the straps at moderate resolutions relative to overall manufacturing tolerances, thereby allowing for useful connection to conductors 140. Furthermore, a conductive medium 270 may also be a metal particles suspended in a carrier, a conductive polymer, a carbon- based conductor, a solder, or other conductive medium as will be appreciated by those skilled in the art.
[049] Figure 3A illustrates a view of an embodiment of the strap of Figure 1 along the line A-A in the direction indicated. The various overlaps between substrate 110, Nanoblock IC 120, planarization layer 130, conductors 140 and insulation layer 150 are all illustrated. Moreover, contact holes 315 in the planarization layer 130 are illustrated, thus making apparent the connection between conductors 140 and Nanoblock IC 120.
[050] Figure 3B illustrates a view of an embodiment of the apparatus of Figure 2 along the line B-B in the direction indicated. Illustrated are overlaps between conductive layers 140, insulation layer 150, and conductors 280. For clarity, substrate 110 is also shown and substrate 290 is not shown.
[051] Figure 4 illustrates an embodiment of an antenna. Each arm 455 is connected to antenna conductor pads 280. Note that in an alternate embodiment, arms 455 may simply form conductor pads 280, making them a single unitary structure of both arm and pad.
[052] Figure 5 illustrates an embodiment of a tape spool having adhered thereon straps including Nanoblock ICs. Each strap 505 (of which one exemplary strap 505 is labeled) is adhered to a pair of electrically conductive tape strips 515. The tape strips 515 form part of a larger spool which also includes through-holes 525 for purposes of spooling. In one embodiment, the tape strips 515 may be anisotropically conductive film (ACF), with the conductors of the straps 505 adhered to the ACF. In an alternate embodiment, the conductive medium may be on a surface of the straps 505 opposite the surface adhered to by tape strips 515. Moreover, the tape spools of either embodiment may be formed with gaps between columns of straps allowing for slitting the tape through the gap to produce a single column of straps.
[053] Figure 6 illustrates an embodiment of a method of forming an apparatus including both small-feature-size and large-feature-size components. At block 610, the integrated circuits are fabricated, such as through a conventional VLSI method. At block 620, the integrated circuits are embedded into substrate(s). At block 630, processing for purposes of forming planarization and insulation layers occurs, and a thick-film insulator is formed (one skilled in the art will appreciate that a thin-film insulation layer may also be formed). At block 640, conductive medium is applied to the substrate, such as by screen printing on paste or through other additive processes. At block 650, a large-scale component is attached to the conductive medium. Note that in one embodiment, the tape spool of Figure 5 may be used to attach a large volume of straps to large-scale components by attaching each strap individually and then cutting the tape after attachment. In an alternate embodiment, the conductive medium 640 is applied directly to the substrate embedded with ICs 620, omitting the insulating layer.
[054] Figure 7 illustrates an alternate embodiment of a method of forming an apparatus including both small-feature-size and large- feature-size components, with particular reference to fabrication of RF- ID tags using Nanoblock ICs. At block 710, the Nanoblock ICs are fabricated, such as through conventional VLSI methods. At block 720, the Nanoblock ICs are embedded in substrates through FSA. At block 730, any necessary post-FSA processing for purposes of forming planarization layers, and/or insulation layers occurs. In particular, at least one thin-film dielectric is formed. As will be appreciated by one skilled in the art, the thin-film dielectric may not be necessary in alternative embodiments. At block 740, a first conductive medium is applied to the substrates, such as in the form of a paste screened on to the substrates for example, thus creating straps. At block 750, electrically conductive tape is adhered to the conductive medium on the straps. At block 760, antennas are attached to the straps, such that the antennas are electrically coupled to the Nanoblock ICs of the corresponding straps. [055] Figure 8 illustrates an alternate embodiment of a strap from a side view. As will be appreciated, the embodiment of Figure 8 is similar to the embodiment of Figure 1. However, Figure 8 illustrates a substrate 810, having embedded therein (in an opening) an integrated circuit 820, with pads 825. Each pad has deposited thereon through use of an additive process a conductive medium 840, such as a silver ink for example. Usually, but not always, the conductive medium 840 is deposited such that it contacts one and only one pad 825 directly, thus allowing for separate conductors for each electrical contact of a circuit.
[056] Moreover, it will be appreciated that the size of the pads 825 may be greater than the size of similar pads on an integrated circuit such as Nanoblock IC 120 of Figure 1 , in that the pads 825 must interface directly with material (the conductive medium 840) having a much larger feature size than is common for VLSI devices. Note that in one embodiment, the conductive medium 840 may be expected to have an as-deposited thickness of approximately 10-15 μms and a final thickness on the order of 1 μm or less, and that pads 825 may have minimum dimensions on the order of 20 x 20 μms or more.
[057] Figure 9 illustrates yet another alternate embodiment of a strap from a side view. Figure 9 illustrates a similar embodiment to that of Figure 8, which further incorporates an insulator. Substrate 910 includes integrated circuit 920 embedded therein. Pads 925 are a part of integrated circuit 920, and may be expected to have similar dimensions to pads 825. Insulator (dielectric) 930 is deposited on integrated circuit 920 through use of a thick film process. Insulator 930 may be expected to have a thickness on the order of 10 (microns). Also deposited with an additive process is a conductive medium 940, which covers both an insulator 930 and some portion of a pad 925, that thereby allows for electrical contact between the integrated circuit 920 and a large scale component. Conductive medium 940 may be expected to have similar characteristics to conductive medium 840.
[058] Figure 10 illustrates a side view of still another alternate embodiment of a strap. In this embodiment, the insulator (1030) is a thin-film insulator patterned with vias through which the conductive medium (1040) may achieve contact with the pads (1025) of the integrated circuit (1020). As will be appreciated, the vias require greater precision in patterning than do any of the insulators of conductor components of Figures 8 and 9. Moreover, as will be appreciated, the substrate 1010 may have insulator 1030 covering nearly its whole surface, rather than the limited areas of Figure 9. Additionally, it will be appreciated that the pads 1025 may be smaller on integrated circuit 1020 than similar pads of integrated circuits 920 and 820.
[059] Figure 11 illustrates another alternate embodiment of a method of forming an apparatus including both small-feature-size and large-feature-size components. At block 1110, an integrated circuit is embedded within a supporting substrate. At block 1120, a thin-film insulator is applied to the substrate. At block 1130, the insulator is patterned such as through a photolithographic thin-film process, whereby portions of the insulator are removed to expose portions of the substrate or integrated circuit, such as bond or conductive pads. Further cleaning, such as washing away photoresist for example, may be involved as part of application, patterning, or even in a post-etch phase. Alternatively, as will be appreciated, a photosensitive insulator or dielectric may be used, thereby eliminating the need for photoresist for example.
[060] At block 1140, a conductive medium is applied to the substrate, coating all or part of the insulator. At block 1150, the conductive medium is processed (such as by heat curing, for example) as necessary to form a proper conductor. Note that curing of silver ink is known in the art to be possible at 90-100°C for some formulations with a reasonable cure time for various manufacturing processes. It will be appreciated that cure times do vary, and that those skilled in the art may adapt cure processes to the needs of a surrounding manufacturing process and the devices to be produced. At block 1160, the large-scale component is attached to the conductive medium, thereby achieving electrical coupling with the integrated circuit. Also note that the final processing of the conductive medium of block 1160 may be performed after the large scale component is attached at block 1170.
[061] For the most part, the previous description has concentrated on use of the invention in conjunction with attaching a strap having embedded therein an integrated circuit to a separate large- scale component. It will be appreciated that other embodiments exist in which the separate large-scale component is not involved. In particular, a large-feature-size component may be incorporated as part of the strap, such as an embedded conductor acting as an antenna, or may be formed on the strap as illustrated in Figures 12a and 12b. Printing or otherwise using additive processing technology to form an antenna 1240 of the conductive medium on the strap is one option.
[062] Alternately, other large-feature-size components, such as power sources, sensors, or logic devices for example may either be formed on the strap or attached to the strap. Interconnecting a Nanoblock IC with such large-feature-size components on the strap may be accomplished through use of conductive medium 1440, allowing for electrical coupling between the large-feature-size components 1460 and the small-feature-size (Nanoblock IC for example) components 1420, as in Figure 14. Moreover, a conductive medium 1340 may be used to interconnect two or more small-feature- size components embedded in a single substrate, such as two Nanoblock ICs for example, as illustrated in Figure 13.
[063] Figure 12A illustrates a top view of another embodiment of a substrate. Substrate 1210 may be a substrate such as those discussed previously, including a flexible or rigid material. Integrated circuit (IC) 1220 is embedded in an opening in substrate 1210. Insulator 1230 is a layer of insulating material (or a dielectric layer) on top of both substrate 1210 and IC 1220 and may have planarizing properties. Contact holes 1215 are holes in the insulator 1230 above contact pads of IC 1220, allowing for physical contact and electrical connection between IC 1220 and conductive media 1240. Layer 1250 is another insulator or dielectric above portions of conductive media 1240, insulator 1220 and substrate 1210, and above all of IC 1220. Note that the actual configuration of the various layers may vary considerably. For example, conductive media 1240 is formed into two arms of an antenna, such as may be useful for radio frequency applications. However, batteries, sensors, power supplies, button cells, and displays and display electrodes may also be formed through use of conductive media and other materials.
[064] Figure 12B illustrates a side view of another embodiment of a substrate. As is illustrated, conductive media 1240 occupies the contact holes 1215 of Figure 12A to contact directly with IC 1220. Furthermore, as will be appreciated, the segments illustrated with respect to conductive media 1240 correspond to the various segments of the antenna as it traces its path along the surface of the insulator 1230. Along these lines, it will be appreciated that the presence of the insulator 1230 may not be necessary in some instances. [065] Figure 13 illustrates a side view of yet another embodiment of a substrate. Substrate 1310 includes first integrated circuit (IC) 1320 and second integrated circuit (IC) 1325. Insulator 1330 is formed above IC 1320, IC 1325 and substrate 1310. Conductive media 1340 is formed above insulator 1330, and contacts both IC 1320 and IC 1325. One portion of conductive media 1340 forms an electrical connection between IC 1320 and IC 1325, thereby electrically coupling IC 1320 to IC 1325. Above both IC 1320 and IC 1325 are formed insulator layers 1350.
[066] Figure 14 illustrates a side view of still another embodiment of a substrate. Substrate 1410 has embedded in an opening therein an IC 1420. Formed above substrate 1410 and IC 1420 is insulator 1430. Formed above insulator 1430 and connected to IC 1420 is conductive media 1440, a portion of which is connected to sensor 1460, thereby electrically coupling IC 1420 to sensor 1460. Formed above a portion of conductive media 1440 and insulator 1430 is insulator 1450, which may or may not be of the same material as insulator 1430.
[067] In the foregoing detailed description, the method and apparatus of the present invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present invention. In particular, the separate blocks of the various block diagrams represent functional blocks of methods or apparatuses and are not necessarily indicative of physical or logical separations or of an order of operation inherent in the spirit and scope of the present invention. For example, the various blocks of Figure 1 may be integrated into components, or may be subdivided into components, and may alternately be formed in different physical shapes from those illustrated. Similarly, the blocks of Figure 6 (for example) represent portions of a method that, in some embodiments, may be reordered or may be organized in parallel rather than in a linear or step-wise fashion. The present specification and figures are accordingly to be regarded as illustrative rather than restrictive.

Claims

CLAIMSWhat is claimed is:
1. An apparatus comprising: a strap including a substrate with an embedded integrated circuit, the integrated circuit having a conductive pad, and a conductive medium attached to the conductive pad of the integrated circuit; and a large-scale component attached to the conductive medium, the large-scale component electrically coupled to the integrated circuit.
2. The apparatus of claim 1 , wherein the large-scale component is a substrate including therein an antenna, the antenna electrically coupled to the integrated circuit directly through the conductive medium.
3. The apparatus of claim 1 , wherein the conductive medium is paste.
4. The apparatus of claim 1 , wherein the conductive medium is electrically conductive tape.
5. The apparatus of claim 2, wherein the conductive medium is paste and wherein the integrated circuit is a Nanoblock IC containing circuitry suitable for radio frequency applications.
6. The apparatus of claim 5, wherein the large-scale component is a substrate having thereon an antenna, the antenna electrically coupled to the integrated circuit directly through the conductive medium.
7. The apparatus of claim 1 , wherein the integrated circuit is a circuit suitable for use with radio frequency applications.
8. The apparatus of claim 7, wherein the large-scale component is a substrate having thereon an antenna, the antenna electrically coupled to the integrated circuit directly through the conductive medium.
9. The apparatus of claim 1 , wherein the integrated circuit includes a circuit suitable to control an electronic display.
10. The apparatus of claim 9, wherein the large-scale component is a substrate including thereon a display electrode, the display electrode electrically coupled to the integrated circuit directly through the conductive medium.
11. The apparatus of claim 9, wherein the large-scale component is a substrate including thereon a display electrode connected to a conductor, the conductor connected to the conductive medium, thereby electrically coupling the display electrode to the integrated circuit.
12. The apparatus of claim 11 , wherein the display electrode is printed on the substrate.
13. The apparatus of claim 1 , wherein the large-scale component is a substrate including therein a sensor, the sensor electrically coupled to the integrated circuit directly through the conductive medium.
14. The apparatus of claim 1 , wherein the large-scale component is a power source, the power source electrically coupled to the integrated circuit directly through the conductive medium.
15. The apparatus of claim 14, wherein the power source is a substrate including a battery, the battery electrically coupled to the integrated circuit directly through the conductive medium.
16. The apparatus of claim 15, wherein the battery is a button cell embedded within the large-scale component substrate.
17. The apparatus of claim 15, wherein the battery is a thick film cell printed on the large-scale component substrate.
18. The apparatus of claim 1 , wherein the large-scale component is a substrate having thereon a logic device, the logic device electrically coupled to the integrated circuit directly through the conductive medium.
19. The apparatus of claim 1 , wherein the conductive medium is metal particles suspended in a carrier.
20. The apparatus of claim 1 , wherein the conductive medium is a conductive polymer.
21. The apparatus of claim 1 , wherein the conductive medium is a carbon-based conductor.
22. The apparatus of claim 1 , wherein the substrate is of a flexible material.
23. A method comprising: attaching a conductive medium to a substrate having embedded therein an integrated circuit such that the conductive medium is connected electrically to the integrated circuit; and attaching a large-scale component to the conductive medium such that the large-scale component is electrically connected to the conductive medium.
24. The method of claim 23, further comprising: embedding the integrated circuit in the substrate.
25. The method of claim 23, wherein attaching the conductive medium is accomplished by printing the conductive medium on the substrate and curing the conductive medium.
26. The method of claim 23 wherein attaching the conductive medium is accomplished by coating the conductive medium in fluidic form on the substrate and curing the conductive medium.
27. The method of claim 25, wherein: printing comprises screen printing.
28. The method of claim 25, wherein: printing comprises stencil printing.
29. The method of claim 25, wherein: printing comprises printing using an ink jet printer.
30. The method of claim 26, wherein: coating the conductive medium comprises extruding the conductive medium.
31. The method of claim 26, wherein: coating the conductive medium comprises curtain coating.
32. The method of claim 23, wherein attaching the conductive medium is accomplished by laminating the conductive medium to the substrate.
33. The method of claim 23, wherein attaching the conductive medium is accomplished by hot pressing the conductive medium to the substrate.
34. The method of claim 23, wherein: the integrated circuit is a Nanoblock IC.
35. The method of claim 23, wherein: the integrated circuit is suitable for radio frequency applications.
36. The method of claim 23, wherein: the large scale component is a substrate having thereon an antenna, the antenna electrically connected to the conductive medium.
37. An apparatus comprising: an integrated circuit embedded within a substrate; a thin-film dielectric layer formed over a portion of the integrated circuit and a portion of the substrate; a conductive medium formed over a portion of the thin-film dielectric layer, the conductive medium having direct electrical connection with the integrated circuit.
38. The apparatus of claim 37, wherein the substrate is of a flexible material.
39. The apparatus of claim 37, wherein the conductive medium is a solder.
40. The apparatus of claim 37, further comprising: a large-scale component connected to the conductive medium, the large-scale component electrically coupled to the integrated circuit.
41. The apparatus of claim 40, wherein the conductive medium is conductive paste.
42. The apparatus of claim 40, wherein the conductive medium is silver ink.
43. The apparatus of claim 40, wherein the conductive medium is tape.
44. The apparatus of claim 40, wherein the conductive medium is metal particles suspended in a carrier.
45. The apparatus of claim 40, wherein the conductive medium is a conductive polymer.
46. The apparatus of claim 40, wherein the conductive medium is solder.
47. The apparatus of claim 40, wherein the conductive medium is a carbon-based conductor.
48. The apparatus of claim 40 wherein the large-scale component is an antenna.
49. The apparatus of claim 40 wherein the large-scale component is a power source.
50. The apparatus of claim 49 wherein the large-scale component is a battery.
51. The apparatus of claim 49 wherein the large-scale component is a thick film cell printed on a large-scale component substrate.
52. The apparatus of claim 49 wherein the large-scale component is a button cell.
53. The apparatus of claim 40 wherein the large-scale component is a sensor.
54. The apparatus of claim 40 wherein the large-scale component is a logic device.
55. The apparatus of claim 40 wherein the large-scale component is a display electrode.
56. The apparatus of claim 37, wherein the integrated circuit is a Nanoblock IC.
57. The apparatus of claim 37, wherein the integrated circuit is a display driver.
58. The apparatus of claim 37, wherein the integrated circuit is a radio-frequency identification circuit.
59. The apparatus of claim 37 wherein the integrated circuit is a circuit suitable for use with radio frequency applications.
60. The apparatus of claim 40 wherein the large-scale component is a substrate having thereon an antenna, the antenna electrically coupled to the integrated circuit directly through the conductive medium.
61. A method comprising: forming a thin-film insulator on a portion of an integrated circuit and a portion of a substrate, the integrated circuit embedded within the substrate; and attaching a conductive medium to the thin-film insulator and to the integrated circuit, the conductive medium electrically connected to the integrated circuit.
62. The method of claim 61 , further comprising: attaching a large-scale component to the conductive medium such that the large-scale component is coupled electrically to the integrated circuit.
63. The method of claim 61 , further comprising: embedding the integrated circuit in the substrate.
64. The method of claim 61 further comprising: adhering tape to the conductive medium on the substrate ; and adhering the tape to a large-scale component, thereby attaching the large-scale component to conductive medium, and thereby electrically coupling the large-scale component to the integrated circuit.
65. The method of claim 61 wherein: forming the thin-film insulator includes: depositing the thin-film insulator on the integrated circuit and on the substrate, and patterning the thin-film insulator through a photolithographic process.
66. The method of claim 61 , wherein: attaching the conductive medium includes printing conductive ink.
67. The method of claim 61 , wherein: attaching the conductive medium includes screen printing conductive paste and curing the conductive paste.
68. The method of claim 65, wherein: attaching the conductive medium includes screen printing solder paste and reflowing the solder.
69. The method of claim 61 , wherein: attaching the conductive medium includes applying conductive tape.
70. The method of claim 69, wherein: conductive tape is laminated.
71. The method of claim 69, wherein: conductive tape is hot pressed.
72. The method of claim 61 , wherein attaching the conductive medium includes extrusion coating.
73. The method of claim 61 , wherein attaching the conductive medium includes curtain coating.
74. The method of claim 61 , wherein: attaching the conductive medium includes applying a carbon- based conductor.
75. The method of claim 61 , wherein: attaching the conductive medium includes applying a conductive polymer.
76. The method of claim 61 , wherein: attaching the conductive medium includes applying a carrier, the carrier including metal particles suspended therein.
77. The method of claim 61 , wherein: attaching the conductive medium includes ink jet printing.
78. The method of claim 62, wherein: the large-scale component is an antenna.
79. The method of claim 62 wherein: the large-scale component is a power supply.
80. The method of claim 62 wherein: the large-scale component is a display electrode.
81. The method of claim 62, wherein: the large-scale component is a sensor.
82. The method of claim 62, wherein: the large-scale component is a logic device.
83. The method of claim 62, wherein: the integrated circuit is a suitable for radio frequency applications.
84. The method of claim 62, wherein: the integrated circuit is a display driver. .
85. The method of claim 62, wherein: the integrated circuit is a Nanoblock IC.
86. The method of claim 61 , further comprising: fabricating the integrated circuit.
87. An apparatus comprising: a substrate having embedded therein an integrated circuit, the integrated circuit having a conductive pad; and a conductive medium attached to the conductive pad of the integrated circuit.
88. The apparatus of claim 87, wherein the substrate is of a flexible material.
89. The apparatus of claim 87, further comprising: a large-scale component attached to the conductive medium, the large-scale component electrically coupled to the integrated circuit.
90. The apparatus of claim 87, wherein the substrate has thereon a logic device, the logic device electrically coupled to the integrated circuit directly through the conductive medium.
91. The apparatus of claim 90, wherein the conductive medium is a solder.
92. The apparatus of claim 89, wherein the logic device is a microprocessor.
93. The apparatus of claim 89, wherein the logic device is a memory integrated circuit.
94. The apparatus of claim 89, wherein the substrate has thereon a power source, the logic device electrically coupled to the power source directly through the conductive medium.
95. The apparatus of claim 94, wherein the power source is a thick film cell.
96. The apparatus of claim 94, wherein the power source is a button cell.
97. The apparatus of claim 87, wherein the substrate has printed thereon an antenna, the antenna electrically coupled to the integrated circuit directly through the conductive medium.
98. The apparatus of claim 87, wherein the conductive medium is formed as an antenna on the substrate.
PCT/US2003/002115 2002-01-23 2003-01-23 Apparatus incorporating small-feature-size and large-feature-size components and method for making same WO2003063211A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2003562978A JP2006504251A (en) 2002-01-23 2003-01-23 Apparatus incorporating small size component and large size component and method of making the same
KR10-2004-7011487A KR20040105705A (en) 2002-01-23 2003-01-23 Apparatus incorporating small-feature-size and large-feature-size components and method for making same
EP03703985A EP1468443A1 (en) 2002-01-23 2003-01-23 Apparatus incorporating small-feature-size and large-feature-size components and method for making same
CA002474054A CA2474054A1 (en) 2002-01-23 2003-01-23 Apparatus incorporating small-feature-size and large-feature-size components and method for making same
AU2003205307A AU2003205307B2 (en) 2002-01-23 2003-01-23 Apparatus incorporating small-feature-size and large-feature-size components and method for making same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US5619202A 2002-01-23 2002-01-23
US10/056,192 2002-01-23

Publications (1)

Publication Number Publication Date
WO2003063211A1 true WO2003063211A1 (en) 2003-07-31

Family

ID=27609271

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/002115 WO2003063211A1 (en) 2002-01-23 2003-01-23 Apparatus incorporating small-feature-size and large-feature-size components and method for making same

Country Status (7)

Country Link
EP (1) EP1468443A1 (en)
JP (1) JP2006504251A (en)
KR (1) KR20040105705A (en)
CN (1) CN1606796A (en)
AU (1) AU2003205307B2 (en)
CA (1) CA2474054A1 (en)
WO (1) WO2003063211A1 (en)

Cited By (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005076353A2 (en) * 2004-01-30 2005-08-18 Alien Technology Corporation Apparatus incorporating small-feature-size and large-feature-size components and method for making same
US7195733B2 (en) 2004-04-27 2007-03-27 The Board Of Trustees Of The University Of Illinois Composite patterning devices for soft lithography
US7230580B1 (en) * 2003-08-29 2007-06-12 National Semiconductor Corporation Design of a two interconnect IC chip for a radio frequency identification tag and method for manufacturing same
US7521292B2 (en) 2004-06-04 2009-04-21 The Board Of Trustees Of The University Of Illinois Stretchable form of single crystal silicon for high performance electronics on rubber substrates
US7557367B2 (en) 2004-06-04 2009-07-07 The Board Of Trustees Of The University Of Illinois Stretchable semiconductor elements and stretchable electrical circuits
US7576656B2 (en) 2005-09-15 2009-08-18 Alien Technology Corporation Apparatuses and methods for high speed bonding
US7799699B2 (en) 2004-06-04 2010-09-21 The Board Of Trustees Of The University Of Illinois Printable semiconductor structures and related methods of making and assembling
US7943491B2 (en) 2004-06-04 2011-05-17 The Board Of Trustees Of The University Of Illinois Pattern transfer printing by kinetic control of adhesion to an elastomeric stamp
US8865489B2 (en) 2009-05-12 2014-10-21 The Board Of Trustees Of The University Of Illinois Printed assemblies of ultrathin, microscale inorganic light emitting diodes for deformable and semitransparent displays
US8886334B2 (en) 2008-10-07 2014-11-11 Mc10, Inc. Systems, methods, and devices using stretchable or flexible electronics for medical applications
US8905772B2 (en) 2008-03-05 2014-12-09 The Board Of Trustees Of The University Of Illinois Stretchable and foldable electronic devices
US8912907B2 (en) 2003-03-24 2014-12-16 Alien Technology, Llc RFID tags and processes for producing RFID tags
US8934965B2 (en) 2011-06-03 2015-01-13 The Board Of Trustees Of The University Of Illinois Conformable actively multiplexed high-density surface electrode array for brain interfacing
US8946683B2 (en) 2008-06-16 2015-02-03 The Board Of Trustees Of The University Of Illinois Medium scale carbon nanotube thin film integrated circuits on flexible plastic substrates
US9012784B2 (en) 2008-10-07 2015-04-21 Mc10, Inc. Extremely stretchable electronics
US9070063B2 (en) 2004-11-22 2015-06-30 Ruizhang Technology Limited Company Radio frequency identification (RFID) tag for an item having a conductive layer included or attached
US9117940B2 (en) 2007-01-17 2015-08-25 The Board Of Trustees Of The University Of Illinois Optical systems fabricated by printing-based assembly
US9159635B2 (en) 2011-05-27 2015-10-13 Mc10, Inc. Flexible electronic structure
US9171794B2 (en) 2012-10-09 2015-10-27 Mc10, Inc. Embedding thin chips in polymer
US9289132B2 (en) 2008-10-07 2016-03-22 Mc10, Inc. Catheter balloon having stretchable integrated circuitry and sensor array
US9324733B2 (en) 2004-06-04 2016-04-26 The Board Of Trustees Of The University Of Illinois Controlled buckling structures in semiconductor interconnects and nanomembranes for stretchable electronics
US9442285B2 (en) 2011-01-14 2016-09-13 The Board Of Trustees Of The University Of Illinois Optical component array having adjustable curvature
US9554484B2 (en) 2012-03-30 2017-01-24 The Board Of Trustees Of The University Of Illinois Appendage mountable electronic devices conformable to surfaces
US9691873B2 (en) 2011-12-01 2017-06-27 The Board Of Trustees Of The University Of Illinois Transient devices designed to undergo programmable transformations
US9723122B2 (en) 2009-10-01 2017-08-01 Mc10, Inc. Protective cases with integrated electronics
US9765934B2 (en) 2011-05-16 2017-09-19 The Board Of Trustees Of The University Of Illinois Thermally managed LED arrays assembled by printing
US9936574B2 (en) 2009-12-16 2018-04-03 The Board Of Trustees Of The University Of Illinois Waterproof stretchable optoelectronics
US9986924B2 (en) 2010-03-17 2018-06-05 The Board Of Trustees Of The University Of Illinois Implantable biomedical devices on bioresorbable substrates
US10441185B2 (en) 2009-12-16 2019-10-15 The Board Of Trustees Of The University Of Illinois Flexible and stretchable electronic systems for epidermal electronics
US10918298B2 (en) 2009-12-16 2021-02-16 The Board Of Trustees Of The University Of Illinois High-speed, high-resolution electrophysiology in-vivo using conformal electronics
US10925543B2 (en) 2015-11-11 2021-02-23 The Board Of Trustees Of The University Of Illinois Bioresorbable silicon electronics for transient implants
US11029198B2 (en) 2015-06-01 2021-06-08 The Board Of Trustees Of The University Of Illinois Alternative approach for UV sensing
US11118965B2 (en) 2015-06-01 2021-09-14 The Board Of Trustees Of The University Of Illinois Miniaturized electronic systems with wireless power and near-field communication capabilities

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104224167B (en) * 2014-09-21 2016-06-01 北京师范大学 Disposable brain condition monitoring flexible patch electrode

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5545291A (en) * 1993-12-17 1996-08-13 The Regents Of The University Of California Method for fabricating self-assembling microstructures
JPH11353439A (en) * 1998-06-04 1999-12-24 Dainippon Printing Co Ltd Noncontact type ic card and its manufacture, and base body for noncontact ic card
JP2001175837A (en) * 1999-12-22 2001-06-29 Toppan Printing Co Ltd Ic card
WO2002097724A1 (en) * 2001-05-31 2002-12-05 Alien Technology Corporation Multi-feature-size electronic structures

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5545291A (en) * 1993-12-17 1996-08-13 The Regents Of The University Of California Method for fabricating self-assembling microstructures
JPH11353439A (en) * 1998-06-04 1999-12-24 Dainippon Printing Co Ltd Noncontact type ic card and its manufacture, and base body for noncontact ic card
JP2001175837A (en) * 1999-12-22 2001-06-29 Toppan Printing Co Ltd Ic card
WO2002097724A1 (en) * 2001-05-31 2002-12-05 Alien Technology Corporation Multi-feature-size electronic structures

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 03 30 March 2000 (2000-03-30) *
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 23 10 February 2001 (2001-02-10) *

Cited By (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9418328B2 (en) 2003-03-24 2016-08-16 Ruizhang Technology Limited Company RFID tags and processes for producing RFID tags
US8912907B2 (en) 2003-03-24 2014-12-16 Alien Technology, Llc RFID tags and processes for producing RFID tags
US7230580B1 (en) * 2003-08-29 2007-06-12 National Semiconductor Corporation Design of a two interconnect IC chip for a radio frequency identification tag and method for manufacturing same
WO2005076353A2 (en) * 2004-01-30 2005-08-18 Alien Technology Corporation Apparatus incorporating small-feature-size and large-feature-size components and method for making same
WO2005076353A3 (en) * 2004-01-30 2006-02-02 Alien Technology Corp Apparatus incorporating small-feature-size and large-feature-size components and method for making same
US7195733B2 (en) 2004-04-27 2007-03-27 The Board Of Trustees Of The University Of Illinois Composite patterning devices for soft lithography
US11088268B2 (en) 2004-06-04 2021-08-10 The Board Of Trustees Of The University Of Illinois Methods and devices for fabricating and assembling printable semiconductor elements
US10355113B2 (en) 2004-06-04 2019-07-16 The Board Of Trustees Of The University Of Illinois Controlled buckling structures in semiconductor interconnects and nanomembranes for stretchable electronics
US7799699B2 (en) 2004-06-04 2010-09-21 The Board Of Trustees Of The University Of Illinois Printable semiconductor structures and related methods of making and assembling
US7943491B2 (en) 2004-06-04 2011-05-17 The Board Of Trustees Of The University Of Illinois Pattern transfer printing by kinetic control of adhesion to an elastomeric stamp
US11456258B2 (en) 2004-06-04 2022-09-27 The Board Of Trustees Of The University Of Illinois Stretchable form of single crystal silicon for high performance electronics on rubber substrates
US9105555B2 (en) 2004-06-04 2015-08-11 The Board Of Trustees Of The University Of Illinois Stretchable form of single crystal silicon for high performance electronics on rubber substrates
US10204864B2 (en) 2004-06-04 2019-02-12 The Board Of Trustees Of The University Of Illinois Stretchable form of single crystal silicon for high performance electronics on rubber substrates
US9324733B2 (en) 2004-06-04 2016-04-26 The Board Of Trustees Of The University Of Illinois Controlled buckling structures in semiconductor interconnects and nanomembranes for stretchable electronics
US10374072B2 (en) 2004-06-04 2019-08-06 The Board Of Trustees Of The University Of Illinois Methods and devices for fabricating and assembling printable semiconductor elements
US7622367B1 (en) 2004-06-04 2009-11-24 The Board Of Trustees Of The University Of Illinois Methods and devices for fabricating and assembling printable semiconductor elements
US9768086B2 (en) 2004-06-04 2017-09-19 The Board Of Trustees Of The University Of Illinois Methods and devices for fabricating and assembling printable semiconductor elements
US7557367B2 (en) 2004-06-04 2009-07-07 The Board Of Trustees Of The University Of Illinois Stretchable semiconductor elements and stretchable electrical circuits
US9761444B2 (en) 2004-06-04 2017-09-12 The Board Of Trustees Of The University Of Illinois Methods and devices for fabricating and assembling printable semiconductor elements
US7521292B2 (en) 2004-06-04 2009-04-21 The Board Of Trustees Of The University Of Illinois Stretchable form of single crystal silicon for high performance electronics on rubber substrates
US9515025B2 (en) 2004-06-04 2016-12-06 The Board Of Trustees Of The University Of Illinois Stretchable form of single crystal silicon for high performance electronics on rubber substrates
US9450043B2 (en) 2004-06-04 2016-09-20 The Board Of Trustees Of The University Of Illinois Methods and devices for fabricating and assembling printable semiconductor elements
US9070063B2 (en) 2004-11-22 2015-06-30 Ruizhang Technology Limited Company Radio frequency identification (RFID) tag for an item having a conductive layer included or attached
US7576656B2 (en) 2005-09-15 2009-08-18 Alien Technology Corporation Apparatuses and methods for high speed bonding
US11309305B2 (en) 2007-01-17 2022-04-19 The Board Of Trustees Of The University Of Illinois Optical systems fabricated by printing-based assembly
US10361180B2 (en) 2007-01-17 2019-07-23 The Board Of Trustees Of The University Of Illinois Optical systems fabricated by printing-based assembly
US10424572B2 (en) 2007-01-17 2019-09-24 The Board Of Trustees Of The University Of Illinois Optical systems fabricated by printing-based assembly
US10504882B2 (en) 2007-01-17 2019-12-10 The Board Of Trustees Of The University Of Illinois Optical systems fabricated by printing-based assembly
US9601671B2 (en) 2007-01-17 2017-03-21 The Board Of Trustees Of The University Of Illinois Optical systems fabricated by printing-based assembly
US9117940B2 (en) 2007-01-17 2015-08-25 The Board Of Trustees Of The University Of Illinois Optical systems fabricated by printing-based assembly
US10292261B2 (en) 2008-03-05 2019-05-14 The Board Of Trustees Of The University Of Illinois Stretchable and foldable electronic devices
US8905772B2 (en) 2008-03-05 2014-12-09 The Board Of Trustees Of The University Of Illinois Stretchable and foldable electronic devices
US10064269B2 (en) 2008-03-05 2018-08-28 The Board Of Trustees Of The University Of Illinois Stretchable and foldable electronic devices
US8946683B2 (en) 2008-06-16 2015-02-03 The Board Of Trustees Of The University Of Illinois Medium scale carbon nanotube thin film integrated circuits on flexible plastic substrates
US9012784B2 (en) 2008-10-07 2015-04-21 Mc10, Inc. Extremely stretchable electronics
US8886334B2 (en) 2008-10-07 2014-11-11 Mc10, Inc. Systems, methods, and devices using stretchable or flexible electronics for medical applications
US9289132B2 (en) 2008-10-07 2016-03-22 Mc10, Inc. Catheter balloon having stretchable integrated circuitry and sensor array
US10546841B2 (en) 2009-05-12 2020-01-28 The Board Of Trustees Of The University Of Illinois Printed assemblies of ultrathin, microscale inorganic light emitting diodes for deformable and semitransparent displays
US8865489B2 (en) 2009-05-12 2014-10-21 The Board Of Trustees Of The University Of Illinois Printed assemblies of ultrathin, microscale inorganic light emitting diodes for deformable and semitransparent displays
US9647171B2 (en) 2009-05-12 2017-05-09 The Board Of Trustees Of The University Of Illinois Printed assemblies of ultrathin, microscale inorganic light emitting diodes for deformable and semitransparent displays
US9723122B2 (en) 2009-10-01 2017-08-01 Mc10, Inc. Protective cases with integrated electronics
US9936574B2 (en) 2009-12-16 2018-04-03 The Board Of Trustees Of The University Of Illinois Waterproof stretchable optoelectronics
US10441185B2 (en) 2009-12-16 2019-10-15 The Board Of Trustees Of The University Of Illinois Flexible and stretchable electronic systems for epidermal electronics
US10918298B2 (en) 2009-12-16 2021-02-16 The Board Of Trustees Of The University Of Illinois High-speed, high-resolution electrophysiology in-vivo using conformal electronics
US11057991B2 (en) 2009-12-16 2021-07-06 The Board Of Trustees Of The University Of Illinois Waterproof stretchable optoelectronics
US9986924B2 (en) 2010-03-17 2018-06-05 The Board Of Trustees Of The University Of Illinois Implantable biomedical devices on bioresorbable substrates
US9442285B2 (en) 2011-01-14 2016-09-13 The Board Of Trustees Of The University Of Illinois Optical component array having adjustable curvature
US9765934B2 (en) 2011-05-16 2017-09-19 The Board Of Trustees Of The University Of Illinois Thermally managed LED arrays assembled by printing
US9159635B2 (en) 2011-05-27 2015-10-13 Mc10, Inc. Flexible electronic structure
US10349860B2 (en) 2011-06-03 2019-07-16 The Board Of Trustees Of The University Of Illinois Conformable actively multiplexed high-density surface electrode array for brain interfacing
US8934965B2 (en) 2011-06-03 2015-01-13 The Board Of Trustees Of The University Of Illinois Conformable actively multiplexed high-density surface electrode array for brain interfacing
US10396173B2 (en) 2011-12-01 2019-08-27 The Board Of Trustees Of The University Of Illinois Transient devices designed to undergo programmable transformations
US9691873B2 (en) 2011-12-01 2017-06-27 The Board Of Trustees Of The University Of Illinois Transient devices designed to undergo programmable transformations
US10357201B2 (en) 2012-03-30 2019-07-23 The Board Of Trustees Of The University Of Illinois Appendage mountable electronic devices conformable to surfaces
US9554484B2 (en) 2012-03-30 2017-01-24 The Board Of Trustees Of The University Of Illinois Appendage mountable electronic devices conformable to surfaces
US10052066B2 (en) 2012-03-30 2018-08-21 The Board Of Trustees Of The University Of Illinois Appendage mountable electronic devices conformable to surfaces
US9171794B2 (en) 2012-10-09 2015-10-27 Mc10, Inc. Embedding thin chips in polymer
US11029198B2 (en) 2015-06-01 2021-06-08 The Board Of Trustees Of The University Of Illinois Alternative approach for UV sensing
US11118965B2 (en) 2015-06-01 2021-09-14 The Board Of Trustees Of The University Of Illinois Miniaturized electronic systems with wireless power and near-field communication capabilities
US10925543B2 (en) 2015-11-11 2021-02-23 The Board Of Trustees Of The University Of Illinois Bioresorbable silicon electronics for transient implants

Also Published As

Publication number Publication date
KR20040105705A (en) 2004-12-16
CN1606796A (en) 2005-04-13
EP1468443A1 (en) 2004-10-20
AU2003205307B2 (en) 2009-03-26
CA2474054A1 (en) 2003-07-31
JP2006504251A (en) 2006-02-02

Similar Documents

Publication Publication Date Title
AU2003205307B2 (en) Apparatus incorporating small-feature-size and large-feature-size components and method for making same
AU2003205307A1 (en) Apparatus incorporating small-feature-size and large-feature-size components and method for making same
US7214569B2 (en) Apparatus incorporating small-feature-size and large-feature-size components and method for making same
JP4494771B2 (en) Smart label and smart label web
US4251852A (en) Integrated circuit package
US7342179B2 (en) Electronic device and method for producing the same
CA2569694C (en) Method of forming circuit assembly
CN101504937A (en) Method of manufacturing semiconductor device
CN101556975A (en) Wafer level interconnection and method
WO2006056999A2 (en) Methods for manufacturing a sensor assembly
KR101414089B1 (en) Wiring substrate, method of manufacturing wiring substrate, and electronic apparatus
US6864119B2 (en) COF semiconductor device and a manufacturing method for the same
JP2019080063A (en) Electronic device and manufacturing method thereof
CN115207019B (en) Display panel and manufacturing method thereof
US20050233620A1 (en) Anisotropic conductive sheet and its manufacturing method
JPS63102110A (en) Anisotropic conductor and making thereof
US20070159341A1 (en) Packaging structure for radio frequency identification devices
JP2579458B2 (en) Anisotropic conductive film and method for producing the same
US7312142B2 (en) Method for making cable with a conductive bump array, and method for connecting the cable to a task object
GB2093401A (en) Composite film
JP2000149666A (en) Anisotropic conductive film
JP2001358252A (en) Semiconductor device
JPS63299242A (en) Connection of semiconductor device
CN115127706A (en) Pressure sensor, circuit board and consumer electronics
JPH11195673A (en) Electrode structure of wiring substrate

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SD SE SG SK SL TJ TM TN TR TT TZ UA UG UZ VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 2003703985

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 20038017814

Country of ref document: CN

WWE Wipo information: entry into national phase

Ref document number: 2003562978

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 2003205307

Country of ref document: AU

WWE Wipo information: entry into national phase

Ref document number: 2474054

Country of ref document: CA

WWE Wipo information: entry into national phase

Ref document number: 1020047011487

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 2003703985

Country of ref document: EP

DPE2 Request for preliminary examination filed before expiration of 19th month from priority date (pct application filed from 20040101)