WO2003067730A3 - Power conditioning module - Google Patents

Power conditioning module Download PDF

Info

Publication number
WO2003067730A3
WO2003067730A3 PCT/US2003/002868 US0302868W WO03067730A3 WO 2003067730 A3 WO2003067730 A3 WO 2003067730A3 US 0302868 W US0302868 W US 0302868W WO 03067730 A3 WO03067730 A3 WO 03067730A3
Authority
WO
WIPO (PCT)
Prior art keywords
interface
conditioning module
power
power conditioning
disposed
Prior art date
Application number
PCT/US2003/002868
Other languages
French (fr)
Other versions
WO2003067730A2 (en
Inventor
Thomas William Kenny Jr
Goodson E Kenneth
Juan G Santiago
George Carl Everett Jr
Original Assignee
Cooligy Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/072,137 external-priority patent/US6606251B1/en
Application filed by Cooligy Inc filed Critical Cooligy Inc
Priority to AU2003217286A priority Critical patent/AU2003217286A1/en
Publication of WO2003067730A2 publication Critical patent/WO2003067730A2/en
Publication of WO2003067730A3 publication Critical patent/WO2003067730A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors

Abstract

In one aspect, the present invention is a technique of, and a system for conditioning power for a consuming device. In this regard, a power conditioning module (100), affixed to an integrated circuit device (200), conditions power to be applied to the integrated circuit device. The power conditioning module includes a semiconductor substrate (102) having a first interface and a second interface wherein the first interface opposes the second interface. The power conditioning module further includes a plurality of interface vias (104a-104h), to provide electrical connection between the first interface and the second interface, and a first set of pads (106I-106p), disposed on the first interface and a second set of pads (106a-106h) disposed on the second interface. Each of the pads is connected to a corresponding one of the interface vias on either the first or second interface. The power conditioning module also includes electrical circuitry (112), disposed within semiconductor substrate, to condition the power to be applied to the integrated circuit device. The electrical circuitry may be disposed on the first interface, the second interface, or both interfaces. Moreover, the electrical circuitry includes at least one voltage regulator and at least one capacitor.
PCT/US2003/002868 2002-02-07 2003-01-31 Power conditioning module WO2003067730A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003217286A AU2003217286A1 (en) 2002-02-07 2003-01-31 Power conditioning module

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US10/072,137 US6606251B1 (en) 2002-02-07 2002-02-07 Power conditioning module
US10/072,137 2002-02-07
US10/114,005 2002-03-27
US10/114,005 US6678168B2 (en) 2002-02-07 2002-03-27 System including power conditioning modules

Publications (2)

Publication Number Publication Date
WO2003067730A2 WO2003067730A2 (en) 2003-08-14
WO2003067730A3 true WO2003067730A3 (en) 2004-01-29

Family

ID=27736811

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/US2003/002869 WO2003067630A2 (en) 2002-02-07 2003-01-31 System including power conditioning modules
PCT/US2003/002868 WO2003067730A2 (en) 2002-02-07 2003-01-31 Power conditioning module

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PCT/US2003/002869 WO2003067630A2 (en) 2002-02-07 2003-01-31 System including power conditioning modules

Country Status (3)

Country Link
AU (2) AU2003217286A1 (en)
TW (1) TWI239438B (en)
WO (2) WO2003067630A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101766835B1 (en) * 2011-05-04 2017-08-09 에스프린팅솔루션 주식회사 Image forming apparatus and method for controlling thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5490117A (en) * 1993-03-23 1996-02-06 Seiko Epson Corporation IC card with dual level power supply interface and method for operating the IC card

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5490117A (en) * 1993-03-23 1996-02-06 Seiko Epson Corporation IC card with dual level power supply interface and method for operating the IC card

Also Published As

Publication number Publication date
AU2003217286A8 (en) 2003-09-02
TWI239438B (en) 2005-09-11
WO2003067630A3 (en) 2003-12-31
AU2003217287A1 (en) 2003-09-02
TW200302960A (en) 2003-08-16
AU2003217287A8 (en) 2003-09-02
AU2003217286A1 (en) 2003-09-02
WO2003067630A2 (en) 2003-08-14
WO2003067730A2 (en) 2003-08-14

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