WO2003077504A2 - Accessory control interface - Google Patents
Accessory control interface Download PDFInfo
- Publication number
- WO2003077504A2 WO2003077504A2 PCT/IB2003/000548 IB0300548W WO03077504A2 WO 2003077504 A2 WO2003077504 A2 WO 2003077504A2 IB 0300548 W IB0300548 W IB 0300548W WO 03077504 A2 WO03077504 A2 WO 03077504A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- master device
- signal line
- interface circuit
- bit serial
- serial bidirectional
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W84/00—Network topologies
- H04W84/18—Self-organising networks, e.g. ad-hoc networks or sensor networks
- H04W84/20—Master-slave selection or change arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/16—Constructional details or arrangements
- G06F1/1613—Constructional details or arrangements for portable computers
- G06F1/1632—External expansion units, e.g. docking stations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W92/00—Interfaces specially adapted for wireless communication networks
- H04W92/16—Interfaces between hierarchically similar devices
- H04W92/18—Interfaces between hierarchically similar devices between terminal devices
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M1/00—Substation equipment, e.g. for use by subscribers
- H04M1/72—Mobile telephones; Cordless telephones, i.e. devices for establishing wireless links to base stations without route selection
- H04M1/724—User interfaces specially adapted for cordless or mobile telephones
- H04M1/72403—User interfaces specially adapted for cordless or mobile telephones with means for local support of applications that increase the functionality
- H04M1/72409—User interfaces specially adapted for cordless or mobile telephones with means for local support of applications that increase the functionality by interfacing with external accessories
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M2201/00—Electronic components, circuits, software, systems or apparatus used in telephone systems
- H04M2201/10—Logic circuits
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- These teachings relate generally to electronic devices, such as mobile terminals, including cellular telephones and personal communicators, and to accessory units for mobile terminals, and more specifically to mobile terminal/accessory interface hardware and software.
- Modern mobile terminals such as cellular telephones and personal communicators, are typically designed with an interface for connecting with external accessory devices. These accessory devices extend the functionality of the mobile terminal and/or provide other useful functions. Examples of accessories include battery chargers, headsets and "hands free” adapters (enabling the mobile terminal to be used without being held in the user's hand).
- the required mobile terminal/accessory interface has increased in complexity as well.
- the interface is typically required to accommodate the transfer of data between the mobile terminal and the accessory.
- the mobile terminal/accessory interface be physically and electrically robust, be capable of handling low error rate data transfers, and yet still be low cost and of minimal complexity. Another important consideration is the power consumption of the mobile terminal/accessory interface. As in all battery powered devices, the minimization of power consumption is an important goal.
- the mobile terminal is enabled to recognize when an accessory is inserted or removed.
- a mobile terminal interrupt signal line is activated by the ACI ASIC for interrupting the data processor of the mobile terminal.
- a mobile terminal interrupt signal line is activated by the ACI ASIC for interrupting the data processor of the mobile terminal.
- the mobile terminal is placed within a hands free (HF) stand the mobile terminal is automatically switched to the HF mode.
- the mobile terminal is removed from the HF stand the mobile terminal is automatically switched out of the HF mode and back to the normal mode of operation.
- the ACI ASIC enables the interface to identify different accessory types by parameters stored as digital data within a memory of the ACI ASIC, and transferred to the mobile terminal using a serial data bus.
- An important feature of this invention is the power savings that are realized, since after insertion detection is accomplished (the mobile terminal and accessory are physically and electrically coupled together) subsequent communications can be performed at a rate set by the low speed (e.g., 32kHz) mobile terminal sleep clock.
- the sleep clock is one used to periodically interrupt the mobile terminal to exit a low power, idle mode of operation. This technique provides considerable savings in mobile terminal (and accessory) power consumption.
- the ACI ASIC includes or is coupled to a simple and inexpensive local oscillator that is implemented as an RC oscillator, as opposed to a crystal oscillator. This is made possible by the tolerance of the interface to the potentially wide frequency range (e.g., 20kHz to 60kHz, nominally about 27kHz) and inaccuracy of the accessory RC oscillator (+-50%).
- the RC oscillator can be integrated into the ACI ASIC, thereby realizing considerable cost and circuit area savings, as well as improving the reliability and testability of the accessory and accessory interface.
- a further advantage made possible by the use of this invention is the ability to design and offer new accessories, even for those mobile terminals that are already in the field. This is possible because the accessory is enabled to inform the mobile terminal of its relevant features due to the presence of a non- volatile memory within the ACI ASIC, where the memory stores feature data that is readable from the mobile terminal through the interface.
- this invention provides an interface between a master device and a slave device.
- the interface includes a bit serial bidirectional signal line for conveying commands and associated data from the master device to the slave device, and for conveying a reset signal, an interrupt signal, and a learning sequence signal for specifying a duration of a bit time for data transferred from the slave device to the master device.
- the bit serial bidirectional signal line further indicates an accessory device connected/disconnected state to the master device.
- the master device is or includes a mobile terminal.
- the mobile terminal samples the data transferred from the slave device to the master device in synchronism with its sleep clock.
- the interface includes, in the accessory device, an Accessory Control Interface chip and an on-chip RC oscillator providing a clock signal to the Accessory Control Interface chip.
- the bit time is a multiple of the clock signal, and the mobile terminal adapts the sampling of the data transferred from the slave device in accordance with the specified duration of the bit time.
- the Accessory Control Interface chip further includes an on-chip non-volatile memory for storing at least accessory related feature data that is readable by the mobile terminal in response to a memory read command sent from the mobile terminal to the Accessory Control Interface chip over the bit serial bidirectional signal line.
- the Accessory Control Interface chip further includes an on-chip challenge/response authentication function that is challenged in response to an authentication challenge command and associated challenge data sent from the mobile terminal to the Accessory Control Interface chip over the bit serial bidirectional signal line.
- Authentication result data is subsequently sent by the Accessory Control Interface chip to the mobile terminal over the bit serial bidirectional signal line in response to an authentication result command sent from the mobile terminal to the Accessory Control Interface chip.
- PDAs personal digital assistants
- mobile terminal and also the term “master device” should be interpreted so as to include a wide variety of equipment types, both portable and non- portable, that include, but that are not limited to, cellular telephones, personal communicators, personal organizers, personal digital assistants (PDAs), email terminals, personal computers, laptop computers, notebook computers, workstations, home electronic devices, including game consoles as well as television monitors, and other devices that can be interfaced to external equipment, devices and/or accessories.
- PDAs personal digital assistants
- email terminals personal computers, laptop computers, notebook computers, workstations, home electronic devices, including game consoles as well as television monitors, and other devices that can be interfaced to external equipment, devices and/or accessories.
- game consoles as well as television monitors
- FIG. 1 is a block diagram of an embodiment of the Accessory Control Interface (ACI) ASIC that is constructed in accordance with this invention
- Fig. 2 is a block diagram showing the ACI ASIC of Fig. 1 installed within an exemplary accessory (a headset having speakers and a microphone), and the coupling between the ACI ASIC and a mobile terminal that includes a baseband ASIC;
- Fig. 3 are waveform diagrams that illustrate the format of a single logical 1 bit and logical 0 bit (Fig. 3 A), the format of a transmission of a byte (8-bits) in bit serial format (Fig. 3B), the format of two data bursts (active mode) separated by a mobile terminal sleep mode period (Fig. 3C), a Reset pulse (Fig. 3D), a Learning Sequence (Fig. 3E), and an Interrupt (Fig. 3F);
- Fig. 4 illustrates an exemplary waveform that would appear on the bit serial data line shown in Fig. 2 from the time the accessory is inserted or attached to the mobile terminal to the time that it is removed or detached from the mobile terminal;
- Fig. 5 illustrates a basic command data sequence, and the format of the initial command byte of the sequence
- Fig. 6 is a waveform diagram that also illustrates an interrupt comparator used with a pull-up resistor that is switchably connected to the bit serial data line.
- Fig. 1 illustrates a block diagram of one (non-limiting) embodiment of the Accessory Control Interface (ACI) ASIC 10 that is constructed in accordance with this invention.
- the ACI ASIC 10 includes a control logic block 12, an I/O port control registers and data registers block (I/O block) 14, an authentication block 16, a non-volatile memory 18 (e.g., 32 bytes) having a read/write (R/W) with password memory portion 18A and a normal R/W portion 18B.
- the memory could be a EEPROM or other type of suitable memory device or devices.
- a clock preferably implemented as a low cost, on-chip resistor/capacitor (RC) oscillator 19 (frequency range about 20kHz to about 60kHz) is also provided.
- RC resistor/capacitor
- the output of the RC oscillator 19 feeds the control logic block 12, and thus forms the master timing signal for the operation of the ACI ASIC 10, as well as controlling the timing of bit serial data that passes over the communications port 10A (preferably one signal line that operates in an asynchronous bit-serial format, as described in further detail below.
- a plurality of programmable I/O lines 10B are also provided for controlling circuitry within the accessory that the ACI ASIC 10 is installed within (when programmed as outputs), or for reading back status and other signals (when programmed as inputs).
- the authentication block 16 executes an authentication algorithm, preferably a challenge response type of algorithm, and can be used to verify that a given accessory is an authentic accessory, and not one provided from unauthorized third parties.
- an authentication algorithm preferably a challenge response type of algorithm
- the ACI ASIC 10 is shown installed within an accessory 20, in this non-limiting example a headset accessory that includes left and right audio transducers (miniature speakers) 22 and 24, respectively, and a microphone 26.
- a multi-wire cable 42 can be used to carry the required analog and digital signal lines between the mobile terminal 30 and the accessory 20. All of these signal lines are interfaced to suitable circuitry in the mobile terminal 30, shown for convenience as a baseband ASIC 32.
- the details of the circuitry that drives the audio transducers 22, 24, and that receives the audio signal from the microphone 26, are not germane to an understanding of this invention.
- R coupled between signal line 10A and circuit ground
- R PU may be a 56k ohm resistor and R PU may be in the range of about 100k to about 120k ohms.
- R and R PU together form a resistor voltage divider network.
- a single bit time T can be in the range of about 500 microseconds to about 1500 microseconds, depending on the frequency of the RC oscillator 19. More particularly, in a presently preferred, but non-limiting embodiment of this invention the control logic 12 operates with 30 clock cycles from the RC oscillator 19 to form the bit time. Assuming the lower frequency of 20kHz, one clock cycle is 50 microseconds, and one bit time T is 30*50 microseconds or 1500 microseconds. Assuming the higher frequency of 60kHz, one clock cycle is 16.6 microseconds, and one bit time T is 30* 16.6 microseconds or 498 microseconds.
- signal transition periods preferably signal other events. For example, and as is shown in Fig. 3D, holding the signal line 10A low for a period T reset (points B and E in Fig. 4) signals a warm (non-power on) reset state.
- the data signal line 1 OA is also controlled to signal a Learning Sequence, as is illustrated in Fig. 3E.
- the Learning Sequence specifies the duration of T for an ensuing data transmission. Data transmission always begins by sending a logic one, which specifies the bit time T. This sequence is sent after a reset and at the beginning of a response from the ACI ASIC 10 (point B in Fig. 4).
- a low Start pulse period (S) starts each byte transmission for synchronization, and is greater than some minimum period (e.g., 50 microseconds). The start of the byte pulse is always generated by the sender of the byte.
- the data signal line 10A is also controlled to generate an Interrupt from the ACI ASIC 10, as shown in Fig. 3F. Assume that the data signal line free state is a logic zero, the ACI ASIC 10 then generates a pull-up pulse of duration T int if the following conditions are fulfilled: an interrupt option bit has been set in one of the control registers 14; the data signal line 10A has been free for period T inten (for example, for 200 internal clock cycles generated by the RC oscillator 19); and the state of the ASIC pin has been loaded into one of the data registers 14.
- Fig. 5 illustrates a basic command data sequence, and the format of the initial command byte of the sequence.
- the number of data bytes following the command byte are a function of the command.
- the first six bits specify an address to read/write in the memory 18, when the state of the Command Selection bit is in a first state (the Read/Write bit specifies read or write), while the first six bits specify a command, when the state of the Command Selection bit is in the other state.
- Exemplary commands include, but need not be limited to: Authentication Challenge, Authentication Response, Read Write an Interrupt Option I/O register 14 A, Read/Write a Data Direction I/O register 14B, Read/Write a Port I/O register 14C and Read a Latched I/O Port register 14D.
- the Authentication Challenge command (write) is followed by six data bytes (a 48- bit challenge word is presently preferred to input to the Authentication block 16), while the Authentication Response command is followed by three data bytes (a 24-bit response word is presently preferred to output from the Authentication block 16).
- the R/W I O register commands are all followed by a single byte, as these registers are, in the current embodiment, one byte in width.
- the data byte is sourced from the mobile terminal 30.
- the mobile terminal 30 sends the appropriate command byte on the data signal line 10A for specifying the I/O register to be read from, and the ACI ASCI 10 responds on the data signal line 10A with the data byte read from the specified I/O register location.
- the returned data byte is prefaced with the Learning Sequence (see Fig. 3E) that specifies the bit time T. Note as well that for a read of the EEPROM 18 the first byte returned from the ACI ASIC 10 is prefaced with the Learning Sequence, and the specified bit time T applies to the bits of the first returned data byte and any other returned bytes for that read operation.
- control logic block 12 is enabled to inform the data bit reading logic of the mobile terminal 10 of the duration of the bit time T for the impending data transfer, and the data bit reading logic is enabled to adjust the T/2 timing of its sampling of the data signal line 10A accordingly, thereby ensuring accurate reading of the transferred bits.
- the pin state can be read from the I/O data register 14C.
- An internal pull-up resistor is preferably supplied for the I/O pins. If the interrupt enable bit is set from the Interrupt Option register 14 A, and a state change in the I/O input pin occurs, the ACI ASIC 10 generates the Interrupt pulse to the data signal line 10A (see Fig. 3F).
- the ACI ASIC 10 instead latches the I/O pin input states to the Latched I/O Port register 14D after a delay (preferably about 20 milliseconds), and then generates the Interrupt pulse to the data signal line 10A.
- This mode of operation is useful, as an example, for debouncing accessory 20 switch contact closures.
- Note in Fig. 3C that between two data transfer active modes is a mobile terminal sleep mode. Each active period can include a Command byte (read or write) and at least one data byte.
- the bit timing in the ACI ASIC 10 is preferably 30 clock cycles of the RC oscillator 19, which is possible to be read using the timing of the sleep clock (e.g., 32kHz) of the mobile terminal 30.
- the mobile terminal 30 sends a Reset pulse (Fig. 3D) to the ACI ASIC 10 on the data signal line 10A, and the ACI ASIC 10 responds with the one bit Learning Sequence (Fig. 3E), enabling the mobile terminal 30 to adapt its bit receive timing (based on the 32 kHz sleep clock).
- the memory 18 preferably stores data descriptive of the features of the accessory 20.
- data descriptive of the features of the accessory 20 As an example, and assuming the headset accessory, there may be a one row display having 15 characters and four user-controlled switches or buttons, such as Answer/Call, Volume Up and Volume Down.
- Other stored parameters can include audio parameters such as echo cancellation on/off, gains and equalizations. All of this information can be communicated between the accessory 20 and the mobile terminal 30, enabling the mobile terminal 30 to configure and operate with a wide range of accessories, including accessories that are released for sale after the mobile terminal 30 is placed into service.
- the use of the single bit serial data line 10A is also an advantage that accrues from the use of this invention, as this one signal line can be used for transferring data bidirectionally between the mobile terminal 30 and the accessory 20 containing the ACI ASIC 10, as well as for accessory insertion and removal detection, as well as for the adaptation of bit timing, reset and interrupt signalling. While described in the context of the accessory 20 and ACI ASIC 10 being connected to the mobile terminal 30, it should be realized that the ACI ASIC 10 could be interfaced with other types of devices, such as a portable computer device, or a pager, or a PDA, or a home electronics device (including a game console), or any type of device that can be used with an attachable accessory device. In any of these embodiments the controlling device may be simply referred to as a master device, and the ACI ASIC 10 and the associated accessory as a slave device.
- the teachings of this invention are also not intended to be limited in scope by, as examples, any of the specific frequencies, time periods, numbers of bits, numbers of bytes, types of commands, numbers of signal lines or registers and so forth that were discussed above.
- the ACI device is also not constrained to being implemented as an ASIC, as any suitable type of single chip or multiple chip integrated circuit embodiment can be used.
- the various blocks can be implemented in a number of suitable ways.
- the control logic 12 could be implemented as combinatorial logic circuits, or as a state machine, or as a suitably programmed microprocessor core.
- the oscillator 19 could be implemented using discrete resistor and capacitor components, or it could be implemented using a crystal or a resonator or any suitable frequency signal generator.
Abstract
Description
Claims
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03743938A EP1483871A4 (en) | 2002-03-08 | 2003-02-13 | Accessory control interface |
CN038054485A CN1640083B (en) | 2002-03-08 | 2003-02-13 | Accessory control interface |
JP2003575585A JP2005520402A (en) | 2002-03-08 | 2003-02-13 | Accessory control interface |
CA2476981A CA2476981C (en) | 2002-03-08 | 2003-02-13 | Accessory control interface |
BR0303340-6A BR0303340A (en) | 2002-03-08 | 2003-02-13 | Interface between master device and slave device, interface circuit for coupling slave device to master device, and method for communicating between master device and slave device |
DE10391056T DE10391056B4 (en) | 2002-03-08 | 2003-02-13 | Accessory control interface |
KR1020047013615A KR100928905B1 (en) | 2002-03-08 | 2003-02-13 | Accessory control interface |
AU2003252811A AU2003252811A1 (en) | 2002-03-08 | 2003-02-13 | Accessory control interface |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US36290802P | 2002-03-08 | 2002-03-08 | |
US60/362,908 | 2002-03-08 | ||
US10/245,053 | 2002-09-16 | ||
US10/245,053 US6742061B1 (en) | 2002-03-08 | 2002-09-16 | Accessory control interface |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2003077504A2 true WO2003077504A2 (en) | 2003-09-18 |
WO2003077504A3 WO2003077504A3 (en) | 2003-12-18 |
Family
ID=27807589
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2003/000548 WO2003077504A2 (en) | 2002-03-08 | 2003-02-13 | Accessory control interface |
Country Status (10)
Country | Link |
---|---|
US (2) | US6742061B1 (en) |
EP (1) | EP1483871A4 (en) |
JP (1) | JP2005520402A (en) |
KR (1) | KR100928905B1 (en) |
CN (1) | CN1640083B (en) |
AU (1) | AU2003252811A1 (en) |
BR (1) | BR0303340A (en) |
CA (1) | CA2476981C (en) |
DE (1) | DE10391056B4 (en) |
WO (1) | WO2003077504A2 (en) |
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- 2003-02-13 BR BR0303340-6A patent/BR0303340A/en active Pending
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- 2003-02-13 JP JP2003575585A patent/JP2005520402A/en active Pending
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- 2003-02-13 CA CA2476981A patent/CA2476981C/en not_active Expired - Fee Related
- 2003-02-13 WO PCT/IB2003/000548 patent/WO2003077504A2/en active Application Filing
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WO2005041548A1 (en) * | 2003-10-28 | 2005-05-06 | Nokia Corporation | Audio block |
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Also Published As
Publication number | Publication date |
---|---|
CA2476981A1 (en) | 2003-09-18 |
US7167935B2 (en) | 2007-01-23 |
CN1640083B (en) | 2010-09-29 |
CA2476981C (en) | 2013-05-28 |
JP2005520402A (en) | 2005-07-07 |
AU2003252811A8 (en) | 2003-09-22 |
AU2003252811A1 (en) | 2003-09-22 |
EP1483871A2 (en) | 2004-12-08 |
WO2003077504A3 (en) | 2003-12-18 |
US20040250002A1 (en) | 2004-12-09 |
DE10391056T5 (en) | 2004-04-22 |
DE10391056B4 (en) | 2006-07-27 |
EP1483871A4 (en) | 2010-08-04 |
KR20040089690A (en) | 2004-10-21 |
BR0303340A (en) | 2004-09-14 |
KR100928905B1 (en) | 2009-11-30 |
CN1640083A (en) | 2005-07-13 |
US6742061B1 (en) | 2004-05-25 |
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