WO2003079202A1

WO2003079202A1 - Memory system using directional coupler for address

Info

Publication number: WO2003079202A1
Application number: PCT/JP2003/002428
Authority: WO
Inventors: Hideki Osaka; Toyohiko Komatsu
Original assignee: Hitachi, Ltd.
Priority date: 2002-03-19
Filing date: 2003-03-03
Publication date: 2003-09-25
Also published as: JP4173970B2; JP2003271538A

Abstract

It was difficult to provide high-speed memory systems of SDRAM because, while data were bus-wired for each memory, address signals were equally wired over the entire memory chip, which resulted in heavy load and waveform distortion. Besides, the access latency was long because of address buffers. In order to realize a high-speed addressing, an address signal is wired from a memory controller to each module, and a directional coupler is used in each module. In order to realize a shorter read access latency, an address is inputted from a far end of the module in a motherboard and is daisy-chain-coupled to each memory on the module. Data are wired from the closest to the farthest of the memories in the motherboard, and the sums of the address signal propagation delay time and the data signal propagation delay time for the respective memories are equalized.

Description

Memory system using directional coupler for moon ^ 鲁 address

The present invention relates to a technology for signal transmission between elements such as a multiprocessor and a memory (for example, between digital circuits constituted by CMOS or the like and functional blocks thereof) in an information processing apparatus. Background art

In order to transfer data at high speed by connecting a large number of nodes, the propagation delay time of wiring cannot be ignored. In particular, in DDR-SDRAM (Double Data Rate Synchronous DRAM), the operating frequency of data is twice that of address, and it is becoming difficult to increase the speed due to the influence of noise on the bus wiring. To solve this problem, Japanese Patent Application No. 5-238087 “Non-contact bus”, Japanese Patent Application No. 10-3 0 6 6 4 5 “Directional coupling type bus system”, Japanese Patent Application No. 11-1-1 3 0 9 5 7 Directional-coupled bus system, Japanese Patent Application No. Hei 2 00 0 -1 2 6 2 3 4 Directional-coupling bus system, Japanese Patent Application No. Hei 2 0 0 0 -1 2 6 2 3 4 There was a “directional connection bus system”. Disclosure of the invention

If the path wiring length is long, the propagation delay of the data signal differs between the module near the memory controller and the module far from the memory controller. For this reason, a method of distributing clock signals with a common phase has become unable to provide sufficient timing margin, and in information processing devices, memory access is generally more readable than write access. Therefore, improving the latency of read access improves the information processing performance. As a memory bus method to solve this problem, there is Japanese Patent Application No. 2000-0—15 2667 “Read priority memory system”. Fig. 14 shows one form of this basic method.

DRAM 10 in memory controller 1 and memory module 2 0—1, 20—2 In order to prioritize read access, the direction of propagation of the clock signal is not from the memory controller 1 but from the DRAM 10 in the farthest module 20-4. The clock signal 30 is wired so as to have the same propagation delay time as the signal. As a result, in the memory controller 1, the propagation delay time of the clock signal 30 and the signal wiring 31 of the read data signal becomes the same, so that the read data processing in the memory controller 1 can be performed without waiting time. As a result, the read access performance could be improved as a system.

However, as the speed of the DRAM increases, the speed of the address / command signal increases even though it is half that of the data signal, so that the noise of the address signal wiring is becoming noticeable. For example, in the case of 100 Mbps (Megabitpersecond) in DDR-SDRAM, the address transfer rate is 50 Mbps, but if the data transfer rate is increased to 1 Gbps, it is 500 Mbps. Become.

Figure 15 shows the wiring of the conventional DDR-SDRAM memory system. 1 is a memory controller (MC), and 20-1 to 20-4 are memory modules with multiple memories 10 mounted. In this figure, four DRAMs 10 are installed in one memory module, but the number of memories 10 may be more or less depending on the system requirements. The signals transmitted / received from the MC 1 to the memory 10 include a data signal 31, an address / command signal 32, a chip select 33 (hereinafter a CS signal 33), and a clock signal 30. In these wirings, the data signal 31 is wired to the memory 10 in the module 20-1 to 20-4 on the same Y coordinate in Fig. 15 respectively. And the clock signal 30 is the same. However, the address / command signal 32 is branched to all chips. The other chip select signal 33 is wired for each module.

In Figure 15, memory access from MC 1 is performed as follows. MC 1 transmits address command signal 32 and CS signal 33 in synchronization with clock signal 30. Only the memory module selected by the CS signal 33 is activated, and the address input to the DRAM 10 in this memory module is written to the memory cell in the DRAM 10 in response to the command signal 32. Perform read and read operations. this Therefore, even if the same address / command signal 32 is input to all memories 10, since the memory module is selected by the CS signal 33, the data signal 31 So-called output collision does not occur.

However, in the address / command signal 32 used in the prior art as shown in FIG. 15, the address' command signal 32 shared the wiring to each module 20-1 to 20-4 and was branched. . In such a wiring method based on branching, when a high-speed operation exceeding 200 Mbps is performed, there is a problem that waveform distortion is large and high-speed signal transfer becomes difficult.

In another design, each module 20—1? In some cases, a buffer was provided in 20-4. As a result, the wiring of the address' command signal 32 goes from the MC 1 to the buffer input in each module 20-1 to 20-4, and the load on the wiring is distributed more than when there is no buffer. Was.

However, unlike data signal 3 1, module 20-1? 2 0—Propagation delay time of address command signal 32 due to passing through the buffer in 4 takes extra time to pass through the buffer, and the access of address command signal 32 is slowed, and the system issues the address command signal. However, there is a problem that system performance cannot be obtained because the speed is limited by the latency.

As another problem, when the address' command signal 32 is distributed to each memory module 20-1, 20-2, the address command signal 32 is composed of the data signal 3.1 and the cloak signal 3. Since the wiring method and wiring length of 0 are different, the propagation delay time from MC 1 to each module 20 1 1 to 20-4 was different. Therefore, as the distance from the address output pin of MC 1 increases, the phase difference between the clock signal 30 and the data signal 31 increases, and the wiring delay time from MC 1 depends on the memory location. However, the timing control in MC 1 was complicated. This complicates evening design.

The present invention is to solve at least one of the above problems.

In a memory system to which multiple memory modules are connected, To increase the speed, address signals were wired for each module from the memory controller, and a directional coupler was used in the module.

In other words, the address / command signal is distributed individually for each module. As a result, the branch of the address / command signal is eliminated, and the waveform distortion is extremely reduced. Thus, the address signal operates at a high speed.

In addition, even if a buffer is not used in the module, it is possible to propagate a signal only by wiring without branching.

Further, by providing a directional coupler for the address' command signal in the memory module, the address propagation delay speed can be further increased. This is because the input capacitance of L S I connected in a path looks small due to coupling. For this reason, the propagation delay speeds of the data signal and the address / command signal become almost equal, and the designing of the timing of the wiring on the substrate becomes easy. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a diagram illustrating a first embodiment.

FIG. 2 is a circuit diagram of the first embodiment.

FIG. 3 is an internal block diagram of the memory controller according to the first embodiment.

FIG. 4 shows a wiring method when one module according to the second embodiment is provided.

FIG. 5 shows another wiring method of the second embodiment.

FIG. 6 shows a module wiring system according to the third embodiment.

FIG. 7 is a timing chart of the address signal of FIG. 6 (B).

Fig. 8 shows a wiring method that gives priority to light data overnight.

FIG. 9 shows a connector provided with an erroneous insertion prevention mechanism.

FIG. 10 shows the substrate configuration of the first embodiment. 'Figure 11 shows an address / command input circuit with adjustable impedance. FIG. 12 shows a one-way data transfer bus wiring method using a directional coupler.

FIG. 13 shows the impedance adjustment sequence of the address / command signal. Figure 14 shows the conventional read access priority wiring.

FIG. 15 is a circuit connection diagram of a conventional example. Fig. 16 shows the signal propagation time relationship between the signal pulse propagating in the main coupling line and the backward crosstalk signal pulse induced in the sub coupling line in the coupler of Fig. 6 (E).

FIG. 17 is a diagram illustrating CTT. BEST MODE FOR CARRYING OUT THE INVENTION

A first embodiment will be described with reference to FIG. Reference numeral 9 denotes a memory bus, which has components related to memory access described below. Reference numeral 100 denotes a board (mother board) on which components constituting the memory system are mounted, and FIG. 1 is a bird's-eye view thereof. In FIG. 1, only the components and wiring constituting the memory bus 99 are shown. Reference numeral 1 denotes an LSI chip (hereinafter, MC: Memory Controller) having a memory controller control mechanism, which is mounted on a motherboard 100. 2 0—1? 2 0—4 is a memory chip 1 0—1? This is a memory module equipped with multiple 10-8. The memory chip is, for example, DRAM. Module 20-0-1 to 20-4 have power / ground pins and signal pins for data / address signals, address / command signals, and clock signals. In FIG. 1, four memory modules are mounted on the motherboard 100. Module 2 0—1? Memory in module 0 4—1 0—1? Eight 10-8 are mounted. The objectives and effects are the same regardless of whether this module is four or more or less, and whether the number of memories is eight or less.

Reference numeral 31 denotes a data signal for transmitting data between the MC 1 and the memory 10-1 to 10-8. The data signal is transmitted using a directional coupler (C 1) formed on the mother board 100. The signal is transmitted by propagation. Hereinafter, signals and signal lines are referred to as signals unless otherwise specified.

C 1 shown by a dotted line in FIG. 1 is one of the directional couplers formed on the motherboard 100, and this directional coupling line is a two-wire having a finite parallel length, That is, it is composed of a main coupling line and a sub coupling line. The directional coupler C 1 in FIG. 1 serves to connect the data signal of MC 1 to the data signals of the memories 10 to 8 in the memory module 20-1, but also to the data signals of other memory modules and memories. The motherboard 100 has a directional coupler that performs the same function. These are not shown in the figure for simplicity. Here, the configuration of the directional coupler C 1 is such that the main coupling line is a data signal 3 1 It is wired inside the motherboard 100, and the far end of the wiring is matched and terminated by a terminating resistor. Is the sub-coupling line each module 20 -1? It is connected to the data signal pins 20-4 via a connector 90, and the other end is terminated by a resistor.

This directional coupling line is based on the above-mentioned prior art, Japanese Patent Application No. 5-23038 “Non-contact bus”, and Japanese Patent Application No. Hei 10-30-0664 “Directional coupling type path system”. , Japanese Patent Application No. 1 1 -1 3 0 9 5 7 "Directional coupling type path system", Japanese Patent Application No. Hei 2 00 0 -1 2 6 2 3 4 "Directional coupling type bus system", Japanese Patent Application No. 20 0 0 -1 2 6 2 3 4 Same as “Directional coupling bus system”.

32 is an address command signal. Address · Command signal 3 2 is from motherboard 1 in motherboard 100 to each module 20-1? Wired to 20-4. The number of each address' command signal 32 wired to each module 20-1? 20-4 is the number of memory modules 20-1? 2 0—4 Same as the number of command signal pins. The address wired to each module 20-1 to 20-4. The number of command signals 32 depends on the storage capacity of the memory 10 in the module 20-1 to 20-4. In this case, there are about 20 to 25 bits. In FIG. 1, the address / command signal 32 of about 20 bits is wired to each of the modules 20-1 to 20-4 without branching. Unlike the data signal 31, the address ′ command signal 3 2 does not form a directional coupling line in the motherboard 100, and one wiring is connected from MC 1 to one signal. Each module 2 0—1? Wired to connector 90 for 20-4.

Although not shown in FIG. 1, the clock signal 30 is also transmitted from MC 1 to each module 20 -1? Wired to 20-4. Is this wiring for each module 20-1? It has the same wiring length as the address command signal 32 for 20-4. For this reason, the address / command signal 32 and the clock signal 30 have the same propagation delay time as viewed from the MC 1 and each memory module 20—1? Reach 2 0—4. Module 20-1? The data signals in 20-4 are wired with equal length from the pins of the module to the memory 10-1-10-8. The address / command signal 32 and the quench signal 30 in the module 20-1 to 20-4 form a directional coupler in the module. Address' Command signal 32 rises from the lower right to the upper side in FIG. Is lined. The address / command signal 32 is not shown, but is terminated at the far end with a resistor to eliminate reflection. The wiring of the address and command signal 32 in this module 20—1 to 20—4 constitutes the main coupler of the directional coupling line, and the sub coupler that is wired close to and parallel to it. Memory 10 is connected. With such a configuration, the address' command signal 32 in the module 20-1 to 20-4 is transferred from the MC 1 to each memory 10-1 to 10-8 using the directional coupler. Transferred.

As described above, since the address' command signal 32 in the modules 20-1 to 20-4 uses a directional coupler, signal distortion due to branching is extremely small. This indicates that the speed of the address / command signal 32 can be easily increased.

Next, it is explained that the skew (variation in transmission time) due to the difference in wiring length between the MC 1 and the memory 10-1-1-10-8 in each module 20-1-4-20-4 is small in read access. .

In FIG. 1, MC 1 is located approximately in the long side direction (x direction) of modules 20-1 to 20-4. The data signal 3 1 on mother port 1 0 0 is pulled out from MC 1 in the X ′ direction, bent in the y direction, and the module 2 0-1? Wired to 20-4. The address' command signal 32 in module 2 0-1? 2 0-4 is also routed in the X direction. For this reason, the memory 1 0-1 -1 0 -8 in the module 20 -1 2 20-4 has a near-far distance with respect to the MC 1. Even if the memory is mounted in the same module, the data signal 31 has a short propagation delay time for the memory 10-8 near the MC 1 and a long propagation delay for the memory 10-1 near the MC 1. It's time. The difference in the propagation delay time of this data signal 3 1 from MC 1 to the memory 10-1 and 10-8 is proportional to the wiring length difference of the data signal 31 in the mother port 100, and this wiring It is equal to the propagation delay time difference obtained by multiplying the difference by the propagation speed (Vp) of the motherboard 100. Similarly, address' command signal 3 2 is module 2 0-1? The memory is connected to memory 1 0—1, 1 0—2 ···, 1 0—8 in order from the right end of 2 0—4, so the memory 1 0-8 closest to MC 1 has the longest propagation delay time It has the shortest propagation delay time for the memory 1 0 -1 farthest (right side) from MC 1. The difference in propagation delay time between this memory 10-1 and 10-8 is the module 20-1? 20-4 It is equal to the propagation delay time difference obtained by multiplying the difference between the wiring length of the command signal 32 and the propagation speed.

Usually, the materials of the motherboard 100 and the modules 20-1 to 20-4 are of the same glass epoxy resin system and have the same relative permittivity, that is, the same propagation velocity. In the case where multiple LSIs are connected to one wiring via a path, the propagation speed is slowed by the input capacitance of the LSI. However, in the path connection using the directional coupler of the present embodiment, the input capacitance of the LSI is reduced. Since it is not directly connected to the main coupling line, there is almost no delay in the propagation speed. For this reason, the propagation delay time difference with respect to the MC 1 is proportional to the wiring length difference in the modules of the memories 10-1 to 10-8. That is, since the propagation speed is the same for the data signal 31, the address' command signal 32, and the clock signal 30, the propagation delay difference between the memories 10-1 to 10-8 is proportional to the wiring length difference. Will be.

In the configuration in Fig. 1, the wiring from the MC 1 to each memory 10-1 to 10-8 in the same module is the sum of the wiring length of the address command signal 32 and the wiring length of the data signal 31. Are almost equal. The difference is only the wiring length difference of the data signal 31 in the y direction in FIG. As a result, in the read access from the MC 1, the time from the read access request time from the MC 1 to the time when the data signal from each memory 10 is received by the MC 1 is substantially equal. Therefore, in the configuration of the present embodiment, there is no need to adjust the skew between the memories 10 for read access, and timing design is easy. Therefore, in a system in which the number of read accesses is much larger than the number of write accesses by the information processing device, the system performance can be greatly improved.

Figure 2 shows the circuit diagram corresponding to Figure 1. Elements having the same functions as those in FIG. The same applies to the following description.

In FIG. 2, the memory modules 20-1 to 20-4 are indicated by dotted lines to improve visibility. The wiring connection is the same as in Fig. 1, but the explanation is focused on the parts not explicitly shown in Fig. 1.

Data signal 31 is derived from MC 1 and is terminated by a resistor at the farthest end. This terminal portion is indicated by a white square. In the termination, one end of the termination resistor (R tt) is connected to the termination power supply (VTT), and the other end is connected to the wiring. Of the directional couplers formed in the motherboard 100, the sub-coupler is All are terminated with signal 31. Here, “forward” refers to the direction in which signals flow through the main coupling wiring. In FIG. 2, the directional coupler and the terminating resistor of the data signal 31 are configured and mounted in the mother node 100.

Also, the address' command signal 32 and the clock signal 30 are drawn from MC 1 to the right end as shown in Fig. 2, and the module 20-1? Folded to 20-4 and wired. Address · Command signal 32 and clock signal 30 are module 20 -1? A directional coupler is constructed in 20-4, and the main direction coupling line is terminated at the far end by a resistor. The other end of the sub-coupling line connected to each of the memories 10-1 to 10-8 is also terminated.

In FIG. 2, the signal related to the memory access of MC 1 operates as follows. 1 ^ (: 1 has address 1, command signal 32 output signals written as 8, 1, A2, A3, A4. Each address and command signal 3 2 A1? It is wired to 2 0—1 to 20—4, and the address' command signal 32 consists of a 20 to 25-bit signal depending on the memory module. Also, MC 1 has D1 to D4 input / output signals, and clock signal 30 also has M (31 has 〇1 to C4 output signals).

The MC 1 connects a system bus 98 and a memory bus 99 such as an I / O bus for connecting a processor bus and peripheral circuits, and reads and writes the memory bus 99 according to a memory access request of the system path 98. The memory bus 99 comprises an address / command signal 32, a data signal 31 and a clock signal 30 for reading from and writing to the memory. Clock signal 30 continues to be transmitted from MC 1 after power-on. Of course, in the power saving mode such as the sleep mode, the operation may be temporarily stopped.

MC 1 selects one of A1 to A4 of the address' command signal 3 2 in MC 1 corresponding to the requested address, and the module 20 0—1 to 20 connected to this address / command signal. One of _4 will be selected. In other words, A1 to A4 of four address / command signals 32 in MC 1 also serve as CS signals for each module. In other words, the CS signal is unnecessary in this memory system, and the circuit, wiring, and pins for this signal are not required, which contributes to cost reduction. Address · Command signal 3 2 has two functions, address mode and command mode. But in command mode, memory 10-1? Command signal to initialize memory 10 to 10-8 or to auto-refresh. Acts as an address mode for memory access. Address during read accessCommand signal 32 is output from MC 1 together with other control signals in synchronization with clock signal 30, and the address corresponding to the address requested for access is divided into CAS and RAS signals. It is transmitted to each memory 10. The data signal 31 outputs data corresponding to the requested address from the memory cells of the memory 10-1 to 10-8. This data is transmitted to MC 1 through the data signal 31 wiring.

In write access, the address / command signal 32 is output from the MC 1 together with other control signals in synchronization with the clock signal 30, and the address corresponding to the address for which access is requested is divided into CAS signals and RAS signals for each memory. It is transmitted to 1 0— 1? 1 0-4. Here, is the write data for each memory 10-1? 1 0—Each memory 1 0-1 at the time the clock signal 30 arrives? The time is adjusted to reach 10-8 and output from MC1. The MC 1 accesses each memory 10-1 to 10-8 when another device such as a processor not shown here requests a memory access via the system bus 98. The unit is performed for each module.

Next, the timing control of the data signal 31 during write access and the internal structure of the MC 1 will be described with reference to FIG. MC 1 receives the system clock 35. This is distributed to a plurality of blocks in the MC 1 via a phase adjustment circuit 1 A such as a PLL (Phase Lock Loop) and a DLL (Delay Lock Loop). Input / output circuits (I / O circuits) for memory access are shown on the right side of MC 1; output circuit for clock signal 30; output circuit for address 'command signal 32'; and data signal 31 I / O circuit. Is data signal 3 1 D 1 in Figure 3? Grouped into D4, which is connected as shown in Figure 2.

All signals on the memory bus 99 are synchronized with the clock φ by a flip-flop circuit 1C to communicate with the core logic 1L. This clock signal Φ is an output signal of the phase adjustment circuit 1A. Clock signal 30 is output in synchronization with clock φ. Similarly, the address command signal 32 is synchronized with the clock φ. Output.

The data signal 31 has a different circuit configuration between the input and output. When the wiring as described above is provided on the substrate, all data signals 31 are input to the data input circuit 1D from the outside at almost the same timing. Therefore, the data input circuit 1D can be latched at the same timing. For this reason, there is no need for extra latency for resynchronization in the MC1 internal clock φ. For this reason, the circuit configuration for data input is simple and the area is small, inexpensive and highly accurate.

On the other hand, it is necessary to provide a delay time difference for each data signal 31 for write data. 1 C of the data output flip-flop in MC 1 is output in synchronization with clock ψ. 1B is an adjustable delay circuit (delay time adjustment circuit) that adjusts the delay amount for each write access according to the access request address. The delay time adjustment circuit 1B is the module 20-1 in Fig. 2. ? Memory in 20-4-1 0-1? The delay time is adjusted so that the write data arrives at the same time as the clock signal 30 distributed to 10-8. The amount of delay varies depending on the module, and also varies with the location of the memory 10 in the module. It is the control circuit 1F that controls the delay time. The control circuit 1F has a register 1G for each bit of data 31 and this register value corresponds to the delay time of the delay circuit 1B. That is, the control circuit 1F can control the delay time for each bit by changing the register value of the register 1G. The register value of this register 1G is set before writing data is output. It should be noted that the delay circuit 1B can make the delay time variable by preparing two inverters as one set and preparing multiple stages, and selecting a stage number equal to or close to the desired delay time. This selection is made by setting the number of stages of the delay circuit in the register 1G in the control circuit 1F.

For example, when writing to module 20-1 in Fig. 2 and writing write data to the farthest memory 10-1 from the viewpoint of MC1, the clock signal 3 The delay circuit 1B generates a small delay amount having a small delay time difference between 0 (C 1) and the data signal 3 1 (D 1), and outputs the data signal 3 1 (D 1) at almost the same timing as the clock signal 30. Just output it. Here, the delay amount generated by the delay circuit 1B is equal to the propagation delay time difference when the clock signal 30 (C1) wiring and the data signal 31 wiring from the MC 1 to the memory 10-1 are propagated. In this way memory 1 0-1 In this case, the data signal 31 (D) arrives at the same time as the clock signal 30 and the two signals have the same phase.

However, for the memory 1 0-8 nearest to MC 1, the non-negligible propagation delay time of the clock signal 30 in the module 20-0-1 from the memory 10-1 to the memory 10-8. There is. In order to make the phases of the clock signal 30 and the data signal 31 (D 8) coincide with each other in the memory 10-8, the data signal 31 (D 8) may be output later by the time of the difference. By setting this delay amount in the register 1 G for the data signal 31 (D 8) prior to output, the delay circuit 1 B delays the signal.

Similarly, D2 and D3 have a wiring delay time delay of clock signal 30 on module 20-1. By doing so, the clock signal 30 and the data signal 31 have the same phase in all the memories 10 -1 to 10-8, and the timing for the write operation can be accurately adjusted. . The propagation delay time of data signal 31 for module 20-4 is the same as that of module 20-1 that passes through the four directional couplers for data signal 31 1 Signal 3 1 arrives late as a whole. Therefore, the data signal 31 is output to the module 20-4 earlier by the delay time. Since this delay time is constant for all of Dl to D4 with respect to the data signal 31, a certain constant value may be added as an offset.

The delay time required for the write data in MC 1 differs for each module 20-1-20-4 and for each memory 10-1-10-8. It is only necessary to have the star values in the form of a table. This register value should be set prior to write access. Moreover, since the address of the MC 1 is known before the output of the write data, it is easy to change the register value and change the delay amount of the delay time adjusting circuit 1B required for the conversion.

The relationship between the register 1G register value and the delay time is shown, but since the dielectric constant of the mother board 100 is clear, it may be held as a fixed value at the design stage, or the dedicated wiring for MC 1 The measurement may be performed by providing a circuit. Of course, the latter is more accurate for manufacturing parachuting. Further, in the present embodiment, the delay adjustment circuit 1B is provided between the flip-flop l'C and the driver. However, the delay adjustment circuit 1B is arranged at an arbitrary position where the same effect as described above is obtained. It is possible. The same effect can be obtained by arranging a flip-flop, for example, on the MC 1 side with respect to the flip-flop 1 C. In this case, since some of the data signals 32 can share the delay adjustment circuit 1B, there is an effect that the circuit scale is reduced.

In this way, read data does not require resynchronization, and has the effect of minimizing latency. Also, for the write data, the data signal 31 can be outputted to each memory 10 in the phase where the clock signal 30 has the timing.

In this way, as described with reference to FIGS. 1, 2, and 3, the address command signal 32 and the clock signal 30 are routed in parallel from the MC 1, and the signal length and data Which memory 1 0—1 is the sum of the wiring length with signal 3 1? By making them equal for 1 0—8, the data in read access can be input with the phases aligned in MC 1. However, the address / command signal 32 is also sent to module 20—1? By wiring every 20-4, there is no module variation in the propagation delay time of the address 'command signal 32'. Also, address' command signal 3 2 to module 2 0-1? Providing a directional coupler within 20_4 for transmission allows transmission of the address of the module 20-1 to 20-4, the command signal 32, and the propagation delay of the motherboard 100 The time is now equal, and the module 1 can capture the data signal 31 in different read accesses with very low skew.

As a second embodiment, a system configuration having only one module will be described with reference to FIG. This embodiment is suitable for a small-sized information processing apparatus such as a notebook-type personal computer, in which the number of mounted computers is one or two. Figure 4 shows a memory path configuration for equipment that requires only one module.

The clock signal 30 and the address / command signal 32 are output from the MC 1 and looped back at the farthest end of the module, and each memory 10-1? Input to address signal pins 1 0—4. Data signal 31 is MC 1 and memory 1 0-1? There is a one-to-one connection between 10-4. Since the data signal 31 is not a bus connecting three or more LSIs, but is a one-to-one connection, no directional coupler is required. In FIG. 4, MC 1 is approximately in the long side direction of memory module 20 (X direction). It is located in. The data signal 31 on the motherboard 100 is drawn from the MC 1 in the X direction, bent in the y direction, and wired to the module 20. The address / command signal 32 in the module 20 is also wired in the X direction. For this reason, near / far occurs at the position of the memory 10 in the module 20 with respect to the MC 1. Even with the memory installed in the same module, the data signal 31 has a short propagation delay time for the memory 10-4 near the MC 1 and a long propagation delay for the memory 10-1 far from the MC 1. Delay time. The difference between the propagation delay times of these two memories is proportional to the wiring length difference of the data signal 31 in the mother port 100, and the propagation speed of the mother port 100 (V p) multiplied by the propagation delay difference.

Similarly, since the address' command signal 3 2 is connected to the memory 10-1 to 10-4 in order from the right end of the module 20, the memory 1 0-4 closest to MC 1 has the longest propagation delay It has time, and has the shortest propagation delay time for the memory 1 0 -1 furthest (right side) to MC 1. The difference between the two propagation delay times is equal to the propagation delay time difference obtained by multiplying the difference between the wiring length of the address / command signal 32 in the module 20 and the propagation speed.

Usually, the mother board 100 and the module 20 are made of the same glass epoxy resin and have the same relative permittivity, that is, the same propagation speed. However, when a plurality of LSIs are path-connected to one wiring, the propagation speed is slowed by the input capacitance of the LSI. However, in the bus connection using the directional coupler of the present embodiment, the input capacitance of the LSI is mainly coupled. Since it is not directly connected to the line, there is almost no delay in the propagation speed. For this reason, the propagation delay time difference with respect to MC 1 is 10 -1? It is proportional to the difference in wiring length within the module of 10-4. That is, since the propagation speed is the same for all of the data signal 31, address' command signal 32, and clock signal 30, the propagation delay time difference between the memories 10-1 to 10-4 is proportional to the wiring length difference. Will be.

In the configuration of Fig. 4, each memory 10 0-1? In the wiring from 10 to 4, the sum of the wiring length of the address' command signal 32 and the wiring length of the data signal 31 is almost equal. The difference is only the wiring length difference of the data signal 31 in the y direction in FIG. As a result, in the read access from the MC 1, the time from the read access request time from the MC 1 to the time when the MC 1 receives the data signal from each memory 10 is read. The time at is almost equal. For this reason, in the configuration of the present embodiment, there is no need to adjust the skew between the memories 10 for read access, and the evening timing design is easy. For this reason, in a system in which the number of read accesses is much larger than the number of write accesses, the system performance can be greatly improved.

If the propagation delay time of the address command signal 32 in the module 20 has a timing margin depending on the system operation frequency, the address command signal 32 is directly stored in the memory 10-1? You may connect them sequentially to —4. When connecting directly as shown in Fig. 5, memory 10-1? Propagation delay time is delayed by the input capacitance of 10_4, but even in such a case, if there is a system timing margin, the propagation speed delay of the address / command signal 32 is allowed within the margin. Can be tolerated. Even in such a case, the re-synchronization loss in the MC 1 is small because the arrival time of the data signal 31 to the MC 1 is almost the same for read access.

With this configuration, the same effect as in the first embodiment can be obtained. That is, the address' command signal 32 and the clock signal 30 are routed in parallel from the MC 1, and the sum of the wiring length of this signal and the wiring length of the data signal 31 is which memory 10-1? By making them equal to 1 0 1 to 8, the phase of the read access data signal 3 1 can be aligned at MC 1. In addition, MC 1 captures data signal 31 in read access with extremely small skew by providing directional coupler in module 20-1? 20-4 to transmit address command signal 32. It became possible. Because module 2 0-1? Although the propagation delay time of the address / command signal 32 in 20-4 is using a directional coupler, the main coupling line is not directly connected to any device, so the propagation speed is the mother port. This is because the propagation speed is the same as 100 and the delay time of both is equal.

A third embodiment will be described with reference to FIG. The purpose of the present embodiment is to arrange the arrival time of the address' command signal 32 in the module to each memory in the order of the position of the memory.

FIG. 6 (A) has wiring for the address' command signal 32, the clock signal 30 and the data signal 31 corresponding to FIG. 5 in the module 20a. That is, address' command signal 32 and clock signal 30 are connected to the connector of module 20a. Are extracted from the edge electrode (pin) that is connected to each memory 10 0-1? 1 0-8 are wired directly in order and terminated at the far end. Data signal 31 from the edge electrode to each memory 1 0 1 1? It is wired with the same length to 10-8. In the case of such a wiring, the number of wirings of the address / command signal 32 is equal to the number of signals, so that high density can be easily achieved. However, there is also a side effect of extending the propagation delay time. Whether this can be used depends on the timing magazine of the system.

FIG. 6B is a module corresponding to FIG. 2 or FIG. FIG. 6 (B) has wiring for the address / command signal 32, the clock signal 30 and the data signal 31 corresponding to FIG. 5 in the module 20a, similarly to FIG. 6 (A). The data signal 31 is wired with equal length from the edge electrode (pin) 25 to each memory 10-1 to 10-8. The address / command signal 32 and the clock signal 30 are drawn from the edge electrode 25 connected to the connector of the module 20a, and the memories 10 0-1 to 10-8 are sequentially passed through the directional coupler. And terminated at the far end. Of the directional couplers, the main coupling wiring is shared by the memories 10 -1 to 10 -8 so that the sub coupling wiring does not overlap. One end of the sub-coupling wiring is each memory 10-1? Directly connected to input pins 10-8 and the other end is matched and terminated by a terminating resistor. In this case, backward crosstalk occurs in memory 1 0—1? 1 0—8 and memory 1 0 -1? 1 0-8 © Reflects at the input pad, so it has the characteristic that approximately twice the signal induced in the sub-coupling wiring is generated. Also, as is clear from the configuration, the address / command signal 32 is transmitted in the order of the memory 10-1, 1, 0-2, 10-3, 10-8, so that it can be read in combination with the first embodiment. Data skew can be minimized.

Fig. 6 (C) is an embodiment in which the terminating resistor is eliminated from Fig. 6 (B) and higher density is achieved. In this embodiment, the sub-coupling line is shared by two memories. The configuration is such that the address / command signal 32 is the main coupling line of the directional coupler and is terminated at the far end. The memory 10 -1 is wired adjacent to and parallel to one side of the main coupling line (about 30 mm). One end of this sub-coupling line is connected to the input pin of the memory 10-1 while the other end is connected to the input pin of the memory 10-3. The input pins of these two memories 10-1 and 10-3 are located at the same position on the package. In addition, the input impedance as seen from the connected pins differs between memory 10-1 and memory 10-3, memory 10-1 is open (Hi-Z), and memory 10-3 is terminated. ing. Similarly, the memory 10-2 and the memory 10-4 share a sub-coupling line, and the input impedance is higher at the side closer to the signal source side of the signal flowing on the main coupling line (memory 10-2), (Memory 10-4) is terminated on the other side. The sub-coupling line shared by the memories 10-2 and .10-4 is opposite to the main-coupling line with respect to the sub-coupling line shared by the memories 10-1 and 10-3. Wired to the side. For this reason, the main coupling line has a sub-coupling line which is a parallel line at the same distance on both sides. That is, three lines are arranged. Similarly, the same wiring structure is used for memories 10-5 to 10-8. For this reason, if the directional couplers are arranged at a certain interval in the memory, the two intervals can have the coupling length. Since the signal amplitude depends on the coupling length, a longer signal can be captured more reliably and captured.

Next, the time relationship of signals propagating through the module 20C in FIG. 6C will be described with reference to FIG. The horizontal axis is time, and the vertical axis is voltage. When an address signal is output from MC 1 (time T 0) and reaches the directional coupler in module 20 C (time T 1), first, the induced voltage reaches memory 10 -1 (time T 0). l). Since the input impedance of the memory 10-1 is open, total reflection occurs here. The reflected wave propagates on the main coupling line to the left in Fig. 6 (C), but the speed at which this reflected wave propagates is the same as that of the main coupling line. This is because the dielectric constant is surrounded by the same material (epoxy resin). Furthermore, the wavefront of the reflected wave propagating on the sub-coupling line and the wavefront of the address signal propagating on the main coupling line travel with almost the same phase. This is because in the memory 10-1, since the sub-coupling line is directly connected to the input pin, the backward crosstalk induced by the coupler is immediately reflected at this input pin. To be precise, the round-trip delay time of the package of memory 10-1 causes a delay in the reflected wave.However, in recent DRAMs, very small packages such as CSP (Chip Scale Package) are used. I ignore the round trip time.

In FIG. 6 (C), the ends indicated by open squares are memory 10-3, 10-4, 10-7, This is done by the terminating resistor built in 10-8. This eliminates the need for an external termination resistor, which eliminates the need for an area for mounting this resistor. Compared with the method of Fig. 6 (B), the mounting area can be reduced.

Next, the signal traveling on the main coupling line reaches the memory 10-2 (time T2), and backward crosstalk is generated and reflected on this sub coupling line as before. Further, the signal traveling on the main coupling line reaches the memory 10-3 (time Τ3), and at this time, the backward crosstalk generated by the sub-coupling line connected to the previous memory 10-1. Of these, the signal reflected from memory 10-1 reaches memory 10-3 (time Τ3). This reflected wave is completely absorbed by the terminating resistor built in the memory 10-3 and there is no re-reflection. <Similarly, the signal traveling on the main coupling line reaches the memory 10-4 (time Τ 4). At this time, of the backward crosstalk generated by the sub-coupling line connected to the previous memory 10-2, the signal reflected by the memory 10-2 arrives at the memory 10-4 (time Τ Four ). This reflected wave is completely absorbed by the terminating resistor built in the memory 10-4, and there is no re-reflection.

In this way, the signals induced by the couplers reach and reflect at the memories 10-1, 1, 0-2, 10-5, and 10-6, and the memories 10-3, 10-4 , 10-7, 10-8, the reflected wave arrives as a signal and is absorbed. As a result, the address' command signal 3 2 can generate signals in the arrangement order of the memory 10-1 to 10-8. Even in combination with the embodiment of FIG. 3 1 can reach MC 1 with low skew.

Also, since the address command signal 32 is input to the same location on the package in the memory 10-1 to 10-8, the address command signal 32 including the main coupling line is output from the edge electrode 25 of the command signal 32. If the wiring is wired linearly in the memory 10-1 to 10-8 sections, the memories 10-1 to 10-3, 10-5, and 10-5, which have sub-coupling lines above this main coupling wiring 10-7 is a memory in which the input pin is located above this main coupling line, while the memory has sub-coupling lines below this main coupling line 10-2, 10-4, 10-0 In 6, 10-8, the input pins are located below the main coupling wiring. Conversely, memory 1 0-1? By shifting the locations of the odd-numbered and even-numbered memories slightly up and down among 10-8, the main coupling line can be wired for a straight line, and the propagation delay of signals transmitted on this wire The time can be designed to be short and accurate. The distance from the edge of module 20 c to the memory 10-1? 10-8 changes due to the displacement of the memory, but the data signal 31 is affected by this. It is easy to perform equal-length wiring for the evening signal 31 because the wiring slightly undulates. Fig. 6 (D) shows an example in which memories 10-9 for parity bits are added to Fig. 6 (C). The difference between FIG. 6 (D) and FIG. 6 (C) lies in the wiring of the address / command signal 32 in a module having nine memories for parity bits. In FIG. 6 (C), since the address / command signal 32 uses a shared sub-coupling line, it is effective when an even number of memories are mounted. In Fig. 6 (D), the address command signal 32 including the main coupling line is directly terminated to the ninth memory 10-9 by the built-in terminating resistor of the memory 10-9. This eliminates the need for terminating resistors for all of the address' command signals 32, and the cost for terminating resistors can be reduced and cost can be reduced even if memory 10-9 for parity is added.

Referring to FIG. In this embodiment, the termination resistance is eliminated in the sub-coupling line as shown in FIG. 6 (B), and the memory 10-1-1-1-8 has a built-in resistance instead. In other words, in FIG. 6 (E), the memory 10-1 to 10-8 has a built-in termination resistor whose input impedance is the same as the characteristic impedance of the sub-coupling line connected to the memory. . The sub-coupling line is open with no terminal resistance. Also, as in Figs. 6 (C) and 6 (D), the even-numbered memory and the odd-numbered memory have directional coupling wiring with offsets above and below the main coupling line. ing. The wiring length of the coupler is almost twice the memory spacing, which is the same as Fig. 6 (C).

For example, in the memory 10-1, the sub-coupling line is connected to the memory 10-1 and the other end of the sub-coupling line is in an open state in which no element is connected. Therefore, it is totally reflected at this end. The wiring direction of the sub-coupling line is characterized in that the memory 10-1 is located on the front side when viewed from the signal when the signal propagates through the main coupling line. The signal is generated on the side, and this generated signal is totally reflected and transmitted to the memory 10-1 side, and is terminated by the terminating resistor in the memory 10-1. In the same way, the same wiring pattern is used for memories 10-2 to 10-8. In other words, each memory 10-1 to 10-8 is a sub-coupler that is arranged in parallel on both sides of the main coupling line at a fixed interval with respect to the address command signal 32 and the clock signal 30. Connected memory 10-1? 10-8 incorporates a terminating resistor equivalent to the characteristic impedance of the line.

Next, the time sequence of waveform generation in FIG. 6 (E) will be described with reference to FIG. The directional coupler C 1 is composed of a main coupling line 30-1 and a sub coupling line 30-2, each of which is matched and terminated. In the figure, the signal pulse 201 propagates from the right to the left on the main coupling line 30-1. The signal pulse 201 moves to the left at the propagation speed Vp.

The time when the directional coupler C1 is formed, that is, the time when the signal pulse 201 reaches the position where the sub-coupling line 30-1 is adjacent is defined as T1. Immediately after time T1, backward crosstalk is generated 301 on the sub-joining line. Road 30-2, and the traveling direction is the direction. However, since the right end of the sub-coupling line 30-2 is open, it is totally reflected and changes its direction to the left. The propagation speed of this pulse 301 is the same as that of pulse 201. Further, the wavefront of pulse 301 is the same as the wavefront of pulse 201. This is because the pulse 301 is generated at the time T1 when the pulse 201 enters the coupler C1, and this is because total reflection is immediately performed on the sub-coupling line 30_2.

In this manner, the crosstalk signal pulse 301 propagates in phase with the pulse 201, and when the pulse 201 reaches the position corresponding to the pin of the memory 10, the backward crosstalk pulse is generated. 3 0 1 also reaches the pin of memory 10. Then, the noise is absorbed by the terminating resistor in the memory 10, there is no re-reflection and the noise does not undergo multiple reflections.

In this way, as the signal pulse 201 propagates through the main coupling line 30-1, the rear crosstalk signal pulse 301 also propagates in the same phase in the sub coupling line 30-2 in the left direction (forward). .

Returning to Fig. 6 (E), the pulse travels forward (on the left side in Fig. 6 (E)) on the main coupling line, and the memory connected by the directional coupler 10-1-1-10-8 Next, a cross-talk signal pulse is generated. As mentioned earlier, the wavefront of this crosstalk signal pulse is the same as the wavefront of the signal pulse propagating through the main coupling line, and The phases of the signals are aligned.

Thus, the arrival time at this memory 10-1 to 10-8 depends on the memory of each signal 10-1? 1 0—Equivalent to the arrival time at position 8, so the address at the time of read access. Command signal 32, clock signal 30 are memory 10-1? The signals will arrive in the order of 10-8 locations. Therefore, even if the module 20E of FIG. 6E is used, the memory path of FIG. 1 or FIG. 2 described in the first embodiment can be configured. Here, even if there is a gap between the sub-coupling lines, memory 10-1? The time relationship to reach 1 0 -8 does not change. Because there is no sub-coupling line in the gap, it does not generate any backward crosstalk signal and does not contribute to signal transmission.

A fourth embodiment will be described with reference to FIG. This embodiment is an embodiment in which the data signal 31 can be written to the memory 10-1 to 10-8 with low skew at the time of write access. The difference between this embodiment and FIG. 2 lies in the wiring scheme of the address' command signal 32 and the clock signal 30. In FIG. 2 of the first embodiment, these wirings drawn out from MC 1 are folded back on the right side of the drawing to make module 20-1? It was entered in 20-4. In FIG. 8, the address / command signal 32 and the clock signal 30 are extracted from the MC 1 and the module 20-1 immediately? Entered in 2 0—4. Here, in FIGS. 2 and 8, the data signal 31 has the same wiring style, and the positional relationship between the MC 1 and the modules 20-1 to 20-4 is the same. However, the orientation of modules 20-1 to 20-4 is opposite between Fig. 2 and Fig. 8. This has the effect that the same module can be used in both the wiring scheme of FIG. 2 and the wiring scheme of FIG. This means that the degree of freedom in system configuration can be increased.

In operation, when MC 1 performs write access, MC 1 outputs the address and command signal 32 relating to the write access. It reaches memory 1 0 -1 physically closest to MC 1 first, and finally reaches memory 10 8 -8, which is farthest. This arrival order is D1 of data signal 31? Equal to that of D4. For this reason, the write data transmitted at the time of write access has the same propagation delay time as the address / command signal 32 and the clock signal 30. Each memory 10-1? 1 0 -8 ', and for each memory 1 0—1? 1 0—8, the address Input signal 32, clock signal 30 and data signal 31. Therefore, timing design for write access becomes very easy.

In the configuration of FIG. 8, when the MC 1 performs read access, unlike the embodiment of FIG. 2, the read data is stored in the memory 10-1? The time to reach M C 1 varies greatly depending on the position of 1 0—8. To be exact, each memory 1 0—1? It will be shifted by the round-trip delay time from 10 to 8. For this reason, a delay adjustment circuit equivalent to this round trip delay time is provided in the MC 1 to adjust the timing so that the read data can be reliably captured. This method can be easily achieved by using the delay circuit 1B shown in FIG. 3 on the data input side.

With this configuration, high-speed writing can be performed with low latency for write access. The system is suitable for processing that involves a lot of writing, such as graphic memory.

Next, FIG. 9 shows a mounting image of FIGS. 1 and 2 of the first embodiment, FIG. 6 of the third embodiment, and FIG. 8 of the fourth embodiment. Reference numeral 20 denotes a module having memories 10-1 to 10-8. Address / command signal 32 and clock signal 30 in module 20 are wired upward from one side of the module. In order to form a directional coupler, the wire is bent in a straight line and the other end is terminated. When mounted on connector 90, a notch for alignment is provided on module 20 so that the orientation is not mistaken, and an incorrect insertion prevention pin corresponding to the notch position is provided on connector 90. I have. For this reason, the direction in which the module 20 is inserted into the connector 90 is not mistaken. In this embodiment, the notch is used as a method for preventing the connection direction from being mistaken. However, any other means for correctly connecting the module side pin and the connector side pin may be included.

Next, FIG. 10 shows a sectional view of the substrate of FIGS. 1 and 2 of the first embodiment. Mother board 10 (HMC 1, connector 90 and module 20 are mounted, Figure 10 is a cross section along the X-axis near MC 1. It has multiple signal and power layers. In this case, MC 1 is a surface-mounted component, and if the package is a BGA (Ball Grid Aray), it is connected to the board 100 with a solder pole.The connector 90 is also a surface-mounted component. Thus, the wiring density of the component Byone can be increased. From the MCI, an address / command signal 32, a clock signal 30 and a data signal 31 are wired so that signals can be transmitted to the module 20 via the connector 90. The overnight signal 31 wiring is wired from MC 1 using one or two signal layers. In FIG. 10, the wiring is formed using two layers. The address command signal 32 and the clock signal 30 are wired in different layers from the data signal. These wirings have a so-called stripline structure sandwiched between power supply layers. Therefore, the propagation delay time is determined by the dielectric constant of the material surrounding the wiring. For this reason, both speeds can be matched by using the same material for module 20 and mother port 100.

In Fig. 10, the address / command 'signal 32, the clock signal 30 and the data signal 31 are wired in the same X-axis direction, but crosstalk noise can be avoided by changing layers. Can be. For this reason, the address command signal 32 and the clock signal 30 of the mother board 100 can be wired so as to overlap the data wiring, and the wiring length can be tuned and the density can be increased.

Next, as a fifth embodiment, the configuration of the receiver for the address command signal 32 will be described with reference to FIG. In the memories used in FIGS. 6 (C) and (D), there are a configuration in which the address command signal and the clock signal are terminated, and a configuration in which they are released (Hi-Z). Although two types of memories may be used, it is better from the viewpoint of cost to realize both functions with the same chip. Therefore, in this embodiment, as shown in FIG. 11 (A), the termination resistance is constituted by the transistor 50, and the input impedance can be controlled by turning the termination transistor 50 on and off. Of course, it is also possible to control the terminating resistance value to be variable. For example, the transistor 50 is configured so that a plurality of transistors having different gate widths are connected in parallel, and the input impedance is adjusted by turning on and off each of these transistors according to the resistance value. can do. The control circuit 53 adjusts the impedance.

In FIG. 11 (A), a resistor 51 is connected between the input terminal and the receiver 52. This can be configured by metal wiring on the chip, but a desired input impedance can be generated by the sum of the resistor 50 (R 1) and the transistor 50 described above. This resistor 51 (R1) keeps the resistance of transistor 50 low. And the size of the transistor 50 can be reduced as a result. In FIG. 11A, the transistor is connected to the termination voltage V tt. This termination voltage Vtt is the same as the reference voltage Vref. That is, the signal passing through the coupler generates positive and negative pulses centered on the termination voltage V tt, and these pulses are input to the receiver 52 of the memory. The input signal is compared with the reference voltage V ref and identified as data.

In FIG. 11B, one of the internal termination transistors 50 of the receiver is connected to the signal input pin and the other is connected to the reference voltage Vref of the receiver 52. Since the signal amplitude generated by the directional coupler is small and has no DC component, the current flowing through the termination transistor 50 to the reference voltage V ref in FIG. 11B is small. Also, since the reference voltage V ref is connected to the ground potential of the module in which the memory is mounted with low impedance by a decoupling capacitor, even if the termination current is fed back to the reference voltage V ref, noise will occur. Hateful. With such a configuration, the memory package does not need to have a V tt pin for the terminal power supply, and the cost of the package can be reduced.

Next, a description will be given of a circuit example of the address and command signal 32, the MC 1 of the clock signal 30 and the voltage of the memory 1 with reference to FIG. 12 as a sixth embodiment.

The address / command signal 32 and the clock signal 30 are one-way signals from the MC 1 to the memory 10. Then, as shown in the first and second embodiments, except for FIG. 6A, these signals are transmitted in the module 20 using the directional coupler. Therefore, MC 1 and memory 10 are not DC connected. As the signal, the signal generated by the coupler is superimposed on the terminal potential on the memory 10 side. In FIG. 12, a driver circuit 2 for the address / command signal 32 and the clock signal 30 provided in the MC 1 is indicated by 2. Driver circuit 2 is open drain. The transistor 55 ′ in the driver 2 is connected to the termination voltage 60 (V dd) through the wiring 70 and the termination resistor 61. The receiver 3 in the memory 10 has a differential receiver 52, a terminating transistor 50, and an impedance adjusting circuit 53, which are connected to the sub-coupling line 71. The combination of the sub-coupling line 71 and the memory 10 with built-in termination is assumed as shown in FIG. Although the package is not shown in this figure, the parasitic capacitance due to this, Of course there is parasitic inductance.

When a signal is output from the driver 55 in the MC 1, the potential of the main coupling line 70 is Vdd or Vol. Here, V o1 is the voltage at the time of L output and is a voltage determined by the terminating resistance 61 and the resistance voltage dividing ratio of the transistor 55.

The signal input to the receiver 52 in the memory 10 is a pulse of a positive electrode and a negative electrode centering on Vtt which is a terminal potential of the sub-coupling wiring 71. This is because the directional coupler does not pass the DC component. For this reason, the terminal voltage V dd on the main coupling line 70 and the terminal potential V tt on the sub coupling line 71 can be independently determined. This is because the address / command signal 32 and the clock signal 30 are one-way signals from the MC 1 to the memory 10; when bidirectional signal transmission is performed, both potentials V dd and V tt are Must be the same. Otherwise, the drive voltage will be different for transmission and reception, which will be asymmetric and complicate the design.

For this reason, the termination voltage V tt on the side of the sub-coupling line Ί ′ 1 can be set to a potential at which the input receiver 52 has the maximum sensitivity. This is because the memory is composed of C-MOS transistors, but depending on the voltage, it becomes a dead zone. An input signal exceeding the power supply voltage cannot be obtained with a general C-MOS transistor.

As an example, a high-speed DRAM operates at 1.8 V, but the termination voltage Vdd of the driver 55 can be set to 1.8 V. Assuming that the terminating resistor 61 is 50 Ω and the impedance of the transistor 55 is 15 Ω, V o 1 is 0.41 V and the signal amplitude is about 1.4 V. Assuming that the voltage coupling of the directional coupler is designed to be 20%, a voltage of 280 mV is induced in the sub-coupler. This is transmitted to the receiver 52 of the memory 10. However, if the termination potential V tt on the side of the sub-coupling line 71 is set to 0.9 V, the voltage input to the receiver 52 becomes 0.9 V ± 0.2. 'It becomes 8 V. This 0.9 V is the potential at which both the N-M も S transistor and the P-MOS transistor can have high sensitivity when the circuit is composed of C-MQS.

In this way, an open-drain binary signal can be used as the drive signal for the address / command signal 32 and the clock signal 30, and the receiver 52 for the memory 10 can receive a receiver signal. Since the voltage at which 52 is the maximum sensitivity can be used as the center voltage, a high-speed circuit can be configured. Further, by making the driver signal binary, the preamble period required before outputting the IZO data can be eliminated from the address signal. This is important for address and command signals. The reason is that if the address has a preamble period, the access latency increases and the system performance decreases accordingly.

Here, the preamble is as described below. The data is an IZO system that transmits and receives data, and when a directional coupler is used, it has a ternary waveform like a CTT (Center Tapped Transceiver) (Fig. 17). In other words, in the CTT, the terminal is terminated at a potential of half the signal amplitude, and the driver outputs an H state or an L state with respect to this terminal potential. When the terminal is not outputting the signal, the terminal is open (Hi-Z). Therefore, when the first data to be transferred is output from the center potential that is in the open (Hi-Z) state, the amplitude is halved, and the signal generated by the directional coupler is also halved. As a result, the operation of the first part of this transfer becomes unstable, so the I / II system sets an L or H state by providing an invalid period called a preamble before transmitting the first data of the transfer. Output, and the potential of the wiring was fixed for a certain period before the full-amplitude data was output. .

Next, a sequence for adjusting the input impedance of the receiver will be described with reference to FIGS. This sequence uses the same memory chip as shown in Fig. 6 (C) and selects whether to turn on the internal termination or open (Hi-Z) depending on the mounting location, and adjust the value of the termination resistor. This sequence is performed before actual data is read or written after power is supplied. In this sense, it is a memory initialization sequence.

The sequence is first supplied to the memory (40-1). Next, the clock is input and the reset sequence is executed (40-2, 40-3). In reset sequence 40-3, the internal cells of each bank of the memory are cleared, and the flip-flop (Flip Flop) in the memory is set to the initial value. Up to this point, it is equivalent to a normal SDRAM sequence. 4 0-4 adjusts the output impedance of the data system. The driver for the data signal is a push-pull circuit such as CTT. In the last stage of the driver, members having different gate widths are connected in parallel.

The adjustment of the impedance of the dryper can be performed in the following manner. The driver impedance can be varied by independently selecting any combination of P-MOS transistors and N-MOS transistors that are connected in parallel in the final stage of the driver. This impedance is constituted by an external resistance value connected to the memory. For example, the external resistance and the impedance of the driver P-MOS transistor are compared by a bridge circuit or the like, and the gate width of the P-MOS transistor is varied stepwise. This makes it possible to control the output impedance of the P-MOS transistor. Similarly, the output impedance of an N-MOS transistor can be adjusted by comparing it with an external resistor.

The next sequence is the setting of the address command signal 32 (40-5). In this sequence, first, the state of the address impedance setting pin is monitored. The memory of this embodiment is provided with an address impedance setting pin, and by monitoring this state, it is determined whether or not to terminate the address and command signal 32. The setting of this address impedance setting pin is performed on the module in which this memory is mounted. In Fig. 6 (C), the memory is set to H state or L state by wiring of module 20 (D) for each memory. You. At 4-6, it is determined whether the input of this address impedance setting pin is H state or L state. If this pin is high in the memory settings, adjust the input impedance of all address / command signals 32 and clock signal 30 to match the impedance of the wiring. As this method, it is easy to adjust using the external resistance used in sequence 40-4. When the characteristic impedance of the module's address and command signal 32 is Z0 and the resistance of the resistor is R, select an external resistor so that the Zo ZR ratio σ has a predetermined value. For example, the input impedance of the address / command signal 32 may be adjusted to be the product of σ and R in the same manner as the method for adjusting the impedance of the driver. ,.

If the value of the address impedance setting pin is L in sequence 40-6, the internal terminating resistor of the address / command / clock signal is open (Hi-Ζ) (40-8). By taking such a sequence, not only the driver but also the input impedance of the address, command, and clock can be set with high accuracy. In addition, the input of the address, command, and clock is controlled by the wiring of the module in which the Since one dance can be selectively terminated or released (Hi-Z), termination or non-termination can be selected depending on the memory mounting position as shown in Fig. 6 (D). As a result, an address / command signal 32 using a directional coupler as a system is configured in a module, and a data signal of read access or write access can be realized with low skew regardless of the wiring length.

As an alternative, the input impedance of the address command signal 32 is released (high impedance) or adjusted to a value approximately equal to the characteristic impedance of the wiring connected to the address command signal 32, as described below. A non-volatile memory (EEPROM, etc.) is installed in module 20, and the impedance adjustment value of each memory is stored in this module. The stored adjustment value may be set in each memory after power-on via a serial signal (boundary scan) for circuit verification. This adjustment value, that is, the input circuit 3a or 3b for the address / command signal 32 in FIG. 11 is a value having the impedance adjustment circuit 53, which is assumed at the time of design. A value may be used, or a value actually measured in a process inspection or a circuit inspection to be inspected at the time of manufacturing a memory may be used.

In this way, by storing the set values in the EEPROM on the module according to the profile (information) of each memory mounted on the module at the time of module manufacture, the configuration shown in FIGS. 6 (B) and 6 (C) can be obtained. FIG. 6 (D) and FIG. 6 (E) can be handled with a single memory. In this case, no external pin for impedance adjustment is required for the memory.

According to the invention of the present application, by running the address 'command signal in parallel with the clock and wiring these for each module, waveform distortion due to the branch wiring of the address' command signal can be eliminated. The address' command signal can be speeded up. This eliminates the need for an address buffer and can reduce accelerator latency.

Also, the address command signal and the clock signal are transmitted by the directional coupler formed in the module so that the data signal wiring and address wiring have the same wiring length for all memories as shown in Fig. 1. By configuring, the data queue of read access can be kept small. As a result, the access level of the read access can be increased in the information processing apparatus where the read access is much larger than the write access. The latency can be shortened, and the system performance improves.

In addition, since the far side of the memory controller of the main coupling line is terminated, the timing or order of multiple memory chips in the memory module can be managed.

In addition, since the address terminal and the data terminal are separate terminals, it is possible to improve the access data rate at low speed.

In addition, the timing of supplying the address and the clock to one memory chip keeps pace, so that the timing margin is improved and the noise resistance is improved. It is needless to say that the present invention is not limited to the above-described embodiment, and can be modified and implemented without departing from the gist, regardless of the application field.

By running the address / command signal in parallel with the clock and arranging these for each module, it is possible to eliminate waveform distortion due to branching of the address / command signal, thereby speeding up the address / command signal. This has the effect of becoming Industrial applicability

The present invention makes it possible to realize high-speed bus transmission in which data is transferred by connecting a plurality of elements to the same transmission line in signal transmission between elements such as a multiprocessor and a memory in an information processing device. The present invention is applicable to a bus connecting a plurality of memory modules and a memory controller and a system using the bus.

Claims

In a memory system having a memory module equipped with a plurality of memories and a memory controller controlling the plurality of memory modules,

An address command signal and a clock signal are wired from the memory controller to each of the memory modules, and the address command signal and the clock signal are written to the respective memories in the memory module in a single stroke. A memory system characterized by being connected.

2.

The memory system of claim 1,

Data signals are pulled from the memory controller, perpendicular to bending ^only; and, the memory module - from near have terminals provided terminals longitudinally from the memory controller Le sequentially electrically connected,

The address / command signal and the click signal are drawn out from the memory controller in the longitudinal direction of the memory module, and are electrically connected to terminals of the memory module at a position remote from the memory controller. ,

Within the memory module,

The data signal is wired in equal length from the connection terminal to the memory, and the address / command signal and the clock signal are applied to all the memories so that the propagation delay time from the connection terminal to each memory is the same. A memory system that prioritizes read access, characterized by being connected in a one-stroke (daisy-chain) fashion.

3.

3. The memory system of claim 2, wherein

In a memory read access, the memory controller outputs the address command signal in synchronization with the clock signal, and the output address command signal is sequentially input to each memory in the memory module together with the clock signal. The memory outputs lead data corresponding to the address, and the read data arrives at the same time in the memory controller.

Four .

The memory controller according to claim 3,

The memory controller outputs an address / command signal and a clock signal in synchronization with each module, receives all read data output from the module at the same time,

The memory controller has a delay adjustment circuit that adjusts a wiring delay time difference of each write data so that the clock signal and the write data arrive in each memory in synchronization with each other. Memory controller that gives priority to read access.

Five .

The memory system of claim 1, wherein

The data signal is extracted from the memory controller, bent at a right angle, and electrically connected to the terminal provided in the longitudinal direction of the memory module in order from the terminal closest to the memory controller,

The address command signal and the click signal are extracted from the memory controller in a longitudinal direction of the memory module, and are electrically connected to terminals of the memory module near the memory controller,

Within the memory module,

The data signal is wired in equal length from the connection terminal to the memory, and the address / command signal and the clock signal are applied to all the memories so that the propagation delay time from the connection terminal to each memory is the same. A memory system that prioritizes write access, which is connected in a one-stroke (daisy-chain) manner.

6.

The memory system of claim 5, wherein:

In a memory write access, the memory controller outputs the address / command signal in synchronization with the clock signal, and the output address / command signal is output to each memory in the memory module together with the clock signal. Write access is sequentially input, the write data is output in synchronization with the clock signal 30, and arrives at the same time as the address / command signal and the clock signal. Memory wiring method.

7.

The memory controller according to claim 6, wherein:

An address command signal and a clock signal are output in synchronization with the module, and a data signal is output in synchronization with the clock signal. All write data is transmitted to all memories in the memory module by the clock signal. Arrived at the same time as

The read data signal output in synchronization with the clock signal in each memory arrives at the memory controller with a wiring delay time difference, and the delay time difference between the arrived read data signals is adjusted by a delay adjustment circuit. Memory controller that gives priority to write access.

8 ·

A memory module for use in any of claims, 1, 2, 3, 5 or claim 6, wherein

The address and command signal and the clock signal are connected to the signal terminals of all the memories in order without branching so that the propagation delay time from the terminal provided in the module to each memory mounted in the memory module is the same. A memory module characterized by being performed.

9 ·

A memory module used in any of claims 1, 2, 3, 5 or claim 6, wherein

The address command signal and the clock signal are provided in the same direction so as to have the same propagation delay time from the terminal provided on the module to each memory mounted on the memory module. A main coupler of the directional coupler, terminated at a far end, terminated at one end of a sub-coupler constituting the directional coupler, and the other end is connected to a signal terminal of the memory; A memory module, characterized in that the connection terminal of the memory is located behind the signal propagation direction of the main coupler.

Ten .

A memory module used in any of claims 1, 2, 3, 5 or claim 6. And

The address / command signal and the clock signal are connected so that the same propagation delay time is obtained from the terminal provided on the module to each memory mounted on the memory module. The main coupler of the sexual coupler is terminated at the far end, and the memory is connected to both ends of the sub-coupler constituting the directional coupler, and the sub-coupler is directed in the signal propagation direction of the main coupler. A memory module terminated with the memory on the front side and opened with the memory on the rear side. A memory module used in any of claims 1, 2, 3, 5 or claim 6, wherein

The address command signal and the clock signal are provided in the same direction so as to have the same propagation delay time from the terminal provided on the module to each memory mounted on the memory module. The main coupler of the directional coupler is terminated at the far end with a terminating resistor built in the memory, and the memory is connected to both ends of the sub-coupler constituting the directional coupler; The memory module is terminated in the memory on the front side with respect to the signal propagation direction of the main coupler, and is opened in the memory on the rear side.

1 2.

A memory module used in any of claims 1, 2, 3, 5 or claim 6, wherein

The address command signal and the clock signal are transmitted from the terminal provided on the module to each memory mounted on the memory module so as to have the same propagation delay time. Are terminated at the far end and constitute the main coupling part of the directional coupler, one end of the sub-coupler constituting the directional coupler is open, and the other end is the signal terminal of the memory. And a terminal terminated by a terminating resistor built in the memory, wherein the connection terminal of the memory is located forward with respect to a signal propagation direction of the main coupler.

13 .

The memory module according to claim 9, 10, or 12, Sub-coupling lines connected to the even-numbered and odd-numbered memories counted from the end with respect to the address command signal and the clock signal are arranged on opposite sides of both sides of the main coupling line, respectively. Memory module.

14 .

The memory module according to any one of claims 9, 10, 11, 12, and 13, wherein:

Address / command signal and clock signal are wired in a straight line at the memory connection part, and the even-numbered memory and odd-numbered memory counted from the end are arranged on opposite sides of both sides of the main coupler. Is a memory module characterized by being wired in equal length.

1 5.

A memory module according to claim 9, 10, 11, 12, 13, 14, wherein

Address and command signals and clock signals are wired in a straight line at the memory connection part, and the even-numbered and odd-numbered memories counted from the end are arranged on opposite sides of both sides of the main coupler, and data signals are equal. A memory module characterized by long wiring.

1 6.

A memory mounted on the memory module according to any one of claims 10, 11, 12, 13, 14, and 15,

A memory characterized in that the input impedance of an address / command signal can be released (high impedance) or adjusted so as to have a value substantially equal to the characteristic impedance of wiring connected to the address / command signal.

17 .- The memory according to claim 16, wherein

The input impedance of the address / command signal can be released (high impedance) or adjusted to a value almost equal to the characteristic impedance of the wiring connected to the address / command signal, and the input impedance of the address / command signal can be adjusted to the characteristic of the wiring. When adjusting to impedance, input differential circuit of the address / command signal Wherein the reference voltage and the input terminal are terminated.

1 8.

The memory according to any one of claims 16 and 17, wherein

An impedance selection signal is provided as an external signal for releasing the input impedance of the address / command signal (high impedance) or adjusting the impedance to a value substantially equal to the characteristic impedance of the wiring connected to the address / command signal. Note U.

1 9.

The memory according to any one of claims 16 and 17, wherein

Releases the input impedance of the address / command signal (high impedance) or holds an adjustment circuit and an adjustment value for adjusting to a value almost equal to the characteristic impedance of the wiring connected to the address / command signal. A memory having a register, wherein the value of the register can be set after power-on via a serial signal (boundary scan) for circuit verification.

2 0.

The memory module according to any one of claims 10, 11, 12, 13, 14, and 15, comprising the memory according to claim 19,

A method of manufacturing a memory module, comprising, after mounting the memory in the module, storing a register value in a nonvolatile memory in the memory module for setting an input impedance of the memory.

twenty one .

Claims 8, 9,

Ten,

1 1,

1 2,

13,

A memory system including the memory module according to any one of (1) and (4), and

For a plurality of memories mounted in the memory module,

A memory system, wherein a difference in propagation delay time between address / command signal and clock signal wiring between memories and a difference in propagation delay time from a memory controller to a data signal terminal of the memory are equal to each other.

twenty two .

The memory system according to any one of claims 1, 2, 3, and 21, The motherboard on which the memory controller is mounted includes a plurality of signal wiring layers, and the data wiring, the address / command signal wiring, and the clock signal wiring are wired in the longitudinal direction of the memory module. A memory system, wherein the address / command signal wiring is provided on another signal wiring. twenty three .

In a bus system that transmits data in one direction from one LSI with a driver to several LSIs with a receiver,

The driver is an open drain having a binary output voltage, the receiver has a differential input circuit,

The open drain driver is terminated at a termination voltage (V dd) via wiring, the differential input circuit is terminated at a termination power supply (V tt), and a wiring is connected to an input of the differential input circuit. The wiring connected to the driver forms a main coupler, the wiring connected to the differential input circuit forms a sub-coupler, and the main coupler and the sub-coupler form a directional coupler. Make up,

A path system, wherein the differential input circuit has a terminating power supply (V tt) lower than the terminating voltage (V dd) via the wiring in the open drain driver.

twenty four .

A memory system according to any one of claims 1, 2, 3, 5, 5, 6, 21, and 22,

A memory system with an incorrect insertion prevention mechanism to prevent errors when inserting multiple memory modules. '

twenty five .

A memory system in which at least a plurality of memory chips are arranged in the X direction or the y direction,

A plurality of memory modules which incorporate a plurality of memory chips in one of the X direction and the y direction and are arranged in the other direction in the X direction or the y direction; the plurality of memory modules and an address Z command line; A memory controller connected via a clock line and a data line,

The memory controller and each of the plurality of memory modules correspond to each other. A plurality of memory chips in a column of the plurality of memory modules are connected to the memory controller via corresponding data lines;

A plurality of memory chips in another column of the plurality of memory modules are a plurality of memory modules used in a memory system connected to the memory controller via another corresponding data line,

The plurality of memory chips included in each of the plurality of memory modules are commonly connected via the main address / command line constituting the address / command line and are accessible to the memory controller. The address / command line is connected to a terminating resistor at a point furthest from the memory controller,

A plurality of memory chips in each of the plurality of memory modules are commonly connected and accessible to the memory controller via a main clock line constituting the link line, A plurality of memory modules, wherein the clock line is connected to a terminating resistor at a point farthest from the memory controller.

2 6.

26. The memory module according to claim 25, wherein each of the plurality of memory modules includes a plurality of crosstalk-type couplers,

The main coupling lines of the plurality of couplers constitute a main address command line and a main clock line,

A memory module, wherein the sub-coupling lines of the plurality of couplers constitute a memory coupling address command line and a memory coupling clock line connected to a memory chip.