WO2003081666A1

WO2003081666A1 - Production method for a contact in a semiconductor structure and corresponding contact

Info

Publication number: WO2003081666A1
Application number: PCT/EP2003/001139
Authority: WO
Inventors: Joern Luetzen; Martin Popp; Till Schloesser
Original assignee: Infineon Technologies Ag
Priority date: 2002-03-22
Filing date: 2003-02-05
Publication date: 2003-10-02
Also published as: TW200304671A; WO2003081666A8; DE10212914A1

Abstract

The invention relates to a production method for a contact in a semiconductor structure comprising a substrate (1) provided with a first and second structural element (GS1, GS2) of approximately the same height which are disposed on the surface of the substrate and which are distanced from each other by means of an intermediate space having a critical lateral dimension. The inventive method comprises the following steps: provision of an active area (60) in the substrate (1) between the structural elements (GS1, GS2); raising the active area (60) by selective epitaxy of conductive substrate material (80); and formation of the contact (CB) on the raised active area. The invention also relates to a corresponding contact.

Description

Manufacturing method for a contact in a semiconductor structure and corresponding contact

DESCRIPTION

The present invention relates to a production method for a contact in a semiconductor structure which has a substrate with first and second structural elements which are provided on the substrate surface and have approximately the same height and which are spaced apart from one another by a space having a critical lateral dimension. The invention also relates to a corresponding contact.

Although applicable in principle to any integrated circuits, the present invention and the problem on which it is based are explained in relation to integrated memory circuits in silicon technology.

In the manufacture of integrated circuits, in particular integrated semiconductor memory circuits, it is necessary to produce various types of contacts. It is desirable to produce these different contacts with as few lithography levels and etching steps as possible in order to ensure a high degree of alignment accuracy.

FIG. 6 shows an exemplary silicon semiconductor substrate 1 with a memory cell arrangement (not illustrated in more detail) to explain the background problem. 60 denotes an active area, for example a common one Source / drain area of two memory cells. GS1, GS2 are two side-by-side gate stacks, which are constructed from a polysilicon layer 10 with an underlying (not illustrated) gate dielectric layer (eg gate oxide), possibly a silicide layer 20 and a silicon nitride cap 30 and a side wall oxide layer 40. The two gate stacks GS1, GS2 have approximately the same height d.

A critical contact type CB, which electrically contacts the active region 60 between the two gate stacks GS1, GS2, must be provided between the two gate stacks GS1, GS2, since the lateral distance between the gate stacks GS1, GS2 has a critical dimension. The contact hole for the critical contact CB is usually etched separately from other less critical contacts. As is known, the critical distance results from increasing miniaturization, which leads to an increase in the number of chips per wafer and thus to a reduction in costs.

A suitable CB contact hole etching (SAC etching = Seif

Finding aligned contact) has been a key problem for many generations of technology. The main requirements include:

- not to cause short circuits between bitline and wordline (CB-GC shorts), so that the etching should be as selective as possible with respect to silicon nitride;

To avoid CB opens, ie not sufficiently deeply etched contact holes; and do not widen the CD (critical dimension) dimension in the upper section of the contact hole, since even slight widening would greatly increase the risk of CB-CB shorts over poorly adjusted metallization paths.

FIG. 7 shows the conditions for explaining the usual contact hole etching process for the example according to FIG. 6. In particular, the gate stacks GS1, GS2 are embedded in two superimposed insulation layers 100, 110 (preferably oxide layers).

Then, the etching process for forming a contact hole for the contact CB is accomplished by two-stage etching. In the first step, anisotropic etching is carried out as vertically as possible up to approximately the level of silicon nitride layer 30, and in the second step, etching is carried out as selectively as possible with respect to silicon nitride layer 30, the profile of the upper region of contact hole KB should preferably not be widened.

In the second stage of the etching, a compromise must therefore be found between the highest possible selectivity for silicon nitride and the avoidance of an etching stop. The selectivity is usually achieved by selecting the etching chemistry in such a way that protective polymers form on the silicon nitride surfaces. On the other hand, an etching stop can occur if too many polymers are formed and the contact hole, which tapers towards the bottom, closes. It is therefore a crucial requirement, an extreme one to find a selective process that does not lead to an etching stop at the same time.

Finally, the contact CB is covered by a metal deposit of e.g. Tungsten and a subsequent CMP step (chemical mechanical polishing) completed.

With the increasing downsizing of the structures of DRAM cells with a trench capacitor, the problem arises that the contact resistance of the connections to the selection transistor both on the side of the trench capacitor (buried strap) and on the opposite side (CB contact or bitline contact) ) increases.

Due to the self-aligned etching of the contact CB with increasingly smaller dimensions, this leads to the fact that, in particular in the lower region of the etched contact hole, a significant tapering can occur, which leads to a considerably increased contact resistance. So far, these problems have been countered by optimizing the etching process and increasing the doping on the buried strap side.

The object of the present invention is to provide a generic method by means of which a new integration concept is created which relaxes the conditions for creating the critical contact. According to the invention, this object is achieved by the manufacturing method specified in claim 1 or the contact according to claim 13.

The advantages of the method according to the invention are in particular that the yield in the process, for example in the DRAM production process, can be significantly increased by reducing the short-circuit problem, since the undesired widening of the contact hole in the upper region and narrowing in the lower region can be further reduced, even though the process control is somewhat more complex than before due to the additional selective growth step.

The idea on which the present invention is based consists, on the one hand, of reducing the necessary depth for the critical etching process on the contact areas and selectively a highly conductive area for the connection to the outside by selectively estimating a conductive material, which can possibly still be doped manufacture. If the raised area is a source / drain area of a field effect transistor, for example a selection transistor, the electrical properties of the transistor are improved by the procedure according to the invention, since the critical E fields can be reduced. The procedure according to the invention also enables an increasing reduction in size of DRAM memory cells and thus a considerable cost advantage.

Advantageous further developments and improvements of the manufacturing method specified in claim 1 are found in the subclaims.

According to a preferred development, an oxide is provided on the surface of the substrate by selective growth before the active region is raised and this oxide is opened above the active region.

According to a further preferred development, a side wall spacer is formed on the two structural elements by selective growth before or after the active area is raised.

According to a further preferred development, after the side wall spacer and the raised active area have been formed, a self-aligned implantation is carried out in the raised active area.

According to a further preferred development, the two structural elements are embedded in at least one insulation layer after the selective growth, after which a contact hole is provided for the contact in the at least one insulation layer. According to a further preferred development, two insulation layers are provided, which are first and second silicon dioxide layers or nitrided SiO _x layers.

According to a further preferred development, the two structural elements are a first and second gate stack of a memory cell arrangement, the active region being a source / gain connection of a selection transistor.

According to a further preferred development, the

Memory cell arrangement constructed using trench technology, the memory cell capacitances being buried in the substrate.

According to a further preferred development, the memory cell arrangement is constructed using stacking technology, the memory cell capacitances being stacked over the substrate.

According to a further preferred development, at least one further active area is provided in the substrate between the structural elements and the further active area is also increased when the active area is increased by selective growth of substrate material or conductive material.

According to a further preferred development, the further active area is a connection of a memory cell capacity. According to a further preferred development, the active region is raised by selective growth of substrate material or conductive material up to approximately half the height of the two structural elements.

Embodiments of the invention are shown in the drawings and explained in more detail in the following description.

Show it:

1-4 are schematic representations of successive process stages of a production process for a contact in a semiconductor structure as a first embodiment of the present invention;

FIG. 5 shows a schematic illustration to illustrate a process stage analogous to FIG. 3 of a production process for a contact in a

Semiconductor structure as a second embodiment of the present invention;

FIG. 6 shows an exemplary silicon semiconductor substrate with a memory cell arrangement (not illustrated in more detail) to explain the background problem; and Fig. 7 shows the conditions for explaining the usual

Contact hole etching process for the example according to FIG. 6.

In the figures, the same reference numerals designate the same or functionally identical components.

1 to 4 are schematic representations of successive process stages of a manufacturing process for a contact hole in a semiconductor structure as a first embodiment of the present invention.

1, a substrate 1 is provided with a memory cell arrangement (not shown). Reference numeral 60 denotes a first active area, for example a common source / drain area of two memory cells. Reference numeral 60 denotes a second active area, for example a trench capacitor connection of a memory cell.

Further doped areas are not shown for the sake of simplicity since they are not relevant to the invention. Adjacent gate stacks GS1 and GS2 are located above the active area 60, which have a critical lateral distance and approximately the same height d.

The gate stacks GS1, GS2 have the same structure as those according to FIG. 6, namely a lower layer 10 made of polysilicon with a gate oxide layer (not shown) underneath, a middle layer 20 made of one Silicide and an upper layer 30 of silicon nitride and a sidewall oxide layer 40. CB denotes the position at which the critical contact to the active region 60 is to be made.

1, after formation of the gate stacks GS1, GS2 constructed in this way, an oxide layer 70 is formed on the entire surface of the substrate 1. In a subsequent process step, this oxide layer 70 is then opened ^Λ 60 in the region between the gate stacks GSL GS2 above the active region 60 and adjacent to the gate stack GSI above the active region. This is preferably done using known photolithographic etching techniques.

In a subsequent process step, which is illustrated in FIG. 2, there is then a selective growth of conductive substrate material 80 or 80 ^Λ above the exposed active areas 60 or 60 ^x . The selective growth is preferably accomplished by means of selective gas phase epitaxy. The height of the grown areas 80, 80 is preferably between 30% and 50% of the height d of the gate stacks GS1, GS2.

As illustrated in FIG. 3, sidewall spacers 90 made of silicon nitride are then formed on the sidewalls of the gate stacks GS1, GS2. In this context, it should also be mentioned that due to the increased area 80 between the gate stacks GS1, GS2, the remaining height d ^{Λ of} the intermediate space is significant. is less than the height d of the space without the raised area 80.

After the side wall spacers 90 have been attached, there is a self-adjusted implantation I, which increases the conductivity of the grown areas 80, 80 ^λ . Under certain circumstances, this implantation I can be omitted if the lubricity of the grown material is sufficient for the application.

Thereafter, as shown in Fig. 4, a silicon oxide layer, e.g. a BPSG layer (boron-phosphorus-silicate glass) deposited, which is designated by reference number 100. This BPSG layer 100 is made to flow in a subsequent tempering, so that it leaves no free spaces or voids, in particular between the closely adjacent gate stacks GS1, GS2.

In a subsequent (not illustrated) process step, a planarizing ARC (anti-reflective coating) varnish is applied, which compensates for the remaining unevenness in the surface of the BPSG 100. If this is not sufficient, planarization, for example by means of chemical mechanical polishing (CMP), can also take place after the tempering of the BPSG layer 100.

A further intermediate oxide (for example TEOS), which is designated by reference symbol 110, is then deposited on the resulting structure. This intermediate oxide 110 serves as a spacer from the substrate, for example from the gate stacks, for later metallization in order to keep capacitive couplings low.

Then, as in the prior art, a contact ^{hole is} formed by means of a two-stage etching process at the location of the critical contact CB ^{Λ to be} formed, which reaches down to the grown-up area 80. This contact hole is then in the usual way with a metal, such as. B. tungsten, filled by a full-surface deposition process, whereupon a CMP step takes place, through which the tungsten is removed outside the contact hole. This completes the critical contact CB, which has a smaller depth extension than the critical contact CB known in the prior art, which leads to a significant relaxation of the etching process in the upper region of the insulation layer 110 and in the lower region between the two gate stacks GS1, GS2 leads.

FIG. 5 shows a schematic illustration to illustrate a process stage analogous to FIG. 3 of a production method for a contact in a semiconductor structure as a second embodiment of the present invention.

In the illustration shown in FIG. 5, the side wall spacers 90 are formed on the side walls of the gate stacks GS1, GS2 before the selective deposition of the raised areas 80, 80. Otherwise, the method steps of this second embodiment are the same as those of the above refined first embodiment. This embodiment has the advantage that the critical contact CB is better insulated from the word lines provided in the gate stacks GS1, GS2.

Although the present invention has been described above on the basis of preferred exemplary embodiments, it is not restricted thereto, but rather can be modified in a variety of ways.

In particular, the selection of the layer materials is only exemplary and can be varied in many ways.

The method according to the invention can also be applied to any semiconductor structures and not only to the memory cell arrangements given by way of example.

REFERENCE SIGN LIST:

1 substrate

GSl, GS2 gate stack

60 ^λ active area (trench capacitor connection)

60 active area (source, drain)

10 polysilicon with underlying

gate oxide

20 silicide

30 silicon nitride

40 side wall oxide

80, 80 ^λ selectively grown areas

90 sidewall spacers

70 oxide layer

100 first silicon oxide

110 second silicon oxide

CB position for bit line contact

I implantation d, d ^Λ height

Claims

1. Production method for a contact in a semiconductor structure which has a substrate (1) with first and second structural elements (GS1, GS2) of approximately the same height which are provided on the substrate surface and which are spaced apart from one another by a space having a critical lateral dimension, with the steps:

Providing an active area (60) in the substrate (1) between the structural elements (GS1, GS2);

Increasing the active area (60) by selectively growing substrate material or conductive material (80); and

Make contact (CB) on the elevated active area.

2. The method according to claim 1, characterized in that before the elevation of the active region (60) by selective growth, an oxide (70) is provided on the surface of the substrate (1) and this oxide (70) over the active region (60) is opened.

3. The method according to claim 1 or 2, characterized in that a side wall spacer (90) is formed on the two structural elements (GS1, GS2) by selective growth before or after the elevation of the active area (60).

4. The method according to claim 1, 2 or 3, so that after formation of the side wall spacer (90) and the raised active area, a self-aligned implantation into the raised active area takes place.

5. The method according to any one of the preceding claims, characterized in that the two structural elements (GSl, GS2) after the selective growth are embedded in at least one insulation layer (100, 110) and a contact hole for the contact (CB) in the at least one insulation layer ( 100, 110) is provided.

6. The method according to claim 4, characterized in that two insulation layers (100, 110) are provided, which are a first (100) and second (110) silicon dioxide layer or nitrided SiO _x layer.

7. The method according to any one of the preceding claims, characterized in that the two structural elements (GSl, GS2) a first and second gate stack (GSl, GS2) of a memory cell arrangement and the active region (60) is a source / dain connection of a selection transistor.

8. The method according to claim 7, so that the memory cell arrangement is constructed according to trench technology, the memory cell capacitances being buried in the substrate.

9. The method of claim 7, so that the memory cell arrangement is constructed according to the stacking technology, the memory cell capacitances being stacked over the substrate.

10. The method according to any one of the preceding claims, characterized in that at least one further active region (60 ^Λ ) is provided in the substrate (1) between the structural elements (GS1, GS2) and the further active region (60 ^Λ ) when increasing the active area (60) is also increased by selective growth of substrate material or conductive material (80 ^Λ ).

11. The method according to claim 10, which also means that the further active area (60) is a connection of a

Memory cell capacity.

12. The method according to any one of the preceding claims, that the active region (60) is increased by selectively growing substrate material or conductive material (80) up to approximately half the height (d) of the two structural elements (GS1, GS2).

13. Contact in a semiconductor structure which has a substrate (1) with first and second structural elements (GS1, GS2) of approximately the same height which are provided on the substrate surface and which are spaced apart by an intermediate space with a critical lateral dimension, with:

an active region (60) in the substrate (1) between the structural elements (GS1, GS2);

an increase in the active area (60) made of substrate material or conductive material (80); and

a contact filling (CB) provided on the elevation