WO2003083956A3 - Enhanced thermal dissipation integrated circuit package and method of manufacturing enhanced thermal dissipation integrated circuit package - Google Patents

Enhanced thermal dissipation integrated circuit package and method of manufacturing enhanced thermal dissipation integrated circuit package Download PDF

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Publication number
WO2003083956A3
WO2003083956A3 PCT/US2003/008928 US0308928W WO03083956A3 WO 2003083956 A3 WO2003083956 A3 WO 2003083956A3 US 0308928 W US0308928 W US 0308928W WO 03083956 A3 WO03083956 A3 WO 03083956A3
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WO
WIPO (PCT)
Prior art keywords
integrated circuit
circuit package
thermal dissipation
enhanced thermal
dissipation integrated
Prior art date
Application number
PCT/US2003/008928
Other languages
French (fr)
Other versions
WO2003083956A9 (en
WO2003083956A2 (en
Inventor
Edward G Combs
Neil R Mcclellan
Chun Ho Fan
Original Assignee
Asat Ltd
Edward G Combs
Neil R Mcclellan
Chun Ho Fan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asat Ltd, Edward G Combs, Neil R Mcclellan, Chun Ho Fan filed Critical Asat Ltd
Priority to AU2003225950A priority Critical patent/AU2003225950A1/en
Publication of WO2003083956A2 publication Critical patent/WO2003083956A2/en
Publication of WO2003083956A3 publication Critical patent/WO2003083956A3/en
Publication of WO2003083956A9 publication Critical patent/WO2003083956A9/en

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    • H—ELECTRICITY
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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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Abstract

The present invention relates to an integrated circuit packages (5) having a thermally conductive element (120) thermally coupled to a heat sink (119) and semiconductor die (130), and a method of manufacturing said integrated circuit package.
PCT/US2003/008928 2002-03-22 2003-03-21 Enhanced thermal dissipation integrated circuit package and method of manufacturing enhanced thermal dissipation integrated circuit package WO2003083956A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003225950A AU2003225950A1 (en) 2002-03-22 2003-03-21 Enhanced thermal dissipation integrated circuit package and method of manufacturing enhanced thermal dissipation integrated circuit package

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/104,263 2002-03-22
US10/104,263 US20030178719A1 (en) 2002-03-22 2002-03-22 Enhanced thermal dissipation integrated circuit package and method of manufacturing enhanced thermal dissipation integrated circuit package

Publications (3)

Publication Number Publication Date
WO2003083956A2 WO2003083956A2 (en) 2003-10-09
WO2003083956A3 true WO2003083956A3 (en) 2004-02-05
WO2003083956A9 WO2003083956A9 (en) 2004-04-29

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PCT/US2003/008928 WO2003083956A2 (en) 2002-03-22 2003-03-21 Enhanced thermal dissipation integrated circuit package and method of manufacturing enhanced thermal dissipation integrated circuit package

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US (2) US20030178719A1 (en)
AU (1) AU2003225950A1 (en)
WO (1) WO2003083956A2 (en)

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US6607937B1 (en) 2000-08-23 2003-08-19 Micron Technology, Inc. Stacked microelectronic dies and methods for stacking microelectronic dies
JP3627738B2 (en) * 2001-12-27 2005-03-09 株式会社デンソー Semiconductor device
SG121707A1 (en) 2002-03-04 2006-05-26 Micron Technology Inc Method and apparatus for flip-chip packaging providing testing capability
SG111935A1 (en) * 2002-03-04 2005-06-29 Micron Technology Inc Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods
US20040212080A1 (en) * 2003-04-22 2004-10-28 Kai-Chi Chen [chip package structure and process for fabricating the same]
US20050093135A1 (en) * 2003-10-31 2005-05-05 Wei-Chi Liu Thermal dissipating element of a chip
KR100632459B1 (en) * 2004-01-28 2006-10-09 삼성전자주식회사 Heat-dissipating semiconductor package and manufacturing method
KR100631403B1 (en) 2004-09-23 2006-10-09 삼성전자주식회사 semiconductor package having heat slug and method for manufacturing the same
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