WO2003100830A3 - Non-volatile multi-threshold cmos latch with leakage control - Google Patents

Non-volatile multi-threshold cmos latch with leakage control Download PDF

Info

Publication number
WO2003100830A3
WO2003100830A3 PCT/US2003/016055 US0316055W WO03100830A3 WO 2003100830 A3 WO2003100830 A3 WO 2003100830A3 US 0316055 W US0316055 W US 0316055W WO 03100830 A3 WO03100830 A3 WO 03100830A3
Authority
WO
WIPO (PCT)
Prior art keywords
latch
circuits
voltage threshold
signal path
master
Prior art date
Application number
PCT/US2003/016055
Other languages
French (fr)
Other versions
WO2003100830A2 (en
Inventor
Mehdi Hamidi Sani
Gregory A Uvieghara
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Priority to DE60324275T priority Critical patent/DE60324275D1/en
Priority to CA002487363A priority patent/CA2487363A1/en
Priority to JP2004508387A priority patent/JP2005527166A/en
Priority to EP03741807A priority patent/EP1510006B1/en
Priority to AU2003273139A priority patent/AU2003273139A1/en
Publication of WO2003100830A2 publication Critical patent/WO2003100830A2/en
Publication of WO2003100830A3 publication Critical patent/WO2003100830A3/en
Priority to HK05107367.5A priority patent/HK1075139A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/356121—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit with synchronous operation

Abstract

An integrated circuit including a Multi-Threshold CMOS (MTCMOS) latch combining low voltage threshold CMOS circuits with high voltage threshold CMOS circuits. The low voltage threshold circuits including a majority of the circuits in the signal path of the latch to ensure high performance of the latch. The latch further including high voltage circuits to eliminate leakage paths from the low voltage threshold circuits when the latch is in a sleep mode. A single-phase latch and a two-phase latch are provided. Each of the latches is implemented with master and slave registers. Data is held in either the master register or the slave register depending on the phase or phases of the clock signals. A multiplexer may alternatively be implemented prior to the master latch for controlling an input signal path during sleep and active modes of the latch and for providing a second input signal path for test.
PCT/US2003/016055 2002-05-24 2003-05-23 Non-volatile multi-threshold cmos latch with leakage control WO2003100830A2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
DE60324275T DE60324275D1 (en) 2002-05-24 2003-05-23 NON-VOLATILE CMOS LATCH WITH MULTIPLE THRESHOLD AND LEAKAGE CURRENT CONTROL
CA002487363A CA2487363A1 (en) 2002-05-24 2003-05-23 Non-volatile multi-threshold cmos latch with leakage control
JP2004508387A JP2005527166A (en) 2002-05-24 2003-05-23 Non-volatile multi-threshold CMOS latch with leakage current control
EP03741807A EP1510006B1 (en) 2002-05-24 2003-05-23 Non-volatile multi-threshold cmos latch with leakage control
AU2003273139A AU2003273139A1 (en) 2002-05-24 2003-05-23 Non-volatile multi-threshold cmos latch with leakage control
HK05107367.5A HK1075139A1 (en) 2002-05-24 2005-08-23 Non-volatile multi-threshold cmos latch with leakage control

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/155,378 US6794914B2 (en) 2002-05-24 2002-05-24 Non-volatile multi-threshold CMOS latch with leakage control
US10/155,378 2002-05-24

Publications (2)

Publication Number Publication Date
WO2003100830A2 WO2003100830A2 (en) 2003-12-04
WO2003100830A3 true WO2003100830A3 (en) 2004-10-07

Family

ID=29549050

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/016055 WO2003100830A2 (en) 2002-05-24 2003-05-23 Non-volatile multi-threshold cmos latch with leakage control

Country Status (10)

Country Link
US (1) US6794914B2 (en)
EP (1) EP1510006B1 (en)
JP (1) JP2005527166A (en)
AT (1) ATE412268T1 (en)
AU (1) AU2003273139A1 (en)
CA (1) CA2487363A1 (en)
DE (1) DE60324275D1 (en)
HK (1) HK1075139A1 (en)
RU (1) RU2321944C2 (en)
WO (1) WO2003100830A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103973268B (en) * 2013-02-05 2018-05-08 德克萨斯仪器股份有限公司 Positive edge trigger with dual-port from latch

Families Citing this family (90)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6989702B2 (en) * 2002-07-11 2006-01-24 Texas Instruments Incorporated Retention register with normal functionality independent of retention power supply
US7091766B2 (en) * 2002-07-11 2006-08-15 Texas Instruments Incorporated Retention register for system-transparent state retention
DE10255636B4 (en) * 2002-11-28 2010-12-02 Infineon Technologies Ag Circuit arrangement
US7294877B2 (en) 2003-03-28 2007-11-13 Nantero, Inc. Nanotube-on-gate FET structures and applications
WO2005019793A2 (en) 2003-05-14 2005-03-03 Nantero, Inc. Sensor platform using a horizontally oriented nanotube element
US7274064B2 (en) 2003-06-09 2007-09-25 Nanatero, Inc. Non-volatile electromechanical field effect devices and circuits using same and methods of forming same
US7211854B2 (en) 2003-06-09 2007-05-01 Nantero, Inc. Field effect devices having a gate controlled via a nanotube switching element
US6946903B2 (en) * 2003-07-28 2005-09-20 Elixent Limited Methods and systems for reducing leakage current in semiconductor circuits
US7289357B2 (en) 2003-08-13 2007-10-30 Nantero, Inc. Isolation structure for deflectable nanotube elements
WO2005048296A2 (en) 2003-08-13 2005-05-26 Nantero, Inc. Nanotube-based switching elements with multiple controls and circuits made from same
JP2005157620A (en) * 2003-11-25 2005-06-16 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit
US7103857B2 (en) * 2003-12-09 2006-09-05 International Business Machines Corporation Method and latch circuit for implementing enhanced performance with reduced quiescent power dissipation using mixed threshold CMOS devices
US7528437B2 (en) * 2004-02-11 2009-05-05 Nantero, Inc. EEPROMS using carbon nanotubes for cell storage
KR20050099259A (en) * 2004-04-09 2005-10-13 삼성전자주식회사 High speed flipflops and complex gates using thereof
US7075175B2 (en) * 2004-04-22 2006-07-11 Qualcomm Incorporated Systems and methods for testing packaged dies
KR101045295B1 (en) * 2004-04-29 2011-06-29 삼성전자주식회사 MTCMOS flip-flop, MTCMOS circuit including the same, and method for generating the same
JP2005323295A (en) * 2004-05-11 2005-11-17 Asahi Kasei Microsystems Kk Latch circuit and flip-flop circuit
JP2006005661A (en) * 2004-06-17 2006-01-05 Matsushita Electric Ind Co Ltd Flip-flop circuit
US7288970B2 (en) 2004-06-18 2007-10-30 Nantero, Inc. Integrated nanotube and field effect switching device
US7164744B2 (en) 2004-06-18 2007-01-16 Nantero, Inc. Nanotube-based logic driver circuits
US7161403B2 (en) * 2004-06-18 2007-01-09 Nantero, Inc. Storage elements using nanotube switching elements
US7652342B2 (en) 2004-06-18 2010-01-26 Nantero, Inc. Nanotube-based transfer devices and related circuits
US8471238B2 (en) 2004-09-16 2013-06-25 Nantero Inc. Light emitters using nanotubes and methods of making same
US7248090B2 (en) 2005-01-10 2007-07-24 Qualcomm, Incorporated Multi-threshold MOS circuits
US8362525B2 (en) * 2005-01-14 2013-01-29 Nantero Inc. Field effect device having a channel of nanofabric and methods of making same
US7598544B2 (en) * 2005-01-14 2009-10-06 Nanotero, Inc. Hybrid carbon nanotude FET(CNFET)-FET static RAM (SRAM) and method of making same
US7180348B2 (en) * 2005-03-24 2007-02-20 Arm Limited Circuit and method for storing data in operational and sleep modes
US7781862B2 (en) 2005-05-09 2010-08-24 Nantero, Inc. Two-terminal nanotube devices and systems and methods of making same
US7479654B2 (en) 2005-05-09 2009-01-20 Nantero, Inc. Memory arrays using nanotube articles with reprogrammable resistance
US7394687B2 (en) 2005-05-09 2008-07-01 Nantero, Inc. Non-volatile-shadow latch using a nanotube switch
TWI324773B (en) 2005-05-09 2010-05-11 Nantero Inc Non-volatile shadow latch using a nanotube switch
US20070008004A1 (en) * 2005-07-11 2007-01-11 Vikram Santurkar Apparatus and methods for low-power routing circuitry in programmable logic devices
US7342287B2 (en) * 2005-07-19 2008-03-11 International Business Machines Corporation Power gating schemes in SOI circuits in hybrid SOI-epitaxial CMOS structures
KR100733447B1 (en) * 2005-09-28 2007-06-29 주식회사 하이닉스반도체 Data output multiplexer for preventing leakage current in memory device
KR100702364B1 (en) 2005-12-07 2007-04-02 한국전자통신연구원 Multi-threshold cmos latch circuit
US7391249B2 (en) * 2005-12-07 2008-06-24 Electronics And Telecommunications Research Institute Multi-threshold CMOS latch circuit
US7420403B2 (en) * 2005-12-08 2008-09-02 Electronics And Telecommunications Research Institute Latch circuit and flip-flop
KR100810501B1 (en) * 2005-12-08 2008-03-07 한국전자통신연구원 Wide-Band Multi-Mode Frequency Composer and Variable Frequency Divider
US7366036B2 (en) * 2006-01-13 2008-04-29 International Business Machines Corporation Memory device with control circuit for regulating power supply voltage
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US8225261B2 (en) 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining contact grid in dynamic array architecture
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US7943967B2 (en) 2006-03-09 2011-05-17 Tela Innovations, Inc. Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US7956421B2 (en) * 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US7932545B2 (en) * 2006-03-09 2011-04-26 Tela Innovations, Inc. Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8245180B2 (en) 2006-03-09 2012-08-14 Tela Innovations, Inc. Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same
US8225239B2 (en) 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining and utilizing sub-resolution features in linear topology
US8247846B2 (en) 2006-03-09 2012-08-21 Tela Innovations, Inc. Oversized contacts and vias in semiconductor chip defined by linearly constrained topology
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US7310278B2 (en) * 2006-05-04 2007-12-18 International Business Machines Corporation Method and apparatus for in-system redundant array repair on integrated circuits
US7979829B2 (en) 2007-02-20 2011-07-12 Tela Innovations, Inc. Integrated circuit cell library with cell-level process compensation technique (PCT) application and associated methods
US8286107B2 (en) 2007-02-20 2012-10-09 Tela Innovations, Inc. Methods and systems for process compensation technique acceleration
US7888705B2 (en) 2007-08-02 2011-02-15 Tela Innovations, Inc. Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
EP2179420A1 (en) * 2007-08-13 2010-04-28 Agere Systems, Inc. Memory device with reduced buffer current during power-down mode
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
SG10201608214SA (en) 2008-07-16 2016-11-29 Tela Innovations Inc Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US8209573B2 (en) * 2008-12-22 2012-06-26 Lsi Corporation Sequential element low power scan implementation
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US8471618B2 (en) 2010-04-12 2013-06-25 Mediatek Inc. Flip-flop for low swing clock signal
US8228109B2 (en) 2010-06-28 2012-07-24 Freescale Semiconductor, Inc. Transmission gate circuitry for high voltage terminal
KR101794261B1 (en) * 2010-11-11 2017-11-08 삼성전자주식회사 Latch circuit, flip-flop having the same and data latching method
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US8207755B1 (en) * 2011-02-15 2012-06-26 Taiwan Semiconductor Manufacturing Company, Ltd. Low leakage power detection circuit
US20120223756A1 (en) * 2011-03-01 2012-09-06 Morteza Afghahi Method and System for High Speed, Low Power and Small Flip-Flops
US8390328B2 (en) 2011-05-13 2013-03-05 Arm Limited Supplying a clock signal and a gated clock signal to synchronous elements
US9083337B2 (en) 2012-01-13 2015-07-14 The Board Of Trustees Of The University Of Arkansas Multi-threshold sleep convention logic without nsleep
US8957716B2 (en) * 2012-11-21 2015-02-17 Broadcom Corporation Multiple threshold voltage standard cells
US8836398B2 (en) * 2013-02-05 2014-09-16 Texas Instruments Incorporated Negative edge flip-flop with dual-port slave latch
US9348402B2 (en) * 2013-02-19 2016-05-24 Qualcomm Incorporated Multiple critical paths having different threshold voltages in a single processor core
US9099998B2 (en) 2013-02-19 2015-08-04 Texas Instruments Incorporated Positive edge preset reset flip-flop with dual-port slave latch
US8970188B2 (en) * 2013-04-05 2015-03-03 Synaptics Incorporated Adaptive frequency compensation for high speed linear voltage regulator
US9673786B2 (en) * 2013-04-12 2017-06-06 Qualcomm Incorporated Flip-flop with reduced retention voltage
US9287858B1 (en) * 2014-09-03 2016-03-15 Texas Instruments Incorporated Low leakage shadow latch-based multi-threshold CMOS sequential circuit
CN106160717B (en) 2015-04-03 2020-08-18 恩智浦美国有限公司 Transmission gate circuit
US9933800B1 (en) 2016-09-30 2018-04-03 Synaptics Incorporated Frequency compensation for linear regulators
US11165430B1 (en) 2020-12-21 2021-11-02 Kepler Computing Inc. Majority logic gate based sequential circuit
US11303280B1 (en) 2021-08-19 2022-04-12 Kepler Computing Inc. Ferroelectric or paraelectric based sequential circuit
JP2023034195A (en) 2021-08-30 2023-03-13 キオクシア株式会社 Flip-flop circuit and asynchronous receiving circuit
CN114253341B (en) * 2021-12-22 2023-03-14 江苏集萃智能集成电路设计技术研究所有限公司 Output circuit and voltage buffer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0964519A2 (en) * 1998-06-12 1999-12-15 Nec Corporation Semiconductor integrated logic circuit with sequential circuits capable of preventing sub-threshold leakage current

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5982211A (en) * 1997-03-31 1999-11-09 Texas Instruments Incorporated Hybrid dual threshold transistor registers
JP2000114935A (en) * 1998-10-02 2000-04-21 Nec Corp Sequential circuit
US6231147B1 (en) * 1999-04-19 2001-05-15 Texas Instruments Incorporated Data storage circuits using a low threshold voltage output enable circuit
JP3614125B2 (en) * 2000-10-23 2005-01-26 三星電子株式会社 CP flip-flop
JP3548115B2 (en) * 2000-12-26 2004-07-28 株式会社東芝 Semiconductor integrated circuit and semiconductor integrated circuit device
US6538471B1 (en) * 2001-10-10 2003-03-25 International Business Machines Corporation Multi-threshold flip-flop circuit having an outside feedback

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0964519A2 (en) * 1998-06-12 1999-12-15 Nec Corporation Semiconductor integrated logic circuit with sequential circuits capable of preventing sub-threshold leakage current

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
SHIGEMATSU S ET AL: "A 1-V HIGH-SPEED MTCMOS CIRCUIT SCHEME FOR POWER-DOWN APPLICATION CIRCUITS", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE INC. NEW YORK, US, vol. 32, no. 6, 1 June 1997 (1997-06-01), pages 861 - 869, XP000723409, ISSN: 0018-9200 *
SHIGEMATSU S ET AL: "A 1-V high-speed MTCMOS circuit scheme for power-down applications", 1995, TOKYO, JAPAN, JAPAN SOC. APPLIED PHYS, JAPAN, 8 June 1995 (1995-06-08), pages 125 - 126, XP002290318, ISBN: 0-7803-2599-0 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103973268B (en) * 2013-02-05 2018-05-08 德克萨斯仪器股份有限公司 Positive edge trigger with dual-port from latch

Also Published As

Publication number Publication date
CA2487363A1 (en) 2003-12-04
ATE412268T1 (en) 2008-11-15
EP1510006A2 (en) 2005-03-02
WO2003100830A2 (en) 2003-12-04
US6794914B2 (en) 2004-09-21
DE60324275D1 (en) 2008-12-04
AU2003273139A1 (en) 2003-12-12
RU2004137817A (en) 2005-06-10
JP2005527166A (en) 2005-09-08
RU2321944C2 (en) 2008-04-10
EP1510006B1 (en) 2008-10-22
US20030218231A1 (en) 2003-11-27
AU2003273139A8 (en) 2003-12-12
HK1075139A1 (en) 2005-12-02

Similar Documents

Publication Publication Date Title
WO2003100830A3 (en) Non-volatile multi-threshold cmos latch with leakage control
US6938225B2 (en) Scan design for double-edge-triggered flip-flops
Kao et al. MTCMOS sequential circuits
US6492854B1 (en) Power efficient and high performance flip-flop
US6784699B2 (en) Glitch free clock multiplexing circuit with asynchronous switch control and minimum switch over time
CN103684355B (en) Gated clock latch, its operational approach and adopt its integrated circuit
KR100574967B1 (en) Controller for Multi-Threshold CMOS
US20080315931A1 (en) Semiconductor integrated circuit having active and sleep modes and non-retention flip-flop that is initialized when switching from sleep mode to active mode
JPH11289246A (en) Semiconductor integrated circuit
US8330518B2 (en) Low consumption flip-flop circuit with data retention and method thereof
US8013628B2 (en) Circuit having an active clock shielding structure and semiconductor intergrated circuit including the same
US6781411B2 (en) Flip flop with reduced leakage current
JP3587299B2 (en) Semiconductor integrated circuit
US6998895B2 (en) System for reducing leakage in integrated circuits during sleep mode
US20020000858A1 (en) Flip-flop circuit
JP2007172587A (en) Chip and system
KR100446303B1 (en) Clocked-scan flip-flop for multi-threshold voltage CMOS circuit
JP5627163B2 (en) Data holding method and circuit in operation mode and sleep mode
JP2004208108A (en) Integrated circuit
TWI426378B (en) System and method for power domain isolation

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NI NO NZ OM PH PL PT RO RU SC SD SE SG SK SL TJ TM TN TR TT TZ UA UG UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 2487363

Country of ref document: CA

WWE Wipo information: entry into national phase

Ref document number: 2004508387

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 2003741807

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2004137817

Country of ref document: RU

Kind code of ref document: A

WWP Wipo information: published in national office

Ref document number: 2003741807

Country of ref document: EP