WO2003107444A2 - Light-emitting diode device geometry - Google Patents

Light-emitting diode device geometry Download PDF

Info

Publication number
WO2003107444A2
WO2003107444A2 PCT/US2003/019036 US0319036W WO03107444A2 WO 2003107444 A2 WO2003107444 A2 WO 2003107444A2 US 0319036 W US0319036 W US 0319036W WO 03107444 A2 WO03107444 A2 WO 03107444A2
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor layer
type semiconductor
region
bonding pad
finger
Prior art date
Application number
PCT/US2003/019036
Other languages
French (fr)
Other versions
WO2003107444A3 (en
Inventor
John C. C. Fan
Tchang-Hun Oh
Hong K. Choi
Jyh Chia Chen
Jagdish Narayan
Original Assignee
Kopin Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/187,466 external-priority patent/US20040000672A1/en
Priority claimed from US10/187,465 external-priority patent/US6734091B2/en
Priority claimed from US10/187,468 external-priority patent/US7002180B2/en
Application filed by Kopin Corporation filed Critical Kopin Corporation
Priority to AU2003251541A priority Critical patent/AU2003251541A1/en
Publication of WO2003107444A2 publication Critical patent/WO2003107444A2/en
Publication of WO2003107444A3 publication Critical patent/WO2003107444A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/918—Light emitting regenerative switching device, e.g. light emitting scr arrays, circuitry

Definitions

  • GaN-based LEDs have been found to exhibit efficient light emission at room temperature.
  • GaN-based LEDs comprise a multilayer structure in which n-type and p-type GaN-based semiconductor layers are stacked on a substrate (most commonly on a sapphire substrate with the n-type GaN-based semiconductor layer in contact with the substrate), and a light-transmissive metal electrode layer is formed over the p-type semiconductor layer.
  • an active region (which can be a single or multiple quantum well structure, for example) is disposed between the p-type and n-type semiconductor layers.
  • each of the layers of the multilayer structure has a four-sided planar top surface.
  • the p-side and the n-side electrical contacts are normally both made on the top side of the device.
  • a portion of the top side of the device is etched to expose one corner or edge of the n-type semiconductor layer, and an n-electrode (i.e. bonding pad) of a suitable metallic material is deposited on the exposed corner or edge of the n-type semiconductor layer.
  • the p-side contact is made by forming a bonding pad of a metallic material on the top surface of the light- transmissive p-electrode layer.
  • the present invention is a semiconductor device, such as a semiconductor light emitting diode (LED) comprising a substrate, and an n-type semiconductor layer over the substrate, the n-type semiconductor layer having a planar top surface.
  • the device also includes a p-type semiconductor layer extending over a major portion of the n-type semiconductor layer, and a p-electrode layer extending over the top surface of the p-type semiconductor layer.
  • the p-type semiconductor layer and the p-electrode layer do not extend over an exposed region of the n-type semiconductor layer, the exposed region located adjacent to at least one edge of the planar top surface of the n-type semiconductor layer.
  • An n-electrode bonding pad is provided on the exposed region of the n-type semiconductor layer.
  • a second bonding pad is provided on the p-electrode layer, the second bonding pad preferably covering an area of the p-electrode layer that approximately corresponds to the geometric center of the planar top surface of the p-electrode layer.
  • the bonding pad on the p-electrode layer can comprise a central region for securing an electrical interconnect (such as a bonding wire), and at least one finger-like region protruding from the central region.
  • the finger-like region has a length extending away from the central region, and a width that is substantially less than the length.
  • the length dimension of the finger-like region extends generally parallel to an edge of the n- type semiconductor layer.
  • the bonding pad includes two fmger-like regions extending away from the central region generally perpendicular to one another.
  • the n-electrode bonding pad can comprise a central region for securing an electrical interconnect (such as a bonding wire), and at least one finger-like region protruding from the central region, hi general, the finger-like region has a length extending away from the central region, and a width that is substantially less than the length.
  • the finger-like regions generally extend adjacent to one or more edges of the n-type semiconductor layer, hi general, the finger-like regions extend adjacent to no more than about 50 percent of the outer perimeter of the n-type semiconductor layer.
  • the bonding pad on the p-electrode layer and the bonding pad on the n-type semiconductor layer are each made from a metallic material of one or more metals (such as gold, titanium, aluminum, indium, platinum, and palladium).
  • each of the bonding pads can be made from a substantially identical material.
  • the device geometry of the present invention provides improved uniformity of the current injection in the active layers of the LED, and thus results in improved device efficiency, i particular, the finger-like protrusions of the p-bonding pad facilitates current spreading over the entire area of the p-electrode layer. This helps reduce the operating voltage of the device, and improves device efficiency.
  • the finger-like protrusions of the n-bonding pad improve current spreading in the n-type semiconductor layer, which further helps reduce operating voltage and improve device efficiency.
  • Fig. 1 is a schematic cross-sectional view of a semiconductor light emitting diode (LED);
  • Fig. 2 is a top view of a semiconductor LED showing the geometric configuration of the p- and n- electrical contacts
  • Fig. 3 is a top view of a semiconductor LED showing an alternative configuration of the p- and n- electrical contacts
  • Fig. 4 is a top view of a semiconductor LED showing yet another alternative configuration of the p- and n- electrical contacts.
  • the present invention relates in general to semiconductor devices, and in particular to semiconductor light emitting diodes (LEDs).
  • the LEDs of the present invention include at least one layer of a GaN- based semiconductor material.
  • GaN-based semiconductor material includes a semiconductor material that can be represented by the formula In x Al y Ga 1.x.y N, where 0 ⁇ x ⁇ l, O ⁇ y ⁇ l, and x+y ⁇ l.
  • the LED device 100 includes a substrate 101, which in this example comprises a sapphire substrate. Directly above the substrate 101 is a layer of n-type GaN-based semiconductor material 102.
  • the n-type semiconductor layer 102 is preferably doped with an n-type dopant, such as silicon (Si), germanium (Ge), selenium (Se), sulfur (S), or tellurium (Te).
  • an n-type dopant such as silicon (Si), germanium (Ge), selenium (Se), sulfur (S), or tellurium (Te).
  • An undoped GaN-based material exhibiting an n-type conductivity could also be used.
  • an active region comprises a region of semiconductor material that has a band gap which is smaller than the band gap of the semiconductor layers on either side of the active region.
  • the larger band gap n-type and p-type semiconductor materials create potential barriers on both sides of the active region and cause carriers (i.e., holes and electrons) to be confined in the active region, where they can combine to emit light.
  • the active region 103 comprises a multiple quantum well structure of alternately stacked In x Ga ⁇ _ x N/GaN layers.
  • a layer of a p-type GaN-based semiconductor material 104 Above the active region 103 is a layer of a p-type GaN-based semiconductor material 104.
  • the active region 103 could also comprise a single quantum well structure. Also, in other embodiments, the active region could be eliminated entirely, and the n-type and p-type semiconductor layers 102, 104 can be made in direct contact with each other.
  • a p-type gallium nitride-based semiconductor material is a gallium nitride-based semiconductor material that includes a p-type dopant.
  • the p-type dopants (also called an acceptor) for gallium nitride-based semiconductor materials include Group II elements such as cadmium, zinc, beryllium, magnesium, calcium, strontium, and barium.
  • Preferred p-type dopants are magnesium and zinc.
  • gaseous compounds containing hydrogen atoms are thermally decomposed to form the semiconductor material.
  • the released hydrogen atoms which are present mainly as protons, become trapped in the growing semiconductor material, and combine with p-type dopant inhibiting their acceptor function.
  • the material may be placed in a high electric field, typically above 10,000 volts/cm for about 10 minutes or more.
  • the protons trapped in the semiconductor material are drawn out of the material to the negative electrode, thereby activating the function of the p-type dopants (see U.S. Patent Application No. 10/127,345, the entire teachings of which are incorporated herein by reference).
  • the conductivity of the p-type gallium nitride-based semiconductor material can be improved by annealing the material at a temperature above 600°C in a nitrogen environment for 10 minutes or more (see U.S. Patent No. 5,306,662, the entire teachings of which are incorporated herein by reference).
  • a p-electrode layer 105 Directly above the p-type semiconductor layer 104 is a p-electrode layer 105.
  • the p-type electrode layer is formed of a metallic material of one or more metals (such as gold, nickel, platinum, aluminum, tin, indium, chromium, and titanium).
  • the metallic material is deposited over substantially the entire top surface of the p-type semiconductor layer, and is annealed at a high-temperature (e.g. > 450°C), preferably in an oxygen-containing environment.
  • the p-electrode layer 105 is preferably light transmissive, meaning that it is able to transmit at least 1% of the light emitted from the gallium nitride-based semiconductor device therethrough, and typically transmits about 50% or more of the light emitted from the gallium nitride-based semiconductor device.
  • the p-electrode layer 105 preferably forms an ohmic contact with the p-type semiconductor layer over an area where two materials are in contact, such that the current flowing through the interface between the two layers is approximately proportional to the potential difference between the layers.
  • the LED of Fig. 1 additionally includes an n-bonding pad 106 and a p- bonding pad 107 for providing electrical contact to the device.
  • the n-bonding pad 106 is formed of a metallic material of one or more metals (such as gold, titanium, aluminum, indium, platinum, and palladium) deposited on an exposed surface of the n-type semiconductor layer 102.
  • the exposed surface of the n-type layer is generally produced by etching the upper layers of the device to expose a region of the n-type semiconductor layer. In general, the exposed region of the n-type semiconductor layer is adjacent to at least one edge of the planar top surface of the layer.
  • the p-bonding pad 107 is formed of a metallic material of one or more metals (such as gold, titanium, aluminum, indium, platinum, and palladium) deposited on the p-electrode layer 105.
  • FIG. 2 top view of a semiconductor LED 100 according to the present invention is shown.
  • the device has four sides forming a generally rectangular shape.
  • the four sides generally correspond to the four sides of the planar top surface of the n-type semiconductor layer (not shown).
  • a p-electrode layer 105 covers the major portion of the rectangular shape, but does not cover an area adjacent to at least one edge of the rectangularly-shaped LED.
  • a p-bonding pad 107 is located over the p-electrode layer 105.
  • the p-bonding bad 107 is located approximately in the geometric center of the p-electrode layer 105.
  • the p-bonding pad 107 includes a central region 201 for securing an electrical interconnect (e.g.
  • a bonding wire a bonding wire
  • two finger-like regions 202, 203 protruding from the central region 201.
  • the finger-like regions have a length extending away from the central region, and a width that is substantially less than the length.
  • a first finger-like region 202 extends away from the central region 201 parallel to one side of the rectangularly-shaped LED
  • a second finger-like region 203 extends away from the central region 201 parallel to another side of the LED.
  • the two finger-like regions 202, 203 extend away from the central region 201 in a generally perpendicular direction relative to one another.
  • An n-bonding pad 106 is provided adjacent to at least one edge of the rectangularly-shaped LED device.
  • the n-bonding pad 106 is located in an area of the device not covered by the p-electrode layer 105. hi general, the n-bonding pad is located on an exposed region of the n-type semiconductor layer (not shown).
  • the n-bonding pad 106 includes a central region 204 for securing an electrical interconnect (e.g. a bonding wire), and two finger-like regions 205, 206 extending away from the central region 204. As shown in Fig. 2, the central region 204 can be located in a corner of the device.
  • a first finger-like region of the n- bonding pad 205 extends along a first edge of the device on one side of the central region 204, and a second finger-like region of the n-bonding pad 206 extends along a second edge of the device on the other side of the central region 204.
  • Fig. 3 shows an alternative design for the device.
  • the central region 204 of the n-bonding pad is located in a corner of the generally rectangularly-shaped LED.
  • a first finger-like region 206 extends along a first edge of the device on one side of the central region 204.
  • a second finger-like region 207 adjoins the far end of the first finger-like region 206 opposite the central region 204, and extends along a second edge towards the corner of the device directly opposite the corner in which the central region 204 is located.
  • the p-electrode layer 105 extends substantially over the remaining area of the device not covered by the n-bonding pad 106, and the p-bonding pad 107 is provided over the approximate geometric center of the p- electrode layer 105.
  • Fig. 4 yet another alternative embodiment is shown.
  • the finger-like regions of the n-bonding pad 205, 206, 207 extend to parts of three adjacent edges of the rectangularly-shaped LED.
  • n-bonding pads may be utilized in accordance with the present invention.
  • thin finger-like protrusions can be provided to either the n-bonding pad or the p- bonding pad (or both) to help facilitate cunent spreading and uniform cunent flow in the device.
  • the finger-like regions of the n-bonding pad extend over no more than about 50 percent of the total perimeter of the LED chip.
  • the semiconductor device layers can be produced by a vapor phase growth method such as metalorganic chemical vapor deposition (MOCND or MOVPE), hydride chemical vapor deposition (HDCVD), or molecular beam epitaxy (MBE).
  • MOCND or MOVPE metalorganic chemical vapor deposition
  • HDCVD hydride chemical vapor deposition
  • MBE molecular beam epitaxy
  • the exposed region of the n-type semiconductor layer for providing the n-bonding pad 106 can then be defined by a conventional plasma-assisted etching technique.
  • the n-bonding pad 106 and the p-bonding pad 107 can be fonned by conventional metal deposition techniques (e.g. evaporation by electron-beam and/or resistive heating or sputtering).
  • the design of the bonding pads i.e. the central region and the finger-like region(s)
  • the fingers can be defined at the same time as the central regions for each of the p- and n-bonding pads.
  • the p- and n-bonding pads are each formed of a three-layer metal stack comprising a first layer of palladium, a second layer of aluminum, and a third layer of gold deposited by electron-beam evaporation.
  • the metal stacks are then annealed at a temperature of 450 degrees C or higher.

Abstract

A semiconductor device includes: a substrate; an n-type semiconductor layer over the substrate, the n-type semiconductor layer having a planar top surface; a p-type semiconductor layer extending over a major portion of the n-type semiconductor layer and not extending over an exposed region of the n-type semiconductor layer located adjacent to at least one edge of the planar top surface of the n-type semiconductor layer; a first bonding pad provided on the exposed region of the n-type semiconductor layer; an electrode layer extending over the p-type semiconductor layer; and a second bonding pad on the electrode layer, the bonding pad including a central region for securing an electrical interconnect, and at least one finger-like region protruding from the central region, the finger-like region having a length extending away from the central region and a width that is substantially less than the length. A method for producing a semiconductor device also is described.

Description

LIGHT-EMITTING DIODE DEVICE GEOMETRY
RELATED APPLICATIONS
This application claims the benefit of U.S. Provisional Application No. 60/389,750, filed June 17, 2002 and U.S. Provisional Application No. 60/393,008, filed June 28, 2002. This application is a continuation-in-part of: U.S. Application No. 10/187,466, filed June 28, 2002; U.S. Application No. 10/187,465, filed June 28, 2002; and U.S. Application No. 10/187,468, filed June 28, 2002. This application is related to U.S. Provisional Application: Domain Epitaxy) for Thin Film Growth, by Jagdish Narayan, filed concurrently herewith under Attorney Docket No. 0717.2033-001. The entire teachings of the above applications are incorporated herein by reference.
BACKGROUND OF THE INVENTION
Recently, much attention has been focused on JJI-V nitride-based semiconductors, and particularly GaN-based semiconductors, for blue, green, and ultraviolet light emitting diode (LED) applications. One important reason is that GaN-based LEDs have been found to exhibit efficient light emission at room temperature.
In general, GaN-based LEDs comprise a multilayer structure in which n-type and p-type GaN-based semiconductor layers are stacked on a substrate (most commonly on a sapphire substrate with the n-type GaN-based semiconductor layer in contact with the substrate), and a light-transmissive metal electrode layer is formed over the p-type semiconductor layer. In certain embodiments, an active region (which can be a single or multiple quantum well structure, for example) is disposed between the p-type and n-type semiconductor layers. In general, each of the layers of the multilayer structure has a four-sided planar top surface. Because the substrate is normally comprised of an electrically insulative material, such as sapphire, the p-side and the n-side electrical contacts are normally both made on the top side of the device. In general, a portion of the top side of the device is etched to expose one corner or edge of the n-type semiconductor layer, and an n-electrode (i.e. bonding pad) of a suitable metallic material is deposited on the exposed corner or edge of the n-type semiconductor layer. The p-side contact is made by forming a bonding pad of a metallic material on the top surface of the light- transmissive p-electrode layer.
SUMMARY OF THE INVENTION
The present invention is a semiconductor device, such as a semiconductor light emitting diode (LED) comprising a substrate, and an n-type semiconductor layer over the substrate, the n-type semiconductor layer having a planar top surface. The device also includes a p-type semiconductor layer extending over a major portion of the n-type semiconductor layer, and a p-electrode layer extending over the top surface of the p-type semiconductor layer. The p-type semiconductor layer and the p-electrode layer do not extend over an exposed region of the n-type semiconductor layer, the exposed region located adjacent to at least one edge of the planar top surface of the n-type semiconductor layer. An n-electrode bonding pad is provided on the exposed region of the n-type semiconductor layer. A second bonding pad is provided on the p-electrode layer, the second bonding pad preferably covering an area of the p-electrode layer that approximately corresponds to the geometric center of the planar top surface of the p-electrode layer.
According to yet another aspect, the bonding pad on the p-electrode layer can comprise a central region for securing an electrical interconnect (such as a bonding wire), and at least one finger-like region protruding from the central region. In general, the finger-like region has a length extending away from the central region, and a width that is substantially less than the length. In one embodiment, the length dimension of the finger-like region extends generally parallel to an edge of the n- type semiconductor layer. In yet another embodiment, the bonding pad includes two fmger-like regions extending away from the central region generally perpendicular to one another.
According to yet another aspect, the n-electrode bonding pad can comprise a central region for securing an electrical interconnect (such as a bonding wire), and at least one finger-like region protruding from the central region, hi general, the finger-like region has a length extending away from the central region, and a width that is substantially less than the length. The finger-like regions generally extend adjacent to one or more edges of the n-type semiconductor layer, hi general, the finger-like regions extend adjacent to no more than about 50 percent of the outer perimeter of the n-type semiconductor layer.
Typically, the bonding pad on the p-electrode layer and the bonding pad on the n-type semiconductor layer are each made from a metallic material of one or more metals (such as gold, titanium, aluminum, indium, platinum, and palladium). In certain embodiments, each of the bonding pads can be made from a substantially identical material.
The device geometry of the present invention provides improved uniformity of the current injection in the active layers of the LED, and thus results in improved device efficiency, i particular, the finger-like protrusions of the p-bonding pad facilitates current spreading over the entire area of the p-electrode layer. This helps reduce the operating voltage of the device, and improves device efficiency. In addition, the finger-like protrusions of the n-bonding pad improve current spreading in the n-type semiconductor layer, which further helps reduce operating voltage and improve device efficiency.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. Fig. 1 is a schematic cross-sectional view of a semiconductor light emitting diode (LED);
Fig. 2 is a top view of a semiconductor LED showing the geometric configuration of the p- and n- electrical contacts; Fig. 3 is a top view of a semiconductor LED showing an alternative configuration of the p- and n- electrical contacts; and
Fig. 4 is a top view of a semiconductor LED showing yet another alternative configuration of the p- and n- electrical contacts.
DETAILED DESCRIPTION OF THE INVENTION A description of preferred embodiments of the invention follows.
The present invention relates in general to semiconductor devices, and in particular to semiconductor light emitting diodes (LEDs). In particular embodiments, the LEDs of the present invention include at least one layer of a GaN- based semiconductor material. As used herein, the term "GaN-based semiconductor material" includes a semiconductor material that can be represented by the formula InxAlyGa1.x.yN, where 0<x≤l, O≤y≤l, and x+y<l.
Turning now to Fig. 1, an example of a GaN-based LED is shown in schematic cross-section. The LED device 100 includes a substrate 101, which in this example comprises a sapphire substrate. Directly above the substrate 101 is a layer of n-type GaN-based semiconductor material 102. The n-type semiconductor layer 102 is preferably doped with an n-type dopant, such as silicon (Si), germanium (Ge), selenium (Se), sulfur (S), or tellurium (Te). An undoped GaN-based material exhibiting an n-type conductivity could also be used.
Above the n-type semiconductor layer 102 is an active region 103, followed by a layer of p-type semiconductor material 104. In general, an active region comprises a region of semiconductor material that has a band gap which is smaller than the band gap of the semiconductor layers on either side of the active region. The larger band gap n-type and p-type semiconductor materials create potential barriers on both sides of the active region and cause carriers (i.e., holes and electrons) to be confined in the active region, where they can combine to emit light. I this embodiment, the active region 103 comprises a multiple quantum well structure of alternately stacked InxGaι_xN/GaN layers. Above the active region 103 is a layer of a p-type GaN-based semiconductor material 104.
It will be understood that in addition to a multiple quantum well structure, the active region 103 could also comprise a single quantum well structure. Also, in other embodiments, the active region could be eliminated entirely, and the n-type and p-type semiconductor layers 102, 104 can be made in direct contact with each other.
Above the active region 103 is a p-type GaN-based semiconductor layer 104. hi general, a p-type gallium nitride-based semiconductor material is a gallium nitride-based semiconductor material that includes a p-type dopant. The p-type dopants (also called an acceptor) for gallium nitride-based semiconductor materials include Group II elements such as cadmium, zinc, beryllium, magnesium, calcium, strontium, and barium. Preferred p-type dopants are magnesium and zinc. Typically, during growth of the gallium nitride-based semiconductor material gaseous compounds containing hydrogen atoms are thermally decomposed to form the semiconductor material. The released hydrogen atoms, which are present mainly as protons, become trapped in the growing semiconductor material, and combine with p-type dopant inhibiting their acceptor function. To improve the conductivity of a p-type gallium nitride-based semiconductor material, the material may be placed in a high electric field, typically above 10,000 volts/cm for about 10 minutes or more. The protons trapped in the semiconductor material are drawn out of the material to the negative electrode, thereby activating the function of the p-type dopants (see U.S. Patent Application No. 10/127,345, the entire teachings of which are incorporated herein by reference). Alternatively, the conductivity of the p-type gallium nitride-based semiconductor material can be improved by annealing the material at a temperature above 600°C in a nitrogen environment for 10 minutes or more (see U.S. Patent No. 5,306,662, the entire teachings of which are incorporated herein by reference). Directly above the p-type semiconductor layer 104 is a p-electrode layer 105. hi general, the p-type electrode layer is formed of a metallic material of one or more metals (such as gold, nickel, platinum, aluminum, tin, indium, chromium, and titanium). The metallic material is deposited over substantially the entire top surface of the p-type semiconductor layer, and is annealed at a high-temperature (e.g. > 450°C), preferably in an oxygen-containing environment. The p-electrode layer 105 is preferably light transmissive, meaning that it is able to transmit at least 1% of the light emitted from the gallium nitride-based semiconductor device therethrough, and typically transmits about 50% or more of the light emitted from the gallium nitride-based semiconductor device.
The p-electrode layer 105 preferably forms an ohmic contact with the p-type semiconductor layer over an area where two materials are in contact, such that the current flowing through the interface between the two layers is approximately proportional to the potential difference between the layers.
The LED of Fig. 1 additionally includes an n-bonding pad 106 and a p- bonding pad 107 for providing electrical contact to the device. The n-bonding pad 106 is formed of a metallic material of one or more metals (such as gold, titanium, aluminum, indium, platinum, and palladium) deposited on an exposed surface of the n-type semiconductor layer 102. The exposed surface of the n-type layer is generally produced by etching the upper layers of the device to expose a region of the n-type semiconductor layer. In general, the exposed region of the n-type semiconductor layer is adjacent to at least one edge of the planar top surface of the layer.
The p-bonding pad 107 is formed of a metallic material of one or more metals (such as gold, titanium, aluminum, indium, platinum, and palladium) deposited on the p-electrode layer 105.
Turning now to Fig. 2, top view of a semiconductor LED 100 according to the present invention is shown. The device has four sides forming a generally rectangular shape. The four sides generally correspond to the four sides of the planar top surface of the n-type semiconductor layer (not shown). A p-electrode layer 105 covers the major portion of the rectangular shape, but does not cover an area adjacent to at least one edge of the rectangularly-shaped LED. A p-bonding pad 107 is located over the p-electrode layer 105. The p-bonding bad 107 is located approximately in the geometric center of the p-electrode layer 105. The p-bonding pad 107 includes a central region 201 for securing an electrical interconnect (e.g. a bonding wire), and two finger-like regions 202, 203 protruding from the central region 201. In general, the finger-like regions have a length extending away from the central region, and a width that is substantially less than the length. As shown in Fig. 2, a first finger-like region 202 extends away from the central region 201 parallel to one side of the rectangularly-shaped LED, and a second finger-like region 203 extends away from the central region 201 parallel to another side of the LED. The two finger-like regions 202, 203 extend away from the central region 201 in a generally perpendicular direction relative to one another. An n-bonding pad 106 is provided adjacent to at least one edge of the rectangularly-shaped LED device. The n-bonding pad 106 is located in an area of the device not covered by the p-electrode layer 105. hi general, the n-bonding pad is located on an exposed region of the n-type semiconductor layer (not shown). The n-bonding pad 106 includes a central region 204 for securing an electrical interconnect (e.g. a bonding wire), and two finger-like regions 205, 206 extending away from the central region 204. As shown in Fig. 2, the central region 204 can be located in a corner of the device. A first finger-like region of the n- bonding pad 205 extends along a first edge of the device on one side of the central region 204, and a second finger-like region of the n-bonding pad 206 extends along a second edge of the device on the other side of the central region 204.
Fig. 3 shows an alternative design for the device. Here, the central region 204 of the n-bonding pad is located in a corner of the generally rectangularly-shaped LED. A first finger-like region 206 extends along a first edge of the device on one side of the central region 204. A second finger-like region 207 adjoins the far end of the first finger-like region 206 opposite the central region 204, and extends along a second edge towards the corner of the device directly opposite the corner in which the central region 204 is located. The p-electrode layer 105 extends substantially over the remaining area of the device not covered by the n-bonding pad 106, and the p-bonding pad 107 is provided over the approximate geometric center of the p- electrode layer 105.
In Fig. 4, yet another alternative embodiment is shown. Here, the finger-like regions of the n-bonding pad 205, 206, 207 extend to parts of three adjacent edges of the rectangularly-shaped LED.
It will be understood that various alternative designs for both the p- and n- bonding pads may be utilized in accordance with the present invention. In general, thin finger-like protrusions can be provided to either the n-bonding pad or the p- bonding pad (or both) to help facilitate cunent spreading and uniform cunent flow in the device. Typically, the finger-like regions of the n-bonding pad extend over no more than about 50 percent of the total perimeter of the LED chip.
A method for producing an LED device in accordance with the present invention is now described. In general, the semiconductor device layers can be produced by a vapor phase growth method such as metalorganic chemical vapor deposition (MOCND or MOVPE), hydride chemical vapor deposition (HDCVD), or molecular beam epitaxy (MBE). The exposed region of the n-type semiconductor layer for providing the n-bonding pad 106 can then be defined by a conventional plasma-assisted etching technique.
The n-bonding pad 106 and the p-bonding pad 107 can be fonned by conventional metal deposition techniques (e.g. evaporation by electron-beam and/or resistive heating or sputtering). The design of the bonding pads (i.e. the central region and the finger-like region(s)) can be defined by a standard photolithography and metal-patterning (etching or liftoff) process. The fingers can be defined at the same time as the central regions for each of the p- and n-bonding pads.
In a prefereed embodiment, the p- and n-bonding pads are each formed of a three-layer metal stack comprising a first layer of palladium, a second layer of aluminum, and a third layer of gold deposited by electron-beam evaporation. The metal stacks are then annealed at a temperature of 450 degrees C or higher. While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.

Claims

CLAIMSWhat is claimed is:
1. A semiconductor device comprising: a substrate; an n-type semiconductor layer over the substrate, the n-type semiconductor layer having a planar top surface; a p-type semiconductor layer extending over a major portion of the n- type semiconductor layer and not extending over an exposed region of the n- type semiconductor layer located adjacent to at least one edge of the planar top surface of the n-type semiconductor layer; a first bonding pad provided on the exposed region of the n-type semiconductor layer; an electrode layer extending over the p-type semiconductor layer; and a second bonding pad on the electrode layer, the bonding pad comprising a central region for securing an electrical interconnect, and at least one finger-like region protruding from the central region, the finger-like region having a length extending away from the central region and a width that is substantially less than the length.
2. The device of Claim 1, wherein the second bonding pad covers an area of the electrode layer that approximately corresponds to the geometric center of the top surface of the electrode layer.
3. The device of Claim 1, wherein the electrode layer comprises a plurality of edges and the second bonding pad is approximately equidistant from each of the edges.
4. The device of Claim 1 , wherein adjacent edges of the n-type semiconductor layer meet to form comers, and the first bonding pad is located adjacent to a corner.
5. The device of Claim 1 , wherein the length dimension of at least one fingerlike region extends generally parallel to an edge of the n-type semiconductor layer.
6. The device of Claim 1, wherein the second bonding pad includes two fingerlike regions extending away from the central region generally perpendicular to one another.
7. The device of Claim 1, wherein the first bonding pad includes a central region for securing an electrical interconnect and at least one finger-like region protruding from the central region, the finger-like region having a length extending away from the central region and a width that is substantially less than the length.
8. The device of Claim 7, wherein at least one finger-like region of the first bonding pad extends adjacent to an edge of the n-type semiconductor layer.
9. The device of Claim 8, wherein a finger-like region of the first bonding pad extends adjacent to more than one edge of the n-type semiconductor layer.
10. The device of Claim 8, wherein the first bonding pad comprises two fingerlike regions, including a first finger-like region extending adjacent to an edge of the n-type semiconductor layer on one side of the central region, and a second finger-like region extending adjacent to an edge of the n-type semiconductor layer on another side of the central region.
11. The device of Claim 8, wherein the at least one finger-like region extends
■• adjacent to no more than about 50 percent of the total outer perimeter of the n-type semiconductor layer.
12. The device of Claim 1, wherein at least one of the first and second bonding pads comprises a metallic material.
13. The device of Claim 12, wherein the metallic material comprises a layer of palladium, a layer of aluminum over the layer of palladium, and a layer of gold over the layer of aluminum.
14. The device of Claim 1, wherein the first bonding pad and the second bonding pad are comprised of a substantially identical material.
15. The device of Claim 1 , wherein at least one of the n-type semiconductor layer and the p-type semiconductor layer comprises a GaN-based semiconductor material.
16. The device of Claim 1, additionally comprising an active region between the n-type semiconductor layer and the p-type semiconductor layer, the active region extending over a major portion of the n-type semiconductor layer and not extending over an exposed region of the n-type semiconductor layer located adjacent to at least one edge of the planar top surface of the n-type semiconductor layer.
17. The device of Claim 1, wherein the active region comprises a single or multiple quantum well structure.
18. A method of producing a semiconductor device comprising: providing a substrate; providing an n-type gallium nitride-based semiconductor layer over the substrate, the n-type semiconductor layer having a planar top surface; providing a p-type gallium nitride-based semiconductor layer extending over a major portion of the n-type semiconductor layer and not extending over an exposed region of the n-type semiconductor layer located adjacent to at least one edge of the planar top surface of the n-type semiconductor layer; providing a first bonding pad provided on the exposed region of the n-type semiconductor layer; providing an electrode layer extending over the p-type semiconductor layer; and providing a second bonding pad on the second electrode, the second bonding pad comprising a central region for securing an electrical interconnect, and at least one finger-like region protruding from the central region, the finger-like region having a length extending away from the central region and a width that is substantially less than the length.
19. The method of Claim 18, wherein the second bonding pad covers an area of the electrode layer that approximately corresponds to the geometric center of the top surface of the electrode layer.
20. The method of Claim 18, wherein the p-type semiconductor layer and the electrode layer are formed substantially over the entire planar top surface of the n-type semiconductor layer, and a portion of the p-type semiconductor layer and the electrode layer are removed to define the exposed region of the n-type semiconductor layer.
21. The method of Claim 18, wherein the length dimension of at least one finger- like region extends generally parallel to an edge of the n-type semiconductor layer.
22. The method of Claim 18, wherein the second bonding pad includes two finger-like regions extending away from the central region generally perpendicular to one another.
23. The method of Claim 18, wherein the first bonding pad includes a central region for securing an electrical interconnect and at least one finger-like region protruding from the central region, the finger-like region having a length extending away from the central region and a width that is substantially less than the length.
24. The method of Claim 23, wherein at least one finger-like region of the first bonding pad extends adjacent to an edge of the n-type semiconductor layer.
25. The method of Claim 24, wherein a finger-like region of the first bonding pad extends adjacent to more than one edge of the n-type semiconductor layer.
26. The method of Claim 23, wherein the first bonding pad comprises two finger-like regions, including a first finger-like region extending adjacent to an edge of the n-type semiconductor layer on one side of the central region, and a second finger-like region extending adjacent to an edge of the n-type semiconductor layer on another side of the central region.
PCT/US2003/019036 2002-06-17 2003-06-17 Light-emitting diode device geometry WO2003107444A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003251541A AU2003251541A1 (en) 2002-06-17 2003-06-17 Light-emitting diode electrode geometry

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US38975002P 2002-06-17 2002-06-17
US60/389,750 2002-06-17
US39300802P 2002-06-28 2002-06-28
US10/187,466 US20040000672A1 (en) 2002-06-28 2002-06-28 High-power light-emitting diode structures
US60/393,008 2002-06-28
US10/187,468 2002-06-28
US10/187,465 2002-06-28
US10/187,465 US6734091B2 (en) 2002-06-28 2002-06-28 Electrode for p-type gallium nitride-based semiconductors
US10/187,468 US7002180B2 (en) 2002-06-28 2002-06-28 Bonding pad for gallium nitride-based light-emitting device
US10/187,466 2002-06-28

Publications (2)

Publication Number Publication Date
WO2003107444A2 true WO2003107444A2 (en) 2003-12-24
WO2003107444A3 WO2003107444A3 (en) 2004-09-02

Family

ID=32097143

Family Applications (3)

Application Number Title Priority Date Filing Date
PCT/US2003/019036 WO2003107444A2 (en) 2002-06-17 2003-06-17 Light-emitting diode device geometry
PCT/US2003/019034 WO2003107442A2 (en) 2002-06-17 2003-06-17 Electrode for p-type gallium nitride-based semiconductors
PCT/US2003/019035 WO2003107443A2 (en) 2002-06-17 2003-06-17 Bonding pad for gallium nitride-based light-emitting device

Family Applications After (2)

Application Number Title Priority Date Filing Date
PCT/US2003/019034 WO2003107442A2 (en) 2002-06-17 2003-06-17 Electrode for p-type gallium nitride-based semiconductors
PCT/US2003/019035 WO2003107443A2 (en) 2002-06-17 2003-06-17 Bonding pad for gallium nitride-based light-emitting device

Country Status (4)

Country Link
US (1) US6847052B2 (en)
AU (3) AU2003251541A1 (en)
TW (2) TW200400608A (en)
WO (3) WO2003107444A2 (en)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USD668234S1 (en) * 2001-05-24 2012-10-02 Lextar Electornics Corp. LED chip
GB2412234A (en) * 2004-03-18 2005-09-21 Sharp Kk Manufacture of a semiconductor light-emitting device
US7566908B2 (en) * 2004-11-29 2009-07-28 Yongsheng Zhao Gan-based and ZnO-based LED
KR100658304B1 (en) 2005-07-04 2006-12-14 엘지전자 주식회사 Quantum dot led with capping layer and process of forming the same
KR101041843B1 (en) * 2005-07-30 2011-06-17 삼성엘이디 주식회사 Nitride-based compound semiconductor light emitting device and fabrication method of the same
US8698184B2 (en) 2011-01-21 2014-04-15 Cree, Inc. Light emitting diodes with low junction temperature and solid state backlight components including light emitting diodes with low junction temperature
US7777240B2 (en) * 2006-10-17 2010-08-17 Epistar Corporation Optoelectronic device
US7843060B2 (en) * 2007-06-11 2010-11-30 Cree, Inc. Droop-free high output light emitting devices and methods of fabricating and operating same
JP4952534B2 (en) * 2007-11-20 2012-06-13 三菱電機株式会社 Manufacturing method of nitride semiconductor light emitting device
US7935979B2 (en) * 2008-05-01 2011-05-03 Bridgelux, Inc. Wire bonding to connect electrodes
US8630326B2 (en) 2009-10-13 2014-01-14 Skorpios Technologies, Inc. Method and system of heterogeneous substrate bonding for photonic integration
US9316785B2 (en) 2013-10-09 2016-04-19 Skorpios Technologies, Inc. Integration of an unprocessed, direct-bandgap chip into a silicon photonic device
US9882073B2 (en) 2013-10-09 2018-01-30 Skorpios Technologies, Inc. Structures for bonding a direct-bandgap chip to a silicon photonic device
US11181688B2 (en) 2009-10-13 2021-11-23 Skorpios Technologies, Inc. Integration of an unprocessed, direct-bandgap chip into a silicon photonic device
USD644187S1 (en) * 2010-02-10 2011-08-30 Epistar Corporation Light emitting diode array
JP2012028749A (en) 2010-07-22 2012-02-09 Seoul Opto Devices Co Ltd Light-emitting diode
US9922967B2 (en) 2010-12-08 2018-03-20 Skorpios Technologies, Inc. Multilevel template assisted wafer bonding
US9977188B2 (en) 2011-08-30 2018-05-22 Skorpios Technologies, Inc. Integrated photonics mode expander
US9097846B2 (en) 2011-08-30 2015-08-04 Skorpios Technologies, Inc. Integrated waveguide coupler
US8835965B2 (en) 2012-01-18 2014-09-16 The Penn State Research Foundation Application of semiconductor quantum dot phosphors in nanopillar light emitting diodes
US9281451B2 (en) * 2012-02-17 2016-03-08 Industrial Technology Research Institute Light emitting element and fabricating method thereof
WO2014176561A1 (en) 2013-04-25 2014-10-30 Skorpios Technologies, Inc. Method and system for height registration during chip bonding
US9419156B2 (en) * 2013-08-30 2016-08-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package and method for integration of heterogeneous integrated circuits
US9664855B2 (en) 2014-03-07 2017-05-30 Skorpios Technologies, Inc. Wide shoulder, high order mode filter for thick-silicon waveguides
US10003173B2 (en) 2014-04-23 2018-06-19 Skorpios Technologies, Inc. Widely tunable laser control
US9658401B2 (en) * 2014-05-27 2017-05-23 Skorpios Technologies, Inc. Waveguide mode expander having an amorphous-silicon shoulder
US10319693B2 (en) 2014-06-16 2019-06-11 Skorpios Technologies, Inc. Micro-pillar assisted semiconductor bonding
US9829631B2 (en) 2015-04-20 2017-11-28 Skorpios Technologies, Inc. Vertical output couplers for photonic devices
US10649148B2 (en) 2017-10-25 2020-05-12 Skorpios Technologies, Inc. Multistage spot size converter in silicon photonics
US11360263B2 (en) 2019-01-31 2022-06-14 Skorpios Technologies. Inc. Self-aligned spot size converter

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001073858A1 (en) * 2000-03-31 2001-10-04 Toyoda Gosei Co., Ltd. Group-iii nitride compound semiconductor device
US6344665B1 (en) * 2000-06-23 2002-02-05 Arima Optoelectronics Corp. Electrode structure of compound semiconductor device
US20020047128A1 (en) * 2000-09-04 2002-04-25 Samsung Electro-Mechanics Co., Ltd. Blue light emitting diode with electrode structure for distributing a current density
US6403987B1 (en) * 1997-05-08 2002-06-11 Showa Denko K.K. Electrode for light-emitting semiconductor devices

Family Cites Families (89)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2421590A1 (en) 1974-05-03 1975-11-13 Siemens Ag Optical semiconductor radiation source - has hilly geometric shaped outer surface with PN junction in or near hill
JPS609355B2 (en) 1975-08-30 1985-03-09 富士通株式会社 Manufacturing method of semiconductor light emitting device
SU773795A1 (en) 1977-04-01 1980-10-23 Предприятие П/Я А-1172 Light-emitting device
JPS5493380A (en) 1977-12-30 1979-07-24 Fujitsu Ltd Semiconductor light emitting device
US4495514A (en) 1981-03-02 1985-01-22 Eastman Kodak Company Transparent electrode light emitting diode and method of manufacture
US4670088A (en) 1982-03-18 1987-06-02 Massachusetts Institute Of Technology Lateral epitaxial growth by seeded solidification
JPS59228776A (en) 1983-06-10 1984-12-22 Nippon Telegr & Teleph Corp <Ntt> Semiconductor hetero-junction element
US5091333A (en) 1983-09-12 1992-02-25 Massachusetts Institute Of Technology Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth
DE3345172A1 (en) 1983-12-14 1985-07-25 Itt Ind Gmbh Deutsche Method of activating latent defects in memories with memory/insulating layer field-effect transistors which have a floating-potential memory gate
JPS6156474A (en) 1984-08-28 1986-03-22 Matsushita Electric Ind Co Ltd Manufacture of gallium nitride semiconductor device
US4625182A (en) 1985-10-28 1986-11-25 The United States Of America As Represented By The Secretary Of The Army Optically triggered bulk device Gunn oscillator
US4946548A (en) 1988-04-29 1990-08-07 Toyoda Gosei Co., Ltd. Dry etching method for semiconductor
EP0356059B1 (en) 1988-08-15 2000-01-26 Gertrude F. Neumark Process for doping crystals of wide band gap semiconductors
US5252499A (en) 1988-08-15 1993-10-12 Rothschild G F Neumark Wide band-gap semiconductors having low bipolar resistivity and method of formation
JPH06101587B2 (en) 1989-03-01 1994-12-12 日本電信電話株式会社 Semiconductor light emitting element
US4966862A (en) 1989-08-28 1990-10-30 Cree Research, Inc. Method of production of light emitting diodes
JPH03203388A (en) 1989-12-29 1991-09-05 Matsushita Electric Ind Co Ltd Semiconductor light emitting element and its manufacture
JP2500319B2 (en) 1990-01-11 1996-05-29 名古屋大学長 Method for producing p-type gallium nitride compound semiconductor crystal
DE69126152T2 (en) 1990-02-28 1997-11-13 Toyoda Gosei Kk Gallium nitride compound semiconductor light emitting device
US6830992B1 (en) 1990-02-28 2004-12-14 Toyoda Gosei Co., Ltd. Method for manufacturing a gallium nitride group compound semiconductor
US5278433A (en) 1990-02-28 1994-01-11 Toyoda Gosei Co., Ltd. Light-emitting semiconductor device using gallium nitride group compound with double layer structures for the n-layer and/or the i-layer
US6362017B1 (en) 1990-02-28 2002-03-26 Toyoda Gosei Co., Ltd. Light-emitting semiconductor device using gallium nitride group compound
US5210051A (en) 1990-03-27 1993-05-11 Cree Research, Inc. High efficiency light emitting diodes from bipolar gallium nitride
US5433169A (en) 1990-10-25 1995-07-18 Nichia Chemical Industries, Ltd. Method of depositing a gallium nitride-based III-V group compound semiconductor crystal layer
US5334277A (en) 1990-10-25 1994-08-02 Nichia Kagaky Kogyo K.K. Method of vapor-growing semiconductor crystal and apparatus for vapor-growing the same
US5281830A (en) 1990-10-27 1994-01-25 Toyoda Gosei Co., Ltd. Light-emitting semiconductor device using gallium nitride group compound
JP3160914B2 (en) 1990-12-26 2001-04-25 豊田合成株式会社 Gallium nitride based compound semiconductor laser diode
US5290393A (en) 1991-01-31 1994-03-01 Nichia Kagaku Kogyo K.K. Crystal growth method for gallium nitride-based compound semiconductor
JP2786952B2 (en) 1991-02-27 1998-08-13 株式会社豊田中央研究所 Gallium nitride based compound semiconductor light emitting device and method of manufacturing the same
JP3098773B2 (en) 1991-03-18 2000-10-16 トラスティーズ・オブ・ボストン・ユニバーシティ Preparation and doping method of highly insulating single crystal gallium nitride thin film
US5442205A (en) 1991-04-24 1995-08-15 At&T Corp. Semiconductor heterostructure devices with strained semiconductor layers
US6001669A (en) 1991-09-09 1999-12-14 Philips Electronics North America Corporation Method for producing II-VI compound semiconductor epitaxial layers having low defects
JP2666228B2 (en) 1991-10-30 1997-10-22 豊田合成株式会社 Gallium nitride based compound semiconductor light emitting device
US5306662A (en) 1991-11-08 1994-04-26 Nichia Chemical Industries, Ltd. Method of manufacturing P-type compound semiconductor
JP3352712B2 (en) 1991-12-18 2002-12-03 浩 天野 Gallium nitride based semiconductor device and method of manufacturing the same
US5285078A (en) 1992-01-24 1994-02-08 Nippon Steel Corporation Light emitting element with employment of porous silicon and optical device utilizing light emitting element
US5406123A (en) 1992-06-11 1995-04-11 Engineering Research Ctr., North Carolina State Univ. Single crystal titanium nitride epitaxial on silicon
EP1313153A3 (en) 1992-07-23 2005-05-04 Toyoda Gosei Co., Ltd. Light-emitting device of gallium nitride compound semiconductor
US5323022A (en) 1992-09-10 1994-06-21 North Carolina State University Platinum ohmic contact to p-type silicon carbide
JP2657743B2 (en) 1992-10-29 1997-09-24 豊田合成株式会社 Nitrogen-3 group element compound semiconductor light emitting device
US5578839A (en) 1992-11-20 1996-11-26 Nichia Chemical Industries, Ltd. Light-emitting gallium nitride-based compound semiconductor device
KR100286699B1 (en) * 1993-01-28 2001-04-16 오가와 에이지 Gallium Nitride Group 3-5 Compound Semiconductor Light-Emitting Device and Manufacturing Method Thereof
US5383088A (en) 1993-08-09 1995-01-17 International Business Machines Corporation Storage capacitor with a conducting oxide electrode for metal-oxide dielectrics
US5656832A (en) * 1994-03-09 1997-08-12 Kabushiki Kaisha Toshiba Semiconductor heterojunction device with ALN buffer layer of 3nm-10nm average film thickness
US5516731A (en) 1994-06-02 1996-05-14 Lsi Logic Corporation High-temperature bias anneal of integrated circuits for improved radiation hardness and hot electron resistance
US5751752A (en) 1994-09-14 1998-05-12 Rohm Co., Ltd. Semiconductor light emitting device and manufacturing method therefor
US6900465B2 (en) 1994-12-02 2005-05-31 Nichia Corporation Nitride semiconductor light-emitting device
US5777350A (en) 1994-12-02 1998-07-07 Nichia Chemical Industries, Ltd. Nitride semiconductor light-emitting device
US5850410A (en) 1995-03-16 1998-12-15 Fujitsu Limited Semiconductor laser and method for fabricating the same
US5900650A (en) * 1995-08-31 1999-05-04 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
KR100267839B1 (en) 1995-11-06 2000-10-16 오가와 에이지 Nitride semiconductor device
US5760423A (en) * 1996-11-08 1998-06-02 Kabushiki Kaisha Toshiba Semiconductor light emitting device, electrode of the same device and method of manufacturing the same device
JP3461074B2 (en) 1995-12-12 2003-10-27 パイオニア株式会社 Method of manufacturing group III nitride semiconductor light emitting device
US6017774A (en) 1995-12-24 2000-01-25 Sharp Kabushiki Kaisha Method for producing group III-V compound semiconductor and fabricating light emitting device using such semiconductor
US5828684A (en) 1995-12-29 1998-10-27 Xerox Corporation Dual polarization quantum well laser in the 200 to 600 nanometers range
DE19638667C2 (en) 1996-09-20 2001-05-17 Osram Opto Semiconductors Gmbh Mixed-color light-emitting semiconductor component with luminescence conversion element
US5987048A (en) * 1996-07-26 1999-11-16 Kabushiki Kaisha Toshiba Gallium nitride-based compound semiconductor laser and method of manufacturing the same
TW383508B (en) 1996-07-29 2000-03-01 Nichia Kagaku Kogyo Kk Light emitting device and display
US5834331A (en) * 1996-10-17 1998-11-10 Northwestern University Method for making III-Nitride laser and detection device
CN100485984C (en) 1997-01-09 2009-05-06 日亚化学工业株式会社 Nitride semiconductor device
WO1998047170A1 (en) 1997-04-11 1998-10-22 Nichia Chemical Industries, Ltd. Method of growing nitride semiconductors, nitride semiconductor substrate and nitride semiconductor device
JP3693468B2 (en) 1997-07-23 2005-09-07 シャープ株式会社 Semiconductor light emitting device
JPH11138773A (en) 1997-11-10 1999-05-25 Fuji Xerox Co Ltd Method and device for image forming
US6051849A (en) 1998-02-27 2000-04-18 North Carolina State University Gallium nitride semiconductor structures including a lateral gallium nitride layer that extends from an underlying gallium nitride layer
TW386286B (en) * 1998-10-26 2000-04-01 Ind Tech Res Inst An ohmic contact of semiconductor and the manufacturing method
US6153894A (en) * 1998-11-12 2000-11-28 Showa Denko Kabushiki Kaisha Group-III nitride semiconductor light-emitting device
AU1626400A (en) 1998-11-16 2000-06-05 Emcore Corporation Iii-nitride quantum well structures with indium-rich clusters and methods of making the same
US6067222A (en) 1998-11-25 2000-05-23 Applied Materials, Inc. Substrate support apparatus and method for fabricating same
JP3469484B2 (en) 1998-12-24 2003-11-25 株式会社東芝 Semiconductor light emitting device and method of manufacturing the same
DE19911717A1 (en) 1999-03-16 2000-09-28 Osram Opto Semiconductors Gmbh Monolithic electroluminescent device, especially an LED chip, has a row of emission zones individually associated with decoupling elements for decoupling radiation from the device
JP3656456B2 (en) 1999-04-21 2005-06-08 日亜化学工業株式会社 Nitride semiconductor device
US6287947B1 (en) * 1999-06-08 2001-09-11 Lumileds Lighting, U.S. Llc Method of forming transparent contacts to a p-type GaN layer
JP3705016B2 (en) * 1999-06-28 2005-10-12 豊田合成株式会社 Translucent electrode film and group III nitride compound semiconductor device
US6992334B1 (en) * 1999-12-22 2006-01-31 Lumileds Lighting U.S., Llc Multi-layer highly reflective ohmic contacts for semiconductor devices
US6475854B2 (en) 1999-12-30 2002-11-05 Applied Materials, Inc. Method of forming metal electrodes
GB0006957D0 (en) 2000-03-23 2000-05-10 Koninkl Philips Electronics Nv A semiconductor device
JP3795298B2 (en) 2000-03-31 2006-07-12 豊田合成株式会社 Method for manufacturing group III nitride compound semiconductor light emitting device
JP4643794B2 (en) 2000-04-21 2011-03-02 富士通株式会社 Semiconductor light emitting device
JP2002026456A (en) 2000-06-30 2002-01-25 Toshiba Corp Semiconductor device, semiconductor laser, method of manufacturing thereof, and method of etching
JP4024994B2 (en) * 2000-06-30 2007-12-19 株式会社東芝 Semiconductor light emitting device
US6420736B1 (en) * 2000-07-26 2002-07-16 Axt, Inc. Window for gallium nitride light emitting diode
US6255129B1 (en) 2000-09-07 2001-07-03 Highlink Technology Corporation Light-emitting diode device and method of manufacturing the same
DE10060439A1 (en) * 2000-12-05 2002-06-13 Osram Opto Semiconductors Gmbh Contact metallization used in production of semiconductors contains copper distributed in partial volume
US6881983B2 (en) 2002-02-25 2005-04-19 Kopin Corporation Efficient light emitting diodes and lasers
US6911079B2 (en) 2002-04-19 2005-06-28 Kopin Corporation Method for reducing the resistivity of p-type II-VI and III-V semiconductors
US20030222263A1 (en) 2002-06-04 2003-12-04 Kopin Corporation High-efficiency light-emitting diodes
US6734091B2 (en) 2002-06-28 2004-05-11 Kopin Corporation Electrode for p-type gallium nitride-based semiconductors
US7002180B2 (en) 2002-06-28 2006-02-21 Kopin Corporation Bonding pad for gallium nitride-based light-emitting device
US20040000672A1 (en) 2002-06-28 2004-01-01 Kopin Corporation High-power light-emitting diode structures

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6403987B1 (en) * 1997-05-08 2002-06-11 Showa Denko K.K. Electrode for light-emitting semiconductor devices
WO2001073858A1 (en) * 2000-03-31 2001-10-04 Toyoda Gosei Co., Ltd. Group-iii nitride compound semiconductor device
US6344665B1 (en) * 2000-06-23 2002-02-05 Arima Optoelectronics Corp. Electrode structure of compound semiconductor device
US20020047128A1 (en) * 2000-09-04 2002-04-25 Samsung Electro-Mechanics Co., Ltd. Blue light emitting diode with electrode structure for distributing a current density

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
KIM H ET AL: "DESIGN AND FABRICATION OF HIGHLY EFFICIENT GAN-BASED LIGHT-EMITTING DIODES" IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE INC. NEW YORK, US, vol. 49, no. 10, October 2002 (2002-10), pages 1715-1722, XP001127576 ISSN: 0018-9383 *

Also Published As

Publication number Publication date
TW200400608A (en) 2004-01-01
WO2003107444A3 (en) 2004-09-02
AU2003251540A1 (en) 2003-12-31
WO2003107442A2 (en) 2003-12-24
WO2003107443A3 (en) 2004-09-02
AU2003251541A1 (en) 2003-12-31
AU2003251541A8 (en) 2003-12-31
US20040077135A1 (en) 2004-04-22
TW200401462A (en) 2004-01-16
AU2003251539A1 (en) 2003-12-31
WO2003107442A3 (en) 2004-09-02
WO2003107443A2 (en) 2003-12-24
US6847052B2 (en) 2005-01-25

Similar Documents

Publication Publication Date Title
US6847052B2 (en) Light-emitting diode device geometry
US5753939A (en) Light-emitting semiconductor device using a Group III nitride compound and having a contact layer upon which an electrode is formed
EP1810351B1 (en) Gan compound semiconductor light emitting element
TWI392106B (en) Iii-nitride light emitting device with reduced polarization fields
US7345315B2 (en) Gallium nitride based light-emitting device
US7705348B2 (en) Semiconductor light-emitting device with electrode for N-polar InGaAIN surface
US6777805B2 (en) Group-III nitride compound semiconductor device
US6992331B2 (en) Gallium nitride based compound semiconductor light-emitting device
US7193249B2 (en) Nitride-based light emitting device and method of manufacturing the same
WO2012091311A2 (en) High efficiency light emitting diode
JP2005217421A (en) Group iii nitride light-emitting device of improved high current efficiency
WO2007086345A1 (en) Semiconductor light-emitting device and method for manufacturing same
KR20060059783A (en) Gan compound semiconductor light emitting element and method of manufacturing the same
US11430934B2 (en) Light-emitting diode device
US20130099248A1 (en) Nitride semiconductor light emitting device
US7196348B2 (en) GaN system semiconductor light emitting device excellent in light emission efficiency and light extracting efficiency
US6734091B2 (en) Electrode for p-type gallium nitride-based semiconductors
EP1530242B1 (en) Semiconductor light emitting device
US7002180B2 (en) Bonding pad for gallium nitride-based light-emitting device
CN111403565A (en) Light emitting diode and manufacturing method thereof
KR101219290B1 (en) Method for fabricating light emitting diodes
KR100755649B1 (en) Gan-based semiconductor light emitting device and method of manufacturing the same
US6642548B1 (en) Light-emitting diodes with loop and strip electrodes and with wide medial sections
US20040000672A1 (en) High-power light-emitting diode structures
WO2005060013A1 (en) Semiconductor light-emitting device and method for manufacturing same

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP