WO2004010468A2 - Low temperature ozone anneal of gate and capacitor dielectrics - Google Patents

Low temperature ozone anneal of gate and capacitor dielectrics Download PDF

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WO2004010468A2
WO2004010468A2 PCT/US2003/022235 US0322235W WO2004010468A2 WO 2004010468 A2 WO2004010468 A2 WO 2004010468A2 US 0322235 W US0322235 W US 0322235W WO 2004010468 A2 WO2004010468 A2 WO 2004010468A2
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ozone
annealing
gas
temperature
dielectric
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PCT/US2003/022235
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French (fr)
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WO2004010468A3 (en
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Yoshihide Senzaki
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Aviza Technology, Inc.
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Publication of WO2004010468A3 publication Critical patent/WO2004010468A3/en

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    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
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    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02142—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
    • H01L21/02148—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides the material containing hafnium, e.g. HfSiOx or HfSiON
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    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02142—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
    • H01L21/02159—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides the material containing zirconium, e.g. ZrSiOx
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02107—Forming insulating materials on a substrate
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    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02189—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing zirconium, e.g. ZrO2

Definitions

  • the present invention relates generally to the field of semiconductors. More specifically, the present invention relates to the thermal anneal process used in gate fabrication of semiconductor devices.
  • High-k dielectrics to conventional silicon dioxide dielectrics (SiO 2 ) are actively sought.
  • These types of metal oxides can be deposited on the surface of a silicon substrate by traditional techniques such as chemical vapor deposition (CVD) or newer
  • ⁇ techniques such as atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • N 2 nitrogen
  • O 2 oxygen
  • Conventional post deposition annealing thermal anneal process induces additional oxide growth at the interface between the metal oxide layer and the underlying silicon substrate.
  • the conventional thermal anneal step induces interfacial oxide growth and therefore increases the equivalent oxide thickness (EOT), and as a result, loses the merit of post deposition anneal.
  • EOT equivalent oxide thickness
  • Oxygen from the metal oxide layer diffuses into the underlying silicon substrate and reacts with the silicon to form a SiO x suboxide layer at the interface between the gate or capacitor dielectric and the substrate thereby degrading the device performance.
  • one object of the present invention is to provide a method in which post deposition anneal of high-k dielectric oxide layers is carried out at a low temperature, thereby suppressing interfacial oxide growth.
  • the anneal can be done at a lower temperature than conventional anneal processes, thereby suppressing interfacial oxide growth.
  • the lower temperature anneal method of the present invention retains the benefits of conventional annealing of fixing electron trapping sites in metal oxides and improving the electrical properties while minimizing the undesired interfacial oxide growth.
  • a method of annealing one or more gate and/or capacitor dielectric layers on a semiconductor substrate characterized in that the one or more gate and/or capacitor dielectric layer(s) is exposed to an ozone-containing atmosphere for a period of time in the range of about 0.1 second to 5 minutes, and at a temperature in the range of 20°C to 500°C.
  • a method of annealing a dielectric layer on a semiconductor substrate wherein the substrate is placed in a chamber, the chamber is heated to an annealing temperature, the dielectric layer is exposed to a ozone- containing gas at a flow rate in the range of about 20 seem to 10,000 seem, where the temperature and flow rate are maintained for a annealing time.
  • FIGS. 1A and IB illustrate two different apparatus suitable for the performing the method of the present invention.
  • FIG. 2 provides a flow chart illustrating the steps of the method according to one embodiment of the present invention.
  • FIG. 3 illustrates devices that may be annealed using the invention.
  • the present invention provides a method of thermal annealing of a semiconductor device. More specifically, the present invention provides a method of annealing a metal oxide dielectric layer having a high dielectric constant (high-k).
  • the method of the present invention uses ozone, or an ozone containing mixture, as the annealing gas.
  • Ozone is a stronger oxidizer than molecular oxygen and allows for annealing of the high-k material at a lower temperature than required in conventional annealing processes that employ nitrogen or oxygen.
  • annealing of high-k metal oxide dielectrics can be performed at a temperature as low as 100°C, and even at or near room temperature with the addition of UV light.
  • Thermal annealing systems are well known in the industry, and are typically classified as hot wall chambers (see FIG. 1A) or cold wall chambers (see FIG. IB).
  • Systems may be batch systems which support a plurality of wafers for processing in one batch, or a single wafer system which processes one wafer at a time. As such systems are well known, they are not described in detail herein and are shown in a simplified manner in FIGS. 1A and IB.
  • a hot wall chamber type system 101 is partially shown in a cross sectional view.
  • a plurality of wafers 100 are stacked vertically in the chamber.
  • Heater elements (not shown) are provided to heat the environment of the wafer 100. Gases are conveyed to and from the chamber 101 via inlet 104 and outlet 105, respectively.
  • a cold wall chamber type system 102 is partially shown in a cross sectional view.
  • a single wafer 100 is processes in the chamber.
  • the wafer is supported and heated by a heated support or chuck 103.
  • a cold wall chamber is preferred as it tends to preserve the stability of the ozone.
  • the chamber 101 or 102 is heated, preferably in an inert environment, to the annealing temperature.
  • Inert diluent gases such as nitrogen, helium, neon, argon, xenon or a mixture of any of the above can be used; nitrogen and argon are preferred inert diluent gases for cost reasons.
  • an ozone containing annealing gas is introduced into the chamber through inlet 104.
  • the wafers are exposed to the ozone containing gas at the annealing temperature for a desired time, the annealing time.
  • the annealing gas is removed from the annealing chamber by pumping the gas out of the chamber through outlet 105.
  • the wafer(s) 100 is allowed to cool to room temperature, or preferably, rapidly cooled to room temperature by conventional cooling techniques in an inert atmosphere.
  • the post deposition annealing method of the present invention is performed at an annealing temperature in the range of about 20°C to 500°C in an ozone-containing atmosphere for a time period ranging from 0.1 seconds to 5 minutes (the annealing time), as required by the device specifications and/or performance.
  • the annealing temperature can be higher than 500°C, however it is not preferred as the best results are achieved at or lower than 500°C.
  • the annealing temperature can be less than 100°C with the assistance of UV light.
  • the annealing time is from 5 seconds to 1 minute, with optimal results obtained with an annealing time of 10 to 30 seconds.
  • the ozone-containing atmosphere may be maintained during annealing at a pressure in the range of 10 Torr to 760 Torr.
  • the total gas flow rate into the chamber can be from 10 seem to 10,000 seem, with 100 seem to 10,000 seem being the preferred range.
  • the preferred ozone mass fraction of the total gas flow can be from 0.1% to 20% with the balance being O 2 .
  • the anneal of the present invention is preferably performed at a temperature within the range from about 150°C to 450°C, and most preferably at a temperature within the range of 200 to 400°C. At this lower temperature with exposure to ozone, the benefits of the anneal are realized, while the growth of the interfacial oxide is minimized.
  • the method is carried out at a temperature less than about 100°C, and during exposure of the substrate to the oxidizing gas UV is radiated on the substrate.
  • the anneal gas contains ozone, and is preferably pure, or close to pure, ozone.
  • the anneal gas contains a mixture of gases that includes ozone gas.
  • the mixture in addition to ozone, can include oxygen and/or nitrogen. Other gases may also be included.
  • the exact proportion of the components of the mixture is not critically important. As a general rule, however, a higher concentration of ozone gas in the mixture allows for annealing at a lower temperature, which in turn minimizes the undesired interfacial oxide growth.
  • rapid cooling after the heat exposure step is preferred. As with conventional annealing, however, rapid cooling is not a required step.
  • the device may alternatively be allowed to cool to ambient temperature simply by being removed from the heat source in an inert atmosphere.
  • the present invention is ideally suited for the annealing of gate and capacitor dielectrics and more specifically after the deposition of a high-k metal oxide dielectric containing a metal such as Ta, Ti, Hf or Zr, or a high-k metal silicate dielectric such as Hf-Si-O or Zr-Si-O 300.
  • a metal such as Ta, Ti, Hf or Zr
  • a high-k metal silicate dielectric such as Hf-Si-O or Zr-Si-O 300.
  • the metal in the oxide or silicate could also be chosen from the list comprising Hf, Ti, Zr, Y, La, V, Nb, Ta, W, Zn, Al, Sn, Ce, Pr, Sm, Eu, Tb, Dy, Ho, Er, Tm, Yb, or Lu.
  • the invention is also suited for annealing of dielectrics stacked with silicon oxide/silicon nitride layers 301. Annealing of other devices is also envisioned within the scope of the present invention where a lower temperature is desired.

Abstract

A method of thermal annealing of semiconductor devices is provided. In one aspect the present invention, gate and/or capacitor dielectric layer(s) on a semiconductor substrate are annealed characterized in that the dielectric layer(s) is exposed to an ozone-containing atmosphere for a period of time in the range of about 0.1 second to 5 minutes and at a temperature in the range of about 20°C to 500°C.

Description

LOW TEMPERATURE OZONE ANNEAL OF GATE AND CAPACITOR
DIELECTRICS
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is related to, and claims priority to, United States Provisional Patent Application No. 60/396,742 entitled Low Temperature Ozone Anneal of Gate and Capacitor Dielectrics, filed July 19, 2002, the entire disclosure of which is hereby incorporated by reference.
FIELD OF THE INVENTION
The present invention relates generally to the field of semiconductors. More specifically, the present invention relates to the thermal anneal process used in gate fabrication of semiconductor devices.
BACKGROUND OF THE INVENTION
As the future device scale aggressively reduces, alternative high-k dielectrics to conventional silicon dioxide dielectrics (SiO2) are actively sought. High dielectric constant ("high-k") metal oxides such as halfhium oxide HfO2 (having a k=20-25), zirconium oxide ZrO2
Figure imgf000002_0001
and halfhium Hf and zirconium Zr silicates are considered alternative materials to silicon oxide (k=3.9) to provide gate dielectrics with high capacitance. These types of metal oxides can be deposited on the surface of a silicon substrate by traditional techniques such as chemical vapor deposition (CVD) or newer
■ techniques such as atomic layer deposition (ALD). It is commonly observed that a post deposition thermal anneal of high-k oxides in a nitrogen (N2) or oxygen (O2) atmosphere improves the electrical properties of the dielectric. Conventional post deposition annealing thermal anneal process induces additional oxide growth at the interface between the metal oxide layer and the underlying silicon substrate. For ultxa-thin dielectric layers, the conventional thermal anneal step induces interfacial oxide growth and therefore increases the equivalent oxide thickness (EOT), and as a result, loses the merit of post deposition anneal. Oxygen from the metal oxide layer diffuses into the underlying silicon substrate and reacts with the silicon to form a SiOx suboxide layer at the interface between the gate or capacitor dielectric and the substrate thereby degrading the device performance.
Numerous papers have reported on the interfacial oxide growth problem for gate and capacitor dielectric applications. This problem is one of the major hurdles for implementing high-k materials in advanced device fabrication. A method for a lower temperature post deposition anneal would be advantageous since it would provide the benefits of improved electrical properties without the drawbacks of interfacial oxide growth.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method in which post deposition anneal of high-k dielectric oxide layers is carried out at a low temperature, thereby suppressing interfacial oxide growth. By performing the post deposition anneal with ozone, or an ozone containing mixture, as the annealing gas, the anneal can be done at a lower temperature than conventional anneal processes, thereby suppressing interfacial oxide growth. The lower temperature anneal method of the present invention retains the benefits of conventional annealing of fixing electron trapping sites in metal oxides and improving the electrical properties while minimizing the undesired interfacial oxide growth. In one aspect of the present invention, a method of annealing one or more gate and/or capacitor dielectric layers on a semiconductor substrate is provided, characterized in that the one or more gate and/or capacitor dielectric layer(s) is exposed to an ozone-containing atmosphere for a period of time in the range of about 0.1 second to 5 minutes, and at a temperature in the range of 20°C to 500°C. In another aspect of the present invention a method of annealing a dielectric layer on a semiconductor substrate is provided wherein the substrate is placed in a chamber, the chamber is heated to an annealing temperature, the dielectric layer is exposed to a ozone- containing gas at a flow rate in the range of about 20 seem to 10,000 seem, where the temperature and flow rate are maintained for a annealing time.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention is described in detail below and with reference to the following figures, in which:
FIGS. 1A and IB illustrate two different apparatus suitable for the performing the method of the present invention.
FIG. 2 provides a flow chart illustrating the steps of the method according to one embodiment of the present invention. FIG. 3 illustrates devices that may be annealed using the invention.
DETAILED DESCRIPTION OF THE INVENTION
The present invention provides a method of thermal annealing of a semiconductor device. More specifically, the present invention provides a method of annealing a metal oxide dielectric layer having a high dielectric constant (high-k). Of particular advantage, the method of the present invention uses ozone, or an ozone containing mixture, as the annealing gas. Ozone is a stronger oxidizer than molecular oxygen and allows for annealing of the high-k material at a lower temperature than required in conventional annealing processes that employ nitrogen or oxygen. According to the method of the present invention, annealing of high-k metal oxide dielectrics can be performed at a temperature as low as 100°C, and even at or near room temperature with the addition of UV light.
Devices to be annealed are fabricated on a Si wafer through well known semiconductor device manufacturing techniques. After deposition of the gate or capacitor dielectric, the wafer 100 is placed into a thermal annealing chamber. Thermal annealing systems are well known in the industry, and are typically classified as hot wall chambers (see FIG. 1A) or cold wall chambers (see FIG. IB). Systems may be batch systems which support a plurality of wafers for processing in one batch, or a single wafer system which processes one wafer at a time. As such systems are well known, they are not described in detail herein and are shown in a simplified manner in FIGS. 1A and IB.
Referring to FIG. 1A, a hot wall chamber type system 101 is partially shown in a cross sectional view. In this embodiment, a plurality of wafers 100 are stacked vertically in the chamber. Heater elements (not shown) are provided to heat the environment of the wafer 100. Gases are conveyed to and from the chamber 101 via inlet 104 and outlet 105, respectively.
Referring to FIG. IB, a cold wall chamber type system 102 is partially shown in a cross sectional view. In this embodiment, a single wafer 100 is processes in the chamber. The wafer is supported and heated by a heated support or chuck 103. A cold wall chamber is preferred as it tends to preserve the stability of the ozone. The chamber 101 or 102 is heated, preferably in an inert environment, to the annealing temperature. Inert diluent gases such as nitrogen, helium, neon, argon, xenon or a mixture of any of the above can be used; nitrogen and argon are preferred inert diluent gases for cost reasons. Upon reaching the annealing temperature, an ozone containing annealing gas is introduced into the chamber through inlet 104. The wafers are exposed to the ozone containing gas at the annealing temperature for a desired time, the annealing time. When the annealing is complete, the annealing gas is removed from the annealing chamber by pumping the gas out of the chamber through outlet 105. The wafer(s) 100 is allowed to cool to room temperature, or preferably, rapidly cooled to room temperature by conventional cooling techniques in an inert atmosphere.
The post deposition annealing method of the present invention is performed at an annealing temperature in the range of about 20°C to 500°C in an ozone-containing atmosphere for a time period ranging from 0.1 seconds to 5 minutes (the annealing time), as required by the device specifications and/or performance. The annealing temperature can be higher than 500°C, however it is not preferred as the best results are achieved at or lower than 500°C. The annealing temperature can be less than 100°C with the assistance of UV light. Preferably the annealing time is from 5 seconds to 1 minute, with optimal results obtained with an annealing time of 10 to 30 seconds. The ozone-containing atmosphere may be maintained during annealing at a pressure in the range of 10 Torr to 760 Torr. The total gas flow rate into the chamber can be from 10 seem to 10,000 seem, with 100 seem to 10,000 seem being the preferred range. The preferred ozone mass fraction of the total gas flow can be from 0.1% to 20% with the balance being O2. As discussed above, exposure of devices incorporating high k materials on Si to the high temperature (700 to 1200 °C) of conventional anneals results in the undesired growth of an interfacial oxide. Therefore, the anneal of the present invention is preferably performed at a temperature within the range from about 150°C to 450°C, and most preferably at a temperature within the range of 200 to 400°C. At this lower temperature with exposure to ozone, the benefits of the anneal are realized, while the growth of the interfacial oxide is minimized.
In an alternative embodiment of the present invention the method is carried out at a temperature less than about 100°C, and during exposure of the substrate to the oxidizing gas UV is radiated on the substrate.
It is preferable to introduce the anneal gas into the annealing chamber after the chamber reaches the appropriate annealing temperature. The anneal gas contains ozone, and is preferably pure, or close to pure, ozone. In an alternate embodiment, the anneal gas contains a mixture of gases that includes ozone gas. The mixture, in addition to ozone, can include oxygen and/or nitrogen. Other gases may also be included. The exact proportion of the components of the mixture is not critically important. As a general rule, however, a higher concentration of ozone gas in the mixture allows for annealing at a lower temperature, which in turn minimizes the undesired interfacial oxide growth.
In performing the anneal method of the present invention, rapid cooling after the heat exposure step is preferred. As with conventional annealing, however, rapid cooling is not a required step. The device may alternatively be allowed to cool to ambient temperature simply by being removed from the heat source in an inert atmosphere.
As displayed in FIG. 3, the present invention is ideally suited for the annealing of gate and capacitor dielectrics and more specifically after the deposition of a high-k metal oxide dielectric containing a metal such as Ta, Ti, Hf or Zr, or a high-k metal silicate dielectric such as Hf-Si-O or Zr-Si-O 300. These materials are listed as examples only. The metal in the oxide or silicate could also be chosen from the list comprising Hf, Ti, Zr, Y, La, V, Nb, Ta, W, Zn, Al, Sn, Ce, Pr, Sm, Eu, Tb, Dy, Ho, Er, Tm, Yb, or Lu. The invention is also suited for annealing of dielectrics stacked with silicon oxide/silicon nitride layers 301. Annealing of other devices is also envisioned within the scope of the present invention where a lower temperature is desired. Having thus described the invention with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.

Claims

What is claimed is:
1. A method for annealing gate and capacitor dielectrics comprising: exposing the dielectric to an ozone-containing atmosphere for a period of time from about 0.1 second to 5 minutes, wherein the ozone-containing atmosphere is at a temperature in the range of 20°C to 500°C; cooling said dielectric to ambient temperature.
2. The method of claim 1. where the ozone-containing atmosphere is at a pressure of from 1 Torr to 760 Torr.
3. The method of claim 1 where the ozone-containing atmosphere contains from 0.01% ozone to 20% ozone, with the balance of the gas as O .
4. The method of claim 1 where the ozone-containing atmosphere contains from 0.01% ozone to 20% ozone, with the balance of the gas as oxygen and an inert gas.
5. The method of claim 1 where the temperature is in the range of 200°C to 400°C
6. The method of claim 1 where cooling the dielectric is done rapidly.
7. A method for annealing gate and capacitor dielectrics comprising: placing the dielectric in a chamber; heating the chamber to an annealing temperature introducing an ozone-containing gas in the chamber at a flow rate in the range of about 20 seem to 10,000 seem; maintaining the annealing temperature and flow rate for an annealing time; removing the ozone containing annealing gas from the chamber; and, cooling the dielectric.
8. The method of claim 1 where the pressure in the chamber is from 1 Torr to 760 Torr.
9. The method of claim 7 where the ozone-containing annealing gas contains from 0.01% ozone to 20% ozone, with the balance of the gas as O2.
10. The method of claim 7 where the ozone-containing annealing gas contains from 0.01% ozone to 20% ozone, with the balance of the gas as oxygen and an inert gas.
11. The method as in claim 7 where the temperature is in the range of 20°C to 500°C
12. The method of claim 7 where cooling the dielectric is done rapidly.
13. A method of annealing gate and/or capacitor dielectrics comprising: exposing the dielectric to an annealing temperature for an annealing period of time in an atmosphere of ozone-containing gas; and removing the dielectric from the atmosphere of ozone-containing gas; and cooling the dielectric.
14. The method of claim 13 where the pressure in the chamber is from 1 Torr to 760 Torr.
15. The method of claim 13 where the ozone-containing annealing gas contains from 0.01% ozone to 20% ozone, with the balance of the gas as O2.
16. The method of claim 13 where the ozone-containing annealing gas contains from 0.01% ozone to 20% ozone, with the balance of the gas as oxygen and an inert gas.
17. The method as in claim 13 where the temperature is in the range of 20°C to 500°C
18. The method of claim 13 where the period of time is in the range of about 5 seconds to 1 minute.
19. The method of claim 13 where the annealing temperature is in the range of about l50°C to 450°C.
20. The method of claim 13 where the annealing temperature is less than about 100°C and further comprising: radiating UV light on the dielectric layer during said exposing step.
PCT/US2003/022235 2002-07-19 2003-07-16 Low temperature ozone anneal of gate and capacitor dielectrics WO2004010468A2 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6165834A (en) * 1998-05-07 2000-12-26 Micron Technology, Inc. Method of forming capacitors, method of processing dielectric layers, method of forming a DRAM cell
US6482686B1 (en) * 1993-08-27 2002-11-19 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
US20030207528A1 (en) * 2002-05-03 2003-11-06 Weimin Li Method of making a memory cell capacitor with Ta2O5 dielectric

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6482686B1 (en) * 1993-08-27 2002-11-19 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
US6165834A (en) * 1998-05-07 2000-12-26 Micron Technology, Inc. Method of forming capacitors, method of processing dielectric layers, method of forming a DRAM cell
US20030207528A1 (en) * 2002-05-03 2003-11-06 Weimin Li Method of making a memory cell capacitor with Ta2O5 dielectric

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