WO2004019403A3 - Mechanical recycling of a wafer comprising a buffer layer, after having taken a layer therefrom - Google Patents

Mechanical recycling of a wafer comprising a buffer layer, after having taken a layer therefrom Download PDF

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Publication number
WO2004019403A3
WO2004019403A3 PCT/IB2003/004029 IB0304029W WO2004019403A3 WO 2004019403 A3 WO2004019403 A3 WO 2004019403A3 IB 0304029 W IB0304029 W IB 0304029W WO 2004019403 A3 WO2004019403 A3 WO 2004019403A3
Authority
WO
WIPO (PCT)
Prior art keywords
layer
taking
wafer
donor wafer
taken
Prior art date
Application number
PCT/IB2003/004029
Other languages
French (fr)
Other versions
WO2004019403A2 (en
Inventor
Bruno Ghyselen
Cecile Aulnette
Benedite Osternaud
Vaillant Yves-Mathieu Le
Takeshi Akatsu
Original Assignee
Soitec Silicon On Insulator
Bruno Ghyselen
Cecile Aulnette
Benedite Osternaud
Vaillant Yves-Mathieu Le
Takeshi Akatsu
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR0210588A external-priority patent/FR2843827B1/en
Application filed by Soitec Silicon On Insulator, Bruno Ghyselen, Cecile Aulnette, Benedite Osternaud, Vaillant Yves-Mathieu Le, Takeshi Akatsu filed Critical Soitec Silicon On Insulator
Priority to EP03792598A priority Critical patent/EP1532676A2/en
Priority to JP2005501224A priority patent/JP2005537685A/en
Priority to US10/726,039 priority patent/US7033905B2/en
Publication of WO2004019403A2 publication Critical patent/WO2004019403A2/en
Publication of WO2004019403A3 publication Critical patent/WO2004019403A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer

Abstract

Method of recycling a donor wafer (10) after taking off at least one useful layer, the donor wafer (10) comprising successively a substrate (1), a buffer structure (I) and, before taking-off, a useful layer. The method comprsises employing mechanical means to remove part of the donor wafer (10) on the side where the taking-off took place, such that, after removal of substance, there remains at least part of the buffer structure (I) capable of being reused as at least part of a buffer structure (I) during a subsequent taking-off of a useful layer. The present document also relates to: a) methods of taking off a thin layer from a donor wafer (10) which can be recycled according to the invention; b) donor wafers (10) which can be recycled according to the invention.
PCT/IB2003/004029 2002-08-26 2003-08-26 Mechanical recycling of a wafer comprising a buffer layer, after having taken a layer therefrom WO2004019403A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP03792598A EP1532676A2 (en) 2002-08-26 2003-08-26 Mechanical recycling of a wafer comprising a buffer layer, after having taken a layer therefrom
JP2005501224A JP2005537685A (en) 2002-08-26 2003-08-26 Mechanical recycling of the wafer after removing the layer from the wafer containing the buffer layer
US10/726,039 US7033905B2 (en) 2002-08-26 2003-12-01 Recycling of a wafer comprising a buffer layer after having separated a thin layer therefrom by mechanical means

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
FR02/10588 2002-08-26
FR0210588A FR2843827B1 (en) 2002-08-26 2002-08-26 MECHANICAL RECYCLING OF A PLATE COMPRISING A STAMP LAYER AFTER SELECTING A THIN LAYER
US43193002P 2002-12-09 2002-12-09
US60/431,930 2002-12-09

Publications (2)

Publication Number Publication Date
WO2004019403A2 WO2004019403A2 (en) 2004-03-04
WO2004019403A3 true WO2004019403A3 (en) 2004-08-12

Family

ID=31947973

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2003/004029 WO2004019403A2 (en) 2002-08-26 2003-08-26 Mechanical recycling of a wafer comprising a buffer layer, after having taken a layer therefrom

Country Status (6)

Country Link
US (1) US7033905B2 (en)
EP (1) EP1532676A2 (en)
JP (1) JP2005537685A (en)
KR (1) KR100854856B1 (en)
CN (1) CN100557785C (en)
WO (1) WO2004019403A2 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6995430B2 (en) 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US20030227057A1 (en) 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
EP1962340A3 (en) * 2004-11-09 2009-12-23 S.O.I. TEC Silicon Method for manufacturing compound material wafers
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
EP2219208B1 (en) * 2009-02-12 2012-08-29 Soitec Method for reclaiming a surface of a substrate
KR101384872B1 (en) 2010-12-31 2014-04-18 솔렉셀, 인크. Method for reconstructing a semiconductor template
US8883612B2 (en) * 2011-09-12 2014-11-11 Infineon Technologies Austria Ag Method for manufacturing a semiconductor device
US10535685B2 (en) 2013-12-02 2020-01-14 The Regents Of The University Of Michigan Fabrication of thin-film electronic devices with non-destructive wafer reuse
CN103794471A (en) * 2014-01-14 2014-05-14 上海新储集成电路有限公司 Method for preparing compound semiconductor substrate
FR3074608B1 (en) * 2017-12-05 2019-12-06 Soitec PROCESS FOR THE PREPARATION OF A RESIDUE OF A DONOR SUBSTRATE, SUBSTRATE OBTAINED AT THE END OF THIS PROCESS, AND USE OF SUCH A SUBSTRATE

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0926709A2 (en) * 1997-12-26 1999-06-30 Canon Kabushiki Kaisha Method of manufacturing an SOI structure
EP0955671A1 (en) * 1998-04-23 1999-11-10 Shin-Etsu Handotai Company Limited A method of recycling a delaminated wafer and a silicon wafer used for the recycling
EP1039513A2 (en) * 1999-03-26 2000-09-27 Canon Kabushiki Kaisha Method of producing a SOI wafer
WO2001011930A2 (en) * 1999-08-10 2001-02-15 Silicon Genesis Corporation A cleaving process to fabricate multilayered substrates using low implantation doses
US6326279B1 (en) * 1999-03-26 2001-12-04 Canon Kabushiki Kaisha Process for producing semiconductor article
US20020072130A1 (en) * 2000-08-16 2002-06-13 Zhi-Yuan Cheng Process for producing semiconductor article using graded expital growth
WO2004006311A2 (en) * 2002-07-09 2004-01-15 S.O.I.Tec Silicon On Insulator Technologies Transfer of a thin layer from a wafer comprising a buffer layer

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JP3352340B2 (en) * 1995-10-06 2002-12-03 キヤノン株式会社 Semiconductor substrate and method of manufacturing the same
SG65697A1 (en) * 1996-11-15 1999-06-22 Canon Kk Process for producing semiconductor article
EP0849788B1 (en) 1996-12-18 2004-03-10 Canon Kabushiki Kaisha Process for producing semiconductor article by making use of a substrate having a porous semiconductor layer
US6143628A (en) * 1997-03-27 2000-11-07 Canon Kabushiki Kaisha Semiconductor substrate and method of manufacturing the same
US5994207A (en) * 1997-05-12 1999-11-30 Silicon Genesis Corporation Controlled cleavage process using pressurized fluid
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
CA2327421A1 (en) * 1998-04-10 1999-10-21 Jeffrey T. Borenstein Silicon-germanium etch stop layer system
JP2000349264A (en) * 1998-12-04 2000-12-15 Canon Inc Method for manufacturing, use and utilizing method of semiconductor wafer
JP3453544B2 (en) * 1999-03-26 2003-10-06 キヤノン株式会社 Manufacturing method of semiconductor member
US6375738B1 (en) * 1999-03-26 2002-04-23 Canon Kabushiki Kaisha Process of producing semiconductor article
JP3607194B2 (en) * 1999-11-26 2005-01-05 株式会社東芝 Semiconductor device, semiconductor device manufacturing method, and semiconductor substrate
JP4296726B2 (en) * 2001-06-29 2009-07-15 株式会社Ｓｕｍｃｏ Manufacturing method of semiconductor substrate and manufacturing method of field effect transistor
US6893424B2 (en) * 2002-07-04 2005-05-17 Semyon Shchervinsky Drain catheters

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0926709A2 (en) * 1997-12-26 1999-06-30 Canon Kabushiki Kaisha Method of manufacturing an SOI structure
EP0955671A1 (en) * 1998-04-23 1999-11-10 Shin-Etsu Handotai Company Limited A method of recycling a delaminated wafer and a silicon wafer used for the recycling
EP1039513A2 (en) * 1999-03-26 2000-09-27 Canon Kabushiki Kaisha Method of producing a SOI wafer
US6326279B1 (en) * 1999-03-26 2001-12-04 Canon Kabushiki Kaisha Process for producing semiconductor article
WO2001011930A2 (en) * 1999-08-10 2001-02-15 Silicon Genesis Corporation A cleaving process to fabricate multilayered substrates using low implantation doses
US20020072130A1 (en) * 2000-08-16 2002-06-13 Zhi-Yuan Cheng Process for producing semiconductor article using graded expital growth
WO2004006311A2 (en) * 2002-07-09 2004-01-15 S.O.I.Tec Silicon On Insulator Technologies Transfer of a thin layer from a wafer comprising a buffer layer

Also Published As

Publication number Publication date
JP2005537685A (en) 2005-12-08
US20040110378A1 (en) 2004-06-10
CN1679158A (en) 2005-10-05
CN100557785C (en) 2009-11-04
US7033905B2 (en) 2006-04-25
WO2004019403A2 (en) 2004-03-04
KR100854856B1 (en) 2008-08-28
KR20050039864A (en) 2005-04-29
EP1532676A2 (en) 2005-05-25

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