WO2004029984A3 - Non-volatile memory and its sensing method - Google Patents

Non-volatile memory and its sensing method Download PDF

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Publication number
WO2004029984A3
WO2004029984A3 PCT/US2003/029603 US0329603W WO2004029984A3 WO 2004029984 A3 WO2004029984 A3 WO 2004029984A3 US 0329603 W US0329603 W US 0329603W WO 2004029984 A3 WO2004029984 A3 WO 2004029984A3
Authority
WO
WIPO (PCT)
Prior art keywords
sensing
current
source line
memory cells
pass
Prior art date
Application number
PCT/US2003/029603
Other languages
French (fr)
Other versions
WO2004029984A2 (en
Inventor
Raul-Adrian Cernea
Yan Li
Original Assignee
Sandisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/254,830 external-priority patent/US7196931B2/en
Application filed by Sandisk Corp filed Critical Sandisk Corp
Priority to AU2003272596A priority Critical patent/AU2003272596A1/en
Priority to EP03754785A priority patent/EP1543529B1/en
Priority to DE60329924T priority patent/DE60329924D1/en
Priority to AT03754785T priority patent/ATE447761T1/en
Priority to CN038248646A priority patent/CN101084556B/en
Priority to JP2004540129A priority patent/JP4420823B2/en
Publication of WO2004029984A2 publication Critical patent/WO2004029984A2/en
Publication of WO2004029984A3 publication Critical patent/WO2004029984A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/067—Single-ended amplifiers

Abstract

Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the control gate voltage of a memory cell is erroneously biased by a voltage drop across the resistance. This error is minimized when the current flowing though the ground loop is reduced. A method for reducing source line bias is accomplished by read/write circuits with features and techniques for multi-pass sensing. When a page of memory cells are being sensed in parallel, each pass helps to identify and shut down the memory cells with conduction current higher than a given demarcation current value. In particular, the identified memory cells are shut down after all sensing in the current pass have been completed. In this way the shutting down operation does not disturb the sensing operation. Sensing in subsequent passes will be less affected by source line bias since the total amount of current flow is significantly reduced by eliminating contributions from the higher current cells. In another aspect of sensing improvement, a reference sense amplifier is employed to control multiple sense amplifiers to reduce their dependence on power supply and environmental variations.
PCT/US2003/029603 2002-09-24 2003-09-23 Non-volatile memory and its sensing method WO2004029984A2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
AU2003272596A AU2003272596A1 (en) 2002-09-24 2003-09-23 Non-volatile memory and its sensing method
EP03754785A EP1543529B1 (en) 2002-09-24 2003-09-23 Non-volatile memory and its sensing method
DE60329924T DE60329924D1 (en) 2002-09-24 2003-09-23 NON-VOLATILE MEMORY AND SELECTING PROCEDURE
AT03754785T ATE447761T1 (en) 2002-09-24 2003-09-23 NON-VOLATILE MEMORY AND READ-OUT METHOD
CN038248646A CN101084556B (en) 2002-09-24 2003-09-23 Non-volatile memory and method with improved sensing
JP2004540129A JP4420823B2 (en) 2002-09-24 2003-09-23 Nonvolatile memory and method with improved sensing behavior

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US10/254,830 US7196931B2 (en) 2002-09-24 2002-09-24 Non-volatile memory and method with reduced source line bias errors
US10/254,830 2002-09-24
US10/665,828 2003-09-17
US10/665,828 US7023736B2 (en) 2002-09-24 2003-09-17 Non-volatile memory and method with improved sensing

Publications (2)

Publication Number Publication Date
WO2004029984A2 WO2004029984A2 (en) 2004-04-08
WO2004029984A3 true WO2004029984A3 (en) 2004-12-23

Family

ID=32044968

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/029603 WO2004029984A2 (en) 2002-09-24 2003-09-23 Non-volatile memory and its sensing method

Country Status (6)

Country Link
US (1) US7212445B2 (en)
EP (1) EP1543529B1 (en)
JP (1) JP4420823B2 (en)
KR (1) KR100615975B1 (en)
AU (1) AU2003272596A1 (en)
WO (1) WO2004029984A2 (en)

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Also Published As

Publication number Publication date
US7212445B2 (en) 2007-05-01
EP1543529B1 (en) 2009-11-04
WO2004029984A2 (en) 2004-04-08
JP2006508483A (en) 2006-03-09
US20060050562A1 (en) 2006-03-09
EP1543529A2 (en) 2005-06-22
KR100615975B1 (en) 2006-08-28
AU2003272596A8 (en) 2004-04-19
KR20050084584A (en) 2005-08-26
JP4420823B2 (en) 2010-02-24
AU2003272596A1 (en) 2004-04-19

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