WO2004032183A2 - Realisation d'un substrat semiconducteur demontable et obtention d'un element semiconducteur. - Google Patents
Realisation d'un substrat semiconducteur demontable et obtention d'un element semiconducteur. Download PDFInfo
- Publication number
- WO2004032183A2 WO2004032183A2 PCT/FR2003/050077 FR0350077W WO2004032183A2 WO 2004032183 A2 WO2004032183 A2 WO 2004032183A2 FR 0350077 W FR0350077 W FR 0350077W WO 2004032183 A2 WO2004032183 A2 WO 2004032183A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- substrate
- layer
- weakened
- micro
- semiconductor material
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Definitions
- the present invention relates to a method for producing a removable semiconductor substrate. It also relates to a process for obtaining an element made of semiconductor material.
- Document FR-A-2 681 472 (corresponding to US patent 5,374,564) describes a process for manufacturing thin films of semiconductor material. It discloses that the introduction of a rare gas or hydrogen into a substrate is capable of inducing, under certain conditions, the formation of microcavities or micro-bubbles at a depth close to the average depth of penetration of the implanted ions. By bringing this substrate into intimate contact, through its implanted face, with a stiffener and carrying out a suitable heat treatment, there can be an interaction between the micro-cavities or micro-bubbles present in the implanted area. This interaction can then lead to a fracture in the implanted area of the semiconductor substrate.
- This process can also be applied to the manufacture of a thin film of solid material other than a semiconductor material, such as for example a conductive or dielectric material, crystalline or not, as disclosed in document FR-A-2,748 850 (corresponding to American patent n ° 6 190 998).
- the document FR-A-2,748,851 (corresponding to American patent n ° 6,020,252) describes a process making it possible to include technological steps requiring the use of high temperatures, for example 900 ° C., between the initial ion implantation step and the final separation step.
- These intermediate steps comprising heat treatments can be carried out without degrading the surface condition of the flat face of the wafer and without generating the fracture at the level of the implanted area, which would induce the separation of the thin surface layer. They can for example be part of the operations for producing electronic components.
- the step of ion implantation for example of hydrogen, must be carried out in a range of appropriate doses.
- the final separation step can then be carried out either by heat treatment, or by applying a mechanical stress to the structure, or even by a combination of these two treatments.
- Document FR-A-2 809 867 discloses a process comprising a step of introducing gaseous species according to a layer buried in the substrate, which will lead to the formation of micro-cavities in this layer. The buried implanted area thus weakened delimits a thin layer with one face of the substrate.
- the method also includes a step of eliminating all or part of the gaseous species from the weakened zone. This evacuation of the gas phase allows subsequent treatments to be carried out at high temperatures without inducing deformation of the surface (for example in the form of blisters or "blisters") or total or partial separation of the surface layer.
- a step of over-embrittlement of the area of the micro-cavities can optionally be carried out by carrying out appropriate heat treatments, by applying mechanical stresses or even by combining these two types of treatment.
- This over-embrittlement of the buried zone could, for example, facilitate the final separation between the surface layer of the substrate and the substrate.
- the stage of implantation of the gaseous species is carried out in a range of suitable doses allowing on the one hand the achievement of a sufficient embrittlement of the buried zone and on the other hand the subsequent elimination of the gaseous species.
- the masked zones can be chosen so as to protect the active zones from the components liable to undergo degradation during the crossing of the implanted ions.
- the dimensions of the masked areas are described in the order of 1 ⁇ m.
- the surface layer carried over comprises inhomogeneities of reliefs at the level of the non-implanted zones. These inhomogeneities are all the stronger the larger the dimensions (between 10 and 15 ⁇ m). The authors explain that these irregular reliefs come from the deviation of the crack in the cleavage planes (111) of the substrate.
- Another process also allows the development of a removable substrate capable of withstanding high temperature treatment (approximately
- This process is based on local implantation, made possible by the use of a mask when introducing ions.
- the size of the implanted regions is studied so that the subsequent heat treatments for embrittlement of the buried area and / or required for all or part of the steps for producing the components do not lead to degradation of the area. This constraint is linked to the subsequent stages of developing components, for example microelectronics, which require a perfect surface condition.
- the document FR-A-2 748 850 proposes a method of embrittlement of a substrate according to a buried layer, - by the introduction in low dose of a gaseous species (for example hydrogen).
- a gaseous species for example hydrogen.
- the implanted dose must be chosen so that thermal annealing does not induce deformation or surface exfoliation.
- the embrittlement stage reached in the implanted area may then prove to be insufficient. It may then be advantageous to increase the level of embrittlement of the implanted area.
- Document FR-A-2 758 907 proposes a local introduction of gaseous species after production of the components in the surface layer of the substrate.
- the introduction of these species leads to the formation of a discontinuous buried layer of micro-cavities capable of generating the fracture after joining of the processed substrate on a support substrate.
- the substrate is therefore weakened after the completion of the various technological stages in the manufacture of the components.
- the accessible size of the areas to be masked (which correspond to the active areas of the components) may prove to be limiting depending on the intended applications. For example, for component sizes of several tens of ⁇ m to several hundred ⁇ m, this technique is difficult to implement.
- the thickness of the active layer can reach several ⁇ m (for example, approximately 50 ⁇ m for the cells silicon photovoltaic).
- the introduction of gaseous species to a great depth while effectively protecting the zones by masking can then prove to be delicate, in particular because of the necessary equipment (specific implanters, accelerators) as well as expensive, for example for photovoltaic applications.
- a removable substrate can also be produced according to the method described above and using a mask at the time of the introduction of the ions.
- This process implements an intermediate masking step prior to implantation which will allow, by lateral confinement of buried micro-cracks, to greatly limit the appearance of deformations in the form of blisters on the surface of the substrate.
- the surface condition of the substrate is then perfectly compatible with different stages in the production of components, for example microelectronics.
- this method can have the disadvantage of a high cost, in particular in fields of application such as photovoltaics.
- the present invention was designed with a view to reducing costs, but keeping the objective of obtaining a processed surface layer which can be separated or detached from its substrate without breakage or deterioration of the structure.
- the subject of the invention is therefore a method of producing a removable semiconductor substrate, comprising the following steps:
- the introduction of gaseous species can be carried out by ion implantation or implantation by plasma immersion.
- a step of forming a thickener Before the step of heat treatment of the substrate, provision may be made for a step of forming a thickener whose thickness is large enough not to generate exfoliations in the thin layer and small enough to avoid separation of the substrate from the level of the weakened layer during the heat treatment step of the weakened layer.
- the thickener can then be totally or partially eliminated before the epitaxy step.
- An additional step of subjecting the epitaxial layer to at least one step of producing components can be provided. It can be a step of producing photovoltaic components.
- An additional step can also be provided for forming a protective layer on the epitaxial layer, this protective layer being intended to protect the epitaxial layer from chemical attack intended for the separation of the substrate at the level of the weakened layer.
- the subject of the invention is also a process for obtaining an element of semiconductor material, characterized in that it comprises the following steps:
- the detachment being either total to provide an element of semiconductor material forming a membrane and consisting of the thin layer of semiconductor material and the epitaxial layer, or partial for providing one or more elements of semiconductor material forming one or more components and consisting of part of the thin layer of semiconductor material and of the epitaxial layer.
- Detachment can result from the application of a tensile stress and / or a shear stress. It may result from the implementation of a step of introducing additional gaseous species into the embrittled layer, then of a step of mechanical stress and / or of heat treatment of the embrittled layer. It can also result from the application of an opening constraint at the level of the weakened layer. It can also result from a chemical attack on the weakened layer. It can still result from a combination of these methods.
- the step of supplying a removable semiconductor substrate may comprise the supply of a substrate which has already been dismantled and which is obtained by the process for producing a removable semiconductor substrate above and without prior surface conditioning.
- FIG. 1 is a cross-sectional view of '' a semiconductor substrate subjected to a ion implantation intended to form a weakened buried layer, according to the invention
- Figure 2 is a cross-sectional view of the semiconductor substrate of Figure 1 having undergone a heat treatment to increase the level of embrittlement of the weakened buried layer, according to the invention
- Figure 3 is a cross-sectional view of the semiconductor substrate of Figure 2 after the epitaxy of a layer of semiconductor material over the entire implanted face of the substrate, according to the invention
- Figure 4 is a cross-sectional view of the semiconductor substrate of Figure 2 after the epitaxy of a layer of semiconductor material on part of the implanted face of the substrate, according to the invention
- FIG. 5 is a cross-sectional view of the semiconductor substrate of Figure 3 after production of components in the epitaxial layer, according to the invention
- FIG. 6 is a cross-sectional view of the semiconductor substrate of Figure 5 after fixing the epitaxial layer on a support, according to the invention
- Figure 7 is a cross-sectional view of the semiconductor substrate fixed to its support, as shown in Figure 6, during the separation step, according to the invention.
- the method according to the invention applies in particular to the field of photovoltaic applications. It allows the production of a substrate (in particular in silicon) comprising a buried weakened layer, which can undergo the different stages of epitaxial growth and cell development, specific to the targeted photovoltaic application, then will allow the final separation between the surface layer processed and the rest of the substrate.
- a substrate in particular in silicon
- a buried weakened layer which can undergo the different stages of epitaxial growth and cell development, specific to the targeted photovoltaic application, then will allow the final separation between the surface layer processed and the rest of the substrate.
- This process is based on the implantation of gaseous species such as hydrogen ions and / or rare gases, capable of creating, around the maximum concentration depth, an area weakened by micro-cavities, "platelets” and / or micro-bubbles.
- a heat treatment is used to increase the level of embrittlement of the embrittled layer. This heat treatment will be called thereafter heat embrittlement treatment. Under certain conditions, this embrittlement heat treatment imposed on the implanted substrate results in the formation of cavities and / or micro-cracks in the weakened buried zone causing the appearance of blisters or bubbles or "blisters" on the surface of the substrate.
- the implantation conditions (the main parameters of which are energy, dose and temperature) as well as the parameters of the embrittlement heat treatment and of the various subsequent optional stages of preparation of the substrate (treatments thermal, layer deposits, etc.) must be chosen according to the nature of the substrate (nature of the material, crystalline orientation, etc.), so that no exfoliation of the surface layer appears.
- exfoliation is meant a partial detachment of the thin layer at the level of the weakened area.
- no exfoliation will be generated.
- the processed surface layer (approximately 50 ⁇ m) can be separated from the initial substrate by cracking in the area weakened by the micro- cavities and / or micro-cracks.
- the process begins with the creation of a weakened buried layer which will allow, after the completion of technological steps, the separation between a surface layer and the rest of the substrate. It is based on the introduction into the substrate of gaseous species such as hydrogen and / or other rare gases (helium ...) by a technique allowing a controlled localization of the species in depth (for example ion implantation, implantation by plasma immersion ). Such an implantation makes it possible to form a weakened buried zone typically composed of micro-cavities, "platelets" and / or micro- bubbles. This disturbed buried zone defines with the surface of the substrate a surface layer.
- gaseous species such as hydrogen and / or other rare gases (helium ...)
- steps for preparing the substrate comprising, for example, a heat treatment and / or a thickening deposit may be carried out on the substrate before the embrittlement heat treatment.
- the micro-cavities and / or "platelets” generated during the implantation will follow a growth law.
- the cumulative effect of the increase in the size of the cavities and / or micro-cracks and the gas pressure in them is the appearance of local deformations of the surface layer in the form of blisters.
- micro-cracks and / or cavities reflect the state of embrittlement of the implanted area.
- an oxide deposit can be made on the surface of the implanted substrate before any heat treatment.
- This will play a mechanical role of thickener which allows the micro-cracks to develop laterally according to larger dimensions, under the effect of an adequate thermal annealing. Characteristics of micro-cracks favorable to greater embrittlement can be obtained by adding this deposited layer.
- the implantation parameters, the embrittlement heat treatment as well as the substrate conditioning parameters dictate the size and density of blisters on the surface of the substrate. , that is to say also the size and density of micro-cracks and / or underlying cavities, contained in the implanted area.
- the level of embrittlement of the substrate can thus be configured as a function of the implantation conditions and the characteristics of the subsequent treatments.
- any subsequent treatment linked to the technological stages specific to the intended application, for example epitaxy in the range of 550 ° C - 1100 ° C, does not induce local exfoliation of the layer.
- the method according to the invention combines implantation conditions and embrittlement treatments making it possible to avoid local exfoliation of the surface layer before and after the different technological stages relating to the intended application.
- the morphology, the size and the density of the micro-cracks and cavities present in the weakened layer can be variable according to the subsequent treatments imposed on the weakened substrate.
- the high thermal budgets for which the reconstruction of the material constituting the substrate is significant have a notable influence on the morphological change of the microcracks formed after implantation, followed by a weakening treatment requiring a low thermal budget.
- these micro-cracks and / or cavities evolve towards stable polyhedral forms.
- the embrittlement step may also include a heat treatment at high temperature, so as to transform the micro-cracks and / or cavities present in the implanted area into stable objects (evacuation of all or part of the gaseous species and reconstruction at least partial of the edges of cracks). This is to avoid any phenomenon of exfoliation during the technological epitaxy and / or component production steps.
- the epitaxial growth of a thick layer of silicon may be carried out on the blistered substrate.
- the "soft" relief of the blisters on the surface typically with a diameter ranging from a few ⁇ m to a few tens of ⁇ m and whose maximum deformation can reach a few hundred nanometers) allows thick layers of monocrystalline silicon to be obtained by epitaxy quality for the intended application.
- the processed surface layer can be separated from
- This membrane can be separated on the total surface of the substrate or even locally at the level of a component or a set of components, by the application of an opening constraint at the level of the weakened zone.
- a low-cost support substrate can be bonded via an adhesive layer (polymer, resin, ceramic, metallic or other, etc.) to the processed layer of silicon. Separation, for example by applying stress in tensile and / or shear and / or in a mixed mode in the bonded structure can then be set at the buried weakened zone.
- an adhesive layer polymer, resin, ceramic, metallic or other, etc.
- the initial substrate on the one hand peeled with a thin layer (this layer being the area delimited by the implanted area and the surface of the initial substrate),
- a SECCO ® type solution has the property of attacking silicon and more preferably zones of constrained silicon and / or having undergone plastic deformations and / or disturbed by the presence of inclusions, structures or other morphological transformations.
- the weakened region having micro-cracks and / or cavities whose lateral size may vary from about a few tens of nanometers to a few tens of .mu.m, will be a privileged area of attack of the SECCO solution ®.
- this step consisting of a localized attack at the level of the weakened zone, can be carried out before the production of the components (for example photovoltaic cells).
- the components for example photovoltaic cells.
- This preferred chemical attack technique can be used alone to completely separate the processed membrane from its initial substrate, this in order to obtain a self-supporting layer or in order to transfer this membrane to an economical mechanical support.
- this chemical attack technique can be used in conjunction with a mechanical separation technique by application of external forces such as for example traction.
- the chemical attack will have the advantage of initiating and locating the crack at the level of the weakened buried zone and thus of facilitating the final decoupling.
- the substrate may be subjected to acoustic wave treatments (ultrasound, nanovibrations, etc.).
- a treatment intended to diffuse gaseous species for example hydrogen
- the techniques used can be, for example, plasma hydrogenation, or other methods of introducing gaseous species by diffusion.
- This step can make it possible to increase the level of embrittlement of the buried area of micro-cracks and / or micro-cavities.
- the species introduced into the material are preferably trapped in the region of micro-cracks.
- the final separation can then be carried out by a suitable heat treatment and / or by application of an adequate mechanical stress and / or by a treatment comprising both a heat treatment and a mechanical treatment.
- the initial substrate peeled from a surface layer can then be recycled to produce another substrate to be weakened.
- Figure 1 is a cross-sectional view of a semiconductor substrate 1, in this example it is a silicon substrate, which will be subjected to the method of the invention, according to a first example of implementation.
- the main face 2 of the silicon substrate 1 is covered with a layer of silicon oxide 3.
- An ion implantation of hydrogen symbolically represented by arrows in FIG. 1, is carried out in the substrate 1 through the oxide layer 3.
- the implantation beam has an energy of 210 keV and a dose of 6.10 16 H + / cm 2 . It causes the formation of a weakened buried layer 4 comprising micro-bubbles and micro-cavities. Annealing at 550 ° C. for 30 minutes is carried out on this substrate in order to increase the level of embrittlement of the implanted area. Indeed, under thermal activation, the cavities induced by the implantation follow a growth law to form micro-cracks and / or larger cavities which causes the appearance of blisters 5 on the surface of the substrate as shown Figure 2.
- FIG. 3 shows the presence of an epitaxial layer 6 on the main face 2 of the substrate 1.
- the thickness of the epitaxial layer 6 can be 50 ⁇ m.
- Liquid phase epitaxy can be done for a temperature of around 950 ° C for 2 hours.
- Vapor phase epitaxy can be done around 1100 ° C for 1 hour.
- the ion implantation of hydrogen is carried out for an energy of 76 keV and a dose of 6.10 16 H + / cm 2 through a layer of silicon oxide of 400 nm covering a silicon substrate.
- a deposition by PECVD is then carried out to obtain an additional layer of silicon oxide 3 ⁇ m thick.
- This substrate can then undergo an embrittlement treatment such as an annealing at increasing temperature starting from 400 ° C to 1100 ° C, the temperature rise being for example at 3 ° C / min and the duration of treatment at 1100 ° C being one hour.
- This treatment has the effect of growing the cavities and / or micro-cracks at the level of the implanted area and then stabilize these cavities and / or micro-cracks at high temperature so that there is no change in the surface condition of the substrate during removal of the thick layer of oxide or in subsequent technological stages.
- the oxidized surface of the substrate is then deoxidized, prior to a technological stage of epitaxy in the liquid or silicon vapor phase, with a thickness of between 20 ⁇ m and 50 ⁇ m.
- the implantation of hydrogen is carried out by plasma immersion for an energy of 76 keV and a dose of 6.10 16 H + / cm 2 through a layer of silicon oxide 400 nm covering a silicon substrate.
- a deposition by PECVD is then carried out to obtain an additional layer of silicon oxide 3 ⁇ m thick.
- This substrate can then undergo an embrittlement treatment such as an annealing at increasing temperature from 400 ° C to 1100 "C, the temperature rise being for example at 3 ° C / min.
- FIG. 4 illustrates this third example of implementation of the invention. It shows a silicon substrate 11 comprising a buried weakened layer 14, an oxide layer 13 remaining in a crown on the substrate 11 and an epitaxial layer 16 deposited on the part of the face 2 of the substrate not covered with oxide. It is clear that on the crown 13 the resumption of epitaxy has not been made.
- the ion implantation of hydrogen is carried out for an energy of 210 keV and a dose of 7.10 16 H + / cm 2 through a layer of silicon oxide of 200 nm covering a silicon substrate.
- a PECVD deposition is then carried out to obtain an additional layer of silicon oxide 10 ⁇ m thick.
- This substrate can then undergo embrittlement annealing at 450 ° C for 14 hours, followed by a rise at 3 ° C / min to 1100 ° C.
- the oxidized surface of the substrate is then partially deoxidized.
- the oxide is, for example, removed from the central part of the substrate but remains on a ring at the edge of the substrate, with a width which can range from a few hundred ⁇ m to a few mm.
- An epitaxy step in the silicon vapor phase to obtain an epitaxial layer with a thickness of between 20 and 50 ⁇ m is then carried out.
- the substrate comprises a central part on which the resumption of epitaxy of monocrystalline silicon was possible due to the deoxidation prior to the epitaxy.
- the substrate also includes, on its peripheral part, the crown of silicon oxide on which the resumption of epitaxy took place in polycrystalline form.
- the implantation of hydrogen by plasma immersion is carried out for an energy of 76 keV and a dose of 6.10 16 H + / cm 2 through a layer of silicon oxide 400 nm covering a double-sided polished silicon substrate.
- the implantation is carried out on the two main faces of the substrate.
- a 3 ⁇ m PECVD oxide deposit is made on this implanted double-sided substrate.
- This substrate then undergoes an embrittlement treatment such as an annealing at increasing temperature starting from 400 ° C to 1100 ° C, the temperature rise being for example at 3 ° C / min.
- the oxidized surfaces of the substrate are then partially deoxidized.
- the oxide is removed on a central part of the two faces of the substrate but remains on a crown at the edge with a width which can range from hundreds of ⁇ m to a few mm.
- a technological step of epitaxy in the liquid phase, with a thickness of between 20 ⁇ m and 50 ⁇ m is then carried out, on both sides of the substrate.
- the substrate comprises a central part on which resumption of epitaxy was possible due to the deoxidation prior to epitaxy.
- the substrate comprises, on the peripheral part of its faces, the PECVD oxide crown deposited on which resumption of epitaxy was not possible.
- the ion implantation of hydrogen is carried out for an energy of 52 keV and a dose of 5.5 ⁇ 10 16 H + / cm 2 through a layer of silicon oxide of 200 nm covering a silicon substrate.
- a deposit by PECVD is then carried out to obtain an additional oxide layer 5 ⁇ m thick.
- the substrate can then undergo embrittlement annealing at 500 ° C for 4 hours.
- the oxidized surface of the substrate is then completely deoxidized.
- An epitaxy step in liquid phase at 600 ° C. can then be carried out with the aim of obtaining an epitaxial layer of between 20 ⁇ m and 50 ⁇ m
- FIG. 5 shows components 7 produced in the epitaxial layer 6 of the substrate shown in FIG. 3. If the epitaxy was carried out on the two main faces of the substrate, components can then be produced in the two epitaxial layers.
- the substrate thus processed is then secured by means of a ceramic adhesive 8 for example on a mechanical support 9 such as a ceramic, glass or mullite substrate as shown in FIG. 6.
- a ceramic adhesive 8 for example on a mechanical support 9 such as a ceramic, glass or mullite substrate as shown in FIG. 6.
- the insertion in the region of the weakened layer 4, of a suitable tool comprising for example a bevelled blade will then make it possible to cut out at the level of the implanted buried zone, thus separating the processed layer 6 from its initial substrate 1, and the leaving it integral with the support substrate 9.
- the initial substrate 1 can then be recycled into a new substrate to be weakened.
- the processed substrate of the second embodiment of the invention can be secured by means of a polymer adhesive on a mechanical support such as a plastic substrate.
- a solution for example SECCO
- the immersion of the bonded structure in a solution, for example SECCO causes the preferential attack of the polycrystalline silicon, of the oxide crown and of the weakened buried zone, which can initiate the separation between the processed layer of its initial substrate.
- the separation can be carried out entirely according to this chemical route or else be assisted by the application of a mechanical stress or else be relayed by a purely mechanical opening route implementing tension and / or shear stresses as this is indicated by the arrows F in FIGS. 6 and 7.
- the initial substrate can then be recycled into new substrate to be weakened.
- the processed substrate of the third embodiment of the invention can be secured by means of a polymer adhesive on a mechanical support such as a plastic substrate.
- the bonded structure can then be immersed in an HF bath. This has the effect of attacking the peripheral oxide layer present on the weakened process substrate.
- the application of the stress during the insertion of a blade is better localized at the level of the weakened zone. This then leads to the separation between the processed layer and its initial substrate.
- the substrate initial can then be recycled into new substrate to weaken.
- the processed substrate of the fourth embodiment of the invention can be secured by means of a polymer adhesive on a mechanical support such as a plastic substrate.
- Immersion of the bonded structure in a solution, for example SECCO causes the preferential attack of the polycrystalline silicon, of the oxide crown and of the weakened buried zone, which can initiate the separation between the processed layer of its initial substrate.
- the separation can be carried out entirely according to this chemical route or else be assisted by the application of a mechanical stress or else be relayed by a purely mechanical opening route implementing tension and / or shear stresses as this is indicated by the arrows F in FIGS. 6 and 7.
- the initial substrate can then be recycled into new substrate to be weakened.
- the processed substrate of the fifth embodiment of the invention can be secured by means of a polymer adhesive on a mechanical support such as a plastic substrate.
- the bonded structure is then immersed in an HF bath. This has the effect of attacking the peripheral oxide layer present on each of the faces of the weakened processed substrate.
- the application of the stress during the insertion of a blade will be better localized at the level of the weakened zone. This constraint will be successively or jointly applied in the region of the layer weakened on both sides of the substrate. This then leads to the separation between the processed layers and the initial substrate.
- the initial substrate can then be recycled into a new substrate to be weakened.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03780289A EP1550158B1 (fr) | 2002-10-07 | 2003-10-03 | Realisation d un substrat semiconducteur demontable et obten tion d un element semiconducteur. |
AT03780289T ATE539446T1 (de) | 2002-10-07 | 2003-10-03 | Herstellung von einem abnehmbaren halbleitersubstrat und einem halbleiterelement |
JP2005500039A JP4777774B2 (ja) | 2002-10-07 | 2003-10-03 | 剥離可能な半導体基板を形成するための方法ならびに半導体素子を得るための方法 |
US10/530,640 US7238598B2 (en) | 2002-10-07 | 2003-10-03 | Formation of a semiconductor substrate that may be dismantled and obtaining a semiconductor element |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0212443A FR2845517B1 (fr) | 2002-10-07 | 2002-10-07 | Realisation d'un substrat semiconducteur demontable et obtention d'un element semiconducteur |
FR02/12443 | 2002-10-07 | ||
FR03/50130 | 2003-04-25 | ||
FR0350130A FR2845518B1 (fr) | 2002-10-07 | 2003-04-25 | Realisation d'un substrat semiconducteur demontable et obtention d'un element semiconducteur |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2004032183A2 true WO2004032183A2 (fr) | 2004-04-15 |
WO2004032183A3 WO2004032183A3 (fr) | 2004-07-29 |
Family
ID=32031847
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/FR2003/050077 WO2004032183A2 (fr) | 2002-10-07 | 2003-10-03 | Realisation d'un substrat semiconducteur demontable et obtention d'un element semiconducteur. |
Country Status (6)
Country | Link |
---|---|
US (1) | US7238598B2 (fr) |
EP (1) | EP1550158B1 (fr) |
JP (1) | JP4777774B2 (fr) |
AT (1) | ATE539446T1 (fr) |
FR (1) | FR2845518B1 (fr) |
WO (1) | WO2004032183A2 (fr) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2898431A1 (fr) * | 2006-03-13 | 2007-09-14 | Soitec Silicon On Insulator | Procede de fabrication de film mince |
CN106896410A (zh) * | 2017-03-09 | 2017-06-27 | 成都理工大学 | 利用声波测井资料解释岩石的变形模量和脆性指数的方法 |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4277481B2 (ja) * | 2002-05-08 | 2009-06-10 | 日本電気株式会社 | 半導体基板の製造方法、半導体装置の製造方法 |
JP2006270000A (ja) * | 2005-03-25 | 2006-10-05 | Sumco Corp | 歪Si−SOI基板の製造方法および該方法により製造された歪Si−SOI基板 |
FR2913968B1 (fr) * | 2007-03-23 | 2009-06-12 | Soitec Silicon On Insulator | Procede de realisation de membranes autoportees. |
US7856212B2 (en) * | 2007-08-07 | 2010-12-21 | Intel Corporation | Millimeter-wave phase-locked loop with injection-locked frequency divider using quarter-wavelength transmission line and method of calibration |
US7977221B2 (en) * | 2007-10-05 | 2011-07-12 | Sumco Corporation | Method for producing strained Si-SOI substrate and strained Si-SOI substrate produced by the same |
US20090124038A1 (en) * | 2007-11-14 | 2009-05-14 | Mark Ewing Tuttle | Imager device, camera, and method of manufacturing a back side illuminated imager |
US20090212397A1 (en) * | 2008-02-22 | 2009-08-27 | Mark Ewing Tuttle | Ultrathin integrated circuit and method of manufacturing an ultrathin integrated circuit |
JP5347345B2 (ja) * | 2008-06-16 | 2013-11-20 | 旭硝子株式会社 | 導電性マイエナイト型化合物の製造方法 |
US7905197B2 (en) * | 2008-10-28 | 2011-03-15 | Athenaeum, Llc | Apparatus for making epitaxial film |
US20100102419A1 (en) * | 2008-10-28 | 2010-04-29 | Eric Ting-Shan Pan | Epitaxy-Level Packaging (ELP) System |
WO2010062659A1 (fr) * | 2008-10-28 | 2010-06-03 | Athenaeum, Llc | Système et procédé pour l'assemblage d’un film épitaxial |
US7967936B2 (en) * | 2008-12-15 | 2011-06-28 | Twin Creeks Technologies, Inc. | Methods of transferring a lamina to a receiver element |
US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
RU2582160C2 (ru) * | 2011-04-11 | 2016-04-20 | Ндсю Рисёрч Фаундейшн | Избирательный лазерно-стимулированный перенос дискретных компонентов |
US9023729B2 (en) * | 2011-12-23 | 2015-05-05 | Athenaeum, Llc | Epitaxy level packaging |
US9184094B1 (en) * | 2012-01-26 | 2015-11-10 | Skorpios Technologies, Inc. | Method and system for forming a membrane over a cavity |
CN104507853B (zh) | 2012-07-31 | 2016-11-23 | 索泰克公司 | 形成半导体设备的方法 |
JP6757953B2 (ja) * | 2016-08-09 | 2020-09-23 | 学校法人 名古屋電気学園 | 表面加工方法、構造体の製造方法 |
FR3073082B1 (fr) * | 2017-10-31 | 2019-10-11 | Soitec | Procede de fabrication d'un film sur un support presentant une surface non plane |
FR3073083B1 (fr) * | 2017-10-31 | 2019-10-11 | Soitec | Procede de fabrication d'un film sur un feuillet flexible |
FR3094559A1 (fr) | 2019-03-29 | 2020-10-02 | Soitec | Procédé de transfert de paves d’un substrat donneur sur un substrat receveur |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2748851A1 (fr) * | 1996-05-15 | 1997-11-21 | Commissariat Energie Atomique | Procede de realisation d'une couche mince de materiau semiconducteur |
US5877070A (en) * | 1997-05-31 | 1999-03-02 | Max-Planck Society | Method for the transfer of thin layers of monocrystalline material to a desirable substrate |
EP0961312A2 (fr) * | 1998-05-15 | 1999-12-01 | Canon Kabushiki Kaisha | Substrat du type SOI fabriqué par collage |
FR2797347A1 (fr) * | 1999-08-04 | 2001-02-09 | Commissariat Energie Atomique | Procede de transfert d'une couche mince comportant une etape de surfragililisation |
FR2809867A1 (fr) * | 2000-05-30 | 2001-12-07 | Commissariat Energie Atomique | Substrat fragilise et procede de fabrication d'un tel substrat |
WO2002005344A1 (fr) * | 2000-07-12 | 2002-01-17 | Commissariat A L'energie Atomique | Procede de decoupage d'un bloc de materiau et de formation d'un film mince |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3412470B2 (ja) * | 1997-09-04 | 2003-06-03 | 三菱住友シリコン株式会社 | Soi基板の製造方法 |
US6306729B1 (en) * | 1997-12-26 | 2001-10-23 | Canon Kabushiki Kaisha | Semiconductor article and method of manufacturing the same |
JPH11233449A (ja) * | 1998-02-13 | 1999-08-27 | Denso Corp | 半導体基板の製造方法 |
US6291326B1 (en) * | 1998-06-23 | 2001-09-18 | Silicon Genesis Corporation | Pre-semiconductor process implant and post-process film separation |
FR2784795B1 (fr) * | 1998-10-16 | 2000-12-01 | Commissariat Energie Atomique | Structure comportant une couche mince de materiau composee de zones conductrices et de zones isolantes et procede de fabrication d'une telle structure |
US6255195B1 (en) * | 1999-02-22 | 2001-07-03 | Intersil Corporation | Method for forming a bonded substrate containing a planar intrinsic gettering zone and substrate formed by said method |
US6323108B1 (en) * | 1999-07-27 | 2001-11-27 | The United States Of America As Represented By The Secretary Of The Navy | Fabrication ultra-thin bonded semiconductor layers |
JP4450126B2 (ja) * | 2000-01-21 | 2010-04-14 | 日新電機株式会社 | シリコン系結晶薄膜の形成方法 |
TW452866B (en) * | 2000-02-25 | 2001-09-01 | Lee Tien Hsi | Manufacturing method of thin film on a substrate |
FR2816445B1 (fr) * | 2000-11-06 | 2003-07-25 | Commissariat Energie Atomique | Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible |
US20020187619A1 (en) * | 2001-05-04 | 2002-12-12 | International Business Machines Corporation | Gettering process for bonded SOI wafers |
-
2003
- 2003-04-25 FR FR0350130A patent/FR2845518B1/fr not_active Expired - Fee Related
- 2003-10-03 WO PCT/FR2003/050077 patent/WO2004032183A2/fr active Application Filing
- 2003-10-03 US US10/530,640 patent/US7238598B2/en not_active Expired - Fee Related
- 2003-10-03 EP EP03780289A patent/EP1550158B1/fr not_active Expired - Lifetime
- 2003-10-03 JP JP2005500039A patent/JP4777774B2/ja not_active Expired - Fee Related
- 2003-10-03 AT AT03780289T patent/ATE539446T1/de active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2748851A1 (fr) * | 1996-05-15 | 1997-11-21 | Commissariat Energie Atomique | Procede de realisation d'une couche mince de materiau semiconducteur |
US5877070A (en) * | 1997-05-31 | 1999-03-02 | Max-Planck Society | Method for the transfer of thin layers of monocrystalline material to a desirable substrate |
EP0961312A2 (fr) * | 1998-05-15 | 1999-12-01 | Canon Kabushiki Kaisha | Substrat du type SOI fabriqué par collage |
FR2797347A1 (fr) * | 1999-08-04 | 2001-02-09 | Commissariat Energie Atomique | Procede de transfert d'une couche mince comportant une etape de surfragililisation |
FR2809867A1 (fr) * | 2000-05-30 | 2001-12-07 | Commissariat Energie Atomique | Substrat fragilise et procede de fabrication d'un tel substrat |
WO2002005344A1 (fr) * | 2000-07-12 | 2002-01-17 | Commissariat A L'energie Atomique | Procede de decoupage d'un bloc de materiau et de formation d'un film mince |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2898431A1 (fr) * | 2006-03-13 | 2007-09-14 | Soitec Silicon On Insulator | Procede de fabrication de film mince |
EP1835534A1 (fr) * | 2006-03-13 | 2007-09-19 | S.O.I.Tec Silicon on Insulator Technologies | Procédé de fabrication de film mince |
US7588997B2 (en) | 2006-03-13 | 2009-09-15 | S.O.I.Tec Silicon On Insulator Technologies | Method of fabricating a thin film |
CN106896410A (zh) * | 2017-03-09 | 2017-06-27 | 成都理工大学 | 利用声波测井资料解释岩石的变形模量和脆性指数的方法 |
Also Published As
Publication number | Publication date |
---|---|
FR2845518A1 (fr) | 2004-04-09 |
ATE539446T1 (de) | 2012-01-15 |
WO2004032183A3 (fr) | 2004-07-29 |
US7238598B2 (en) | 2007-07-03 |
FR2845518B1 (fr) | 2005-10-14 |
JP4777774B2 (ja) | 2011-09-21 |
JP2006502593A (ja) | 2006-01-19 |
EP1550158A2 (fr) | 2005-07-06 |
US20060019476A1 (en) | 2006-01-26 |
EP1550158B1 (fr) | 2011-12-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP1550158B1 (fr) | Realisation d un substrat semiconducteur demontable et obten tion d un element semiconducteur. | |
EP1285461B1 (fr) | Procede de fabrication d'une couche mince | |
EP1678755B1 (fr) | Procede de transfert catastrophique d une couche fine apres co-implantation | |
EP1194951B1 (fr) | Procede de realisation d'un film mince utilisant une mise sous pression | |
EP2175478B1 (fr) | Procédé pour le transfert d'un film mince comportant une étape de création d'inclusions | |
EP1435111B1 (fr) | Procede de fabrication de couches minces contenant des microcomposants | |
EP1559138B1 (fr) | Procede de formation d'une zone fragile dans un substrat par co-implantation | |
WO2002037556A1 (fr) | Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible | |
WO2003017357A1 (fr) | Procede d'obtention d'une couche mince semiconductrice auto-portee pour circuits electroniques | |
FR2889887A1 (fr) | Procede de report d'une couche mince sur un support | |
FR2899378A1 (fr) | Procede de detachement d'un film mince par fusion de precipites | |
WO2008031980A1 (fr) | Procede de transfert d'une couche a haute temperature | |
EP2256798A1 (fr) | Traitement thermique de stabilisation d'interface de collage | |
EP2302666B1 (fr) | Procédé de planarisation par ultrasons d'un substrat dont une surface a été libérée par fracture d'une couche enterrée fragilisée | |
WO2014096690A1 (fr) | Procédé de fabrication d'une couche épaisse cristalline | |
EP3766094A1 (fr) | Procede de preparation d'une couche mince de materiau ferroelectriqie a base d'alcalin | |
FR2845517A1 (fr) | Realisation d'un substrat semiconducteur demontable et obtention d'un element semiconducteur | |
FR2873235A1 (fr) | Procede d'obtention d'un substrat demontable a energie de collage controlee |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): JP US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2003780289 Country of ref document: EP |
|
ENP | Entry into the national phase |
Ref document number: 2006019476 Country of ref document: US Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2005500039 Country of ref document: JP Ref document number: 10530640 Country of ref document: US |
|
WWP | Wipo information: published in national office |
Ref document number: 2003780289 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 10530640 Country of ref document: US |