WO2004032241A1 - Indium-boron dual halo for mosfet - Google Patents

Indium-boron dual halo for mosfet Download PDF

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Publication number
WO2004032241A1
WO2004032241A1 PCT/US2003/029769 US0329769W WO2004032241A1 WO 2004032241 A1 WO2004032241 A1 WO 2004032241A1 US 0329769 W US0329769 W US 0329769W WO 2004032241 A1 WO2004032241 A1 WO 2004032241A1
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WO
WIPO (PCT)
Prior art keywords
halo
indium
channel region
substrate
boron
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PCT/US2003/029769
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French (fr)
Inventor
Cory Weber
Gerhard Schrom
Ian Post
Mark Stettler
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Intel Corporation
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Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to AU2003272623A priority Critical patent/AU2003272623A1/en
Priority to EP03754816A priority patent/EP1547154A1/en
Publication of WO2004032241A1 publication Critical patent/WO2004032241A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface

Definitions

  • the field effect transistor is a common element of an integrated circuit such as a multiprocessor or other circuit.
  • the transistor typically includes a source and drain junction region formed in a semiconductor substrate and a gate electrode formed on a surface of the substrate.
  • the gate length is generally the distance between the source and drain junction region.
  • the region of the substrate beneath the gate electrode and between the source and drain junctions is generally referred to as a channel with a channel length being the distance between the source and drain junctions.
  • an N-type transistor device may have source and drain region (and gate electrode) doped with an N-type dopant such as arsenic.
  • the N-type junction regions are formed in a well that has previously been formed as a P-type conductivity.
  • a suitable P-type dopant is boron.
  • a transistor device works generally in the following way.
  • Carriers e.g., electrons, holes
  • V t threshold voltage
  • threshold voltage tends to decrease in response to reduced gate length.
  • performance is often dictated by a reduction in transistor size (e.g., faster switching, more devices on a chip, etc.) that dominates the objectives of the semiconductor processing industry.
  • gate electrode lengths approach dimensions less than 100 nanometers (ran)
  • a small change in the gate electrode length e.g., a 10 nanometer difference from a targeted length
  • the threshold voltage should be constant over a range of gate lengths about a target gate length to account for manufacturing margins.
  • locally implanted dopants P-type in N-type metal oxide semiconductor FETS (NMOSFETS) and N-type dopants in P-type metal oxide semiconductor FETS (PMOSFETS) may be introduced under the gate edges. Such implants are referred to as "halo" implants.
  • the implanted dopant tends to raise the doping concentration around the edges of the channel, thereby increasing the threshold voltage.
  • One effect is to reduce the threshold voltage of the target size device while maintaining the threshold voltage of the worst case size device.
  • Typical halo implants for NMOSFETS include boron (e.g., boron fluoride (BF 2 )) and indium (In).
  • Halo implants for PMOSFETS include arsenic, antimony, and phosphorous.
  • indium is a particularly preferred dopant because the channel of indium forms a retrograde profile from the surface of the device. Such a concentration profile with respect to indium, tends to decrease the threshold voltage required to meet a given leakage current (I off ) in the device relative to a boron dopant which does not have the same retrograde profile.
  • indium achieves a state of solid solubility at a point below the concentration required to reach worst case leakage currents.
  • a halo implant of an indium species alone cannot reach such targets.
  • Figure 1 shows a cross-sectional side view of a portion of a circuit substrate including a transistor device having a first halo implant.
  • Figure 2 shows the device of Figure 1 following a second halo implant.
  • Figure 3 shows a graphical representation of halo concentration in a substrate versus gate length for a selected leakage current.
  • Figure 4 shows the dopant concentration for P-type dopants in a silicon substrate.
  • Figure 5 shows a representative graph of threshold voltage versus P- type dopant concentration for a silicon substrate.
  • Figure 6 shows a graphical representation of leakage current versus threshold voltage for P-type dopants.
  • Figure 7 shows a graphical representation of threshold voltage versus gate length for an NMOSFET device.
  • Figure 8 shows a graphical representation of leakage current versus gate length for an NMOSFET.
  • Figure 9 shows a graphical representation of a number of devices on a substrate versus gate length.
  • Figure 10 shows a graphical representation of drive current versus gate length for a number of devices on a substrate.
  • Figure 11 shows a graphical representation of drive current versus leakage current for a transistor device.
  • indium is a preferred NMOSFET channel dopant (e.g., halo dopant) because its retrograde concentration profile results in lower threshold voltages and improved drive currents.
  • indium alone as a halo dopant is unacceptable because its solid solubility limit tends to prevent indium from doping an NMOSFET channel to a high enough level to maintain reasonable worst-case leakage currents.
  • Figure 1 shows a cross-sectional side view of a portion of a circuit substrate having a transistor device formed thereon.
  • Structure 100 includes substrate 110 of, for example, a semiconductor material, representatively silicon.
  • substrate 110 formed in and on substrate 110 in Figure 1 is a transistor device.
  • the transistor device is an NMOSFET, formed in P-type well 120.
  • the transistor device includes gate electrode 130 formed on the surface of substrate 110 having gate length 170.
  • the transistor device also includes source junction 140 and drain junction 150. In an NMOSFET, source junction 140 and drain junction 150 are both N-type as typically is gate electrode 130.
  • Source junction 140 includes tip implant 145 formed, for example, as self-aligned to gate electrode 130 (by an implant prior to the formation of spacer portions 135).
  • drain junction 150 includes tip implant 155 substantially aligned to gate electrode 130 (e.g., a lightly- doped drain). The bulk of drain junction 150 is aligned to spacers 135 on gate electrode 130.
  • Figure 1 also shows a single halo implant in channel region 160 of substrate 110.
  • first implant 180 is, for example, indium.
  • Halo implants may be formed by introducing dopant ions, such as indium ions, into substrate 110 at a tilt angle of, for example, 25-30°.
  • One way to introduce first halo 180 is an implanting operation after formation of the gate electrode (but before the spacers) so that the gate electrode acts as an aligned implant mask.
  • Figure 2 shows the structure of Figure 1 following the introduction of second halo 190.
  • first halo 180 is an indium species
  • second halo 190 is, for example, a boron species (e.g., boron diflouride).
  • Second halo 190 may be introduced by implantation according to a similar technique as first halo 180.
  • first halo 180 is indium
  • second halo 190 is boron or similar species
  • one technique involving multiple halos includes introducing first halo 180 into channel 120 of substrate 110 to a solid solubility of indium for silicon, generally 2E18 cm "3 .
  • a boron species is implanted as second halo 190 in an amount sufficient to achieve a target threshold voltage for a particular gate length device. It is appreciated that, having determined the appropriate amount of indium and boron dopants, the order by which either is introduced may vary.
  • a first halo e.g., first halo 180
  • a second halo e.g., second halo 190
  • structure 100 includes two halos introduced into channel 120.
  • the dopants described include indium and boron species. It is appreciated that other species may similarly be suitable for either NMOSFETS or PMOSFETS.
  • indium is selected and introduced to its solid solubility in the context of reduced gate lengths (e.g., on the order of 70 nanometers or less) to achieve target threshold voltages, leakage currents and drive currents.
  • Figure 3 shows a graphical representation of halo concentration in a silicon substrate versus gate length for a selected leakage current (I off ) of, for example, 40 nA.
  • Figure 3 shows that as gate lengths are decreased beyond approximately 100 nm, indium saturates and cannot, alone, achieve the desired leakage current.
  • Figure 4 representatively shows halo concentration in a silicon substrate.
  • Figure 3 demonstrates that a concentration required to meet a leakage current requirement (e.g., 3E18 cm "3 ) is greater than the indium solid solubility (e.g., on the order of 2E18 cm "3 ).
  • Figure 5 shows a graphical representation of threshold voltage versus dopant concentration.
  • Figure 5 demonstrates that at its solid solubility, indium saturates.
  • Figure 6 shows the graphical representation of leakage current versus threshold voltage.
  • Figure 6 demonstrates that at its solid solubility, indium again saturates (e.g., on the order of 100 nanoamps/ ⁇ m).
  • an additional halo implant in addition to a halo implant including an indium species, is used.
  • a second halo implant of a boron species may be used to achieve the target threshold voltage and target leakage current.
  • leakage current (I off ) for a worst-case gate length device is, for example, 100 nanoamps/ ⁇ m
  • a target gate length is, for example, 60 nanometers
  • an indium species may be introduced as a first halo to its solid solubility and a second halo of, for example, a boron species, may be introduced until a threshold voltage required to support the leakage current is established.
  • Figures 7 and 8 show graphical representations associated with threshold voltages and leakage currents for a particular gate length device.
  • the graphical representations illustrate the manufacturing tolerances associated with fabricating devices, particularly the acceptable variations in gate length.
  • a target gate length is 70 nanometers (nm) with a worst-case gate length on the order of -10 nm.
  • a halo implant, as illustrated in Figure 7, tends to reduce the threshold voltage of the target size device while maintaining the threshold voltage of the worst case size device.
  • the leakage current effects for various gate lengths are illustrated in Figure 8.
  • Figures 9 and 10 illustrate a multiple halo device such as described above and a prior art single halo/ boron well device.
  • Figure 9 shows a representation of devices formed on a substrate and their corresponding gate length. The devices adopt essentially a bell-shaped curve.
  • Figure 10 shows a typical drive current for the devices formed, in one case with a indium halo/boron well as in the prior art and, as multiple
  • FIG. 10 shows that the multiple (indium and boron) halo devices tend to have higher drive currents at target gate lengths, because they have higher leakage currents at target gate lengths.
  • Figure 11 shows a graphical representation of drive current versus leakage current for a transistor device.
  • N-type dopants such as arsenic and phosphorous may be introduced in a multiple halo process where effects such as, but not limited to, drive and leakage currents are to be optimized.
  • N-type dopants such as arsenic and phosphorous

Abstract

A method including forming a transistor device having a channel region; implanting a first halo into the channel region; and implanting a second different halo into the channel region. An apparatus including a gate electrode formed on a substrate; a channel region formed in the substrate below the gate electrode and between contact points; a first halo implant comprising a first species in the channel region; and a second halo implant including a different second species in the channel region.

Description

INDIUM-BORON DUAL HALO IMPLANT FOR MOSFET
BACKGROUND
Field
[0001] Circuit devices and methods for forming circuit devices.
Background
[0002] The field effect transistor (FET) is a common element of an integrated circuit such as a multiprocessor or other circuit. The transistor typically includes a source and drain junction region formed in a semiconductor substrate and a gate electrode formed on a surface of the substrate. The gate length is generally the distance between the source and drain junction region. Within the substrate, the region of the substrate beneath the gate electrode and between the source and drain junctions is generally referred to as a channel with a channel length being the distance between the source and drain junctions.
[0003] As noted above, many transistor devices are formed in a semiconductor substrate. To improve the conductivity of the semiconductor material of the substrate, dopants are introduced (e.g., implanted) into the substrate. Representatively, an N-type transistor device may have source and drain region (and gate electrode) doped with an N-type dopant such as arsenic. The N-type junction regions are formed in a well that has previously been formed as a P-type conductivity. A suitable P-type dopant is boron.
[0004] A transistor device works generally in the following way. Carriers (e.g., electrons, holes) flow between source junction and drain junction by the establishment of contacts on the substrate to the source and drain junction. In order to establish the carrier flow, a sufficient voltage must be applied to the gate electrode to form an inversion layer of carriers in the channel. This minimum amount of voltage is generally referred to as a threshold voltage (Vt).
[0005] In general, when fabricating multiple transistors of similar size, it is desired that a performance characteristic like threshold voltage be similar between devices. In general, the threshold voltage tends to decrease in response to reduced gate length. Of course, performance is often dictated by a reduction in transistor size (e.g., faster switching, more devices on a chip, etc.) that dominates the objectives of the semiconductor processing industry. As gate electrode lengths approach dimensions less than 100 nanometers (ran), what is seen is that the threshold voltage drops off or decreases rapidly. Therefore, even a small change in the gate electrode length (e.g., a 10 nanometer difference from a targeted length), can significantly affect the threshold voltage.
[0006] Ideally, the threshold voltage should be constant over a range of gate lengths about a target gate length to account for manufacturing margins. To, in one aspect, promote a more constant threshold voltage over a range of acceptable gate lengths, locally implanted dopants (P-type in N-type metal oxide semiconductor FETS (NMOSFETS) and N-type dopants in P-type metal oxide semiconductor FETS (PMOSFETS) may be introduced under the gate edges. Such implants are referred to as "halo" implants. The implanted dopant tends to raise the doping concentration around the edges of the channel, thereby increasing the threshold voltage. One effect is to reduce the threshold voltage of the target size device while maintaining the threshold voltage of the worst case size device.
[0007] Typical halo implants for NMOSFETS include boron (e.g., boron fluoride (BF2)) and indium (In). Halo implants for PMOSFETS include arsenic, antimony, and phosphorous. With respect to NMOSFETS, indium is a particularly preferred dopant because the channel of indium forms a retrograde profile from the surface of the device. Such a concentration profile with respect to indium, tends to decrease the threshold voltage required to meet a given leakage current (Ioff) in the device relative to a boron dopant which does not have the same retrograde profile. One problem with indium is that indium achieves a state of solid solubility at a point below the concentration required to reach worst case leakage currents. Thus, to target small leakage currents (e.g., on the order of 40 nanoamps (na) at device sizes less than 100 nanometers (nm)), a halo implant of an indium species alone cannot reach such targets.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] The features, aspects, and advantages of the invention will become more thoroughly apparent from the following detailed description, appended claims, and accompanying drawings in which:
[0009] Figure 1 shows a cross-sectional side view of a portion of a circuit substrate including a transistor device having a first halo implant.
[0010] Figure 2 shows the device of Figure 1 following a second halo implant.
[0011] Figure 3 shows a graphical representation of halo concentration in a substrate versus gate length for a selected leakage current.
[0012] Figure 4 shows the dopant concentration for P-type dopants in a silicon substrate.
[0013] Figure 5 shows a representative graph of threshold voltage versus P- type dopant concentration for a silicon substrate.
[0014] Figure 6 shows a graphical representation of leakage current versus threshold voltage for P-type dopants.
[0015] Figure 7 shows a graphical representation of threshold voltage versus gate length for an NMOSFET device. [0016] Figure 8 shows a graphical representation of leakage current versus gate length for an NMOSFET.
[0017] Figure 9 shows a graphical representation of a number of devices on a substrate versus gate length.
[0018] Figure 10 shows a graphical representation of drive current versus gate length for a number of devices on a substrate.
[0019] Figure 11 shows a graphical representation of drive current versus leakage current for a transistor device.
DETAILED DESCRIPTION
[0020] As noted above, indium is a preferred NMOSFET channel dopant (e.g., halo dopant) because its retrograde concentration profile results in lower threshold voltages and improved drive currents. However, for smaller devices, such as devices with target gate length at 60 nanometers or less, indium alone as a halo dopant is unacceptable because its solid solubility limit tends to prevent indium from doping an NMOSFET channel to a high enough level to maintain reasonable worst-case leakage currents.
[0021] Figure 1 shows a cross-sectional side view of a portion of a circuit substrate having a transistor device formed thereon. Structure 100 includes substrate 110 of, for example, a semiconductor material, representatively silicon. Formed in and on substrate 110 in Figure 1 is a transistor device. Representatively, the transistor device is an NMOSFET, formed in P-type well 120. The transistor device includes gate electrode 130 formed on the surface of substrate 110 having gate length 170. The transistor device also includes source junction 140 and drain junction 150. In an NMOSFET, source junction 140 and drain junction 150 are both N-type as typically is gate electrode 130. Source junction 140 includes tip implant 145 formed, for example, as self-aligned to gate electrode 130 (by an implant prior to the formation of spacer portions 135). The bulk of source junction 140 is aligned to spacer portions 135 on gate electrode 130 (by an implant after spacer portions 135 are formed). Similarly, drain junction 150 includes tip implant 155 substantially aligned to gate electrode 130 (e.g., a lightly- doped drain). The bulk of drain junction 150 is aligned to spacers 135 on gate electrode 130.
[0022] Figure 1 also shows a single halo implant in channel region 160 of substrate 110. In an embodiment where the transistor device is an NMOSFET, first implant 180 is, for example, indium. Halo implants may be formed by introducing dopant ions, such as indium ions, into substrate 110 at a tilt angle of, for example, 25-30°. One way to introduce first halo 180 is an implanting operation after formation of the gate electrode (but before the spacers) so that the gate electrode acts as an aligned implant mask.
[0023] Figure 2 shows the structure of Figure 1 following the introduction of second halo 190. For an NMOSFET as shown, representatively, where first halo 180 is an indium species, second halo 190 is, for example, a boron species (e.g., boron diflouride). Second halo 190 may be introduced by implantation according to a similar technique as first halo 180.
[0024] In the example where first halo 180 is indium, and second halo 190 is boron or similar species, one technique involving multiple halos includes introducing first halo 180 into channel 120 of substrate 110 to a solid solubility of indium for silicon, generally 2E18 cm"3. Following the implantation of an indium species to the indium solid solubility, a boron species is implanted as second halo 190 in an amount sufficient to achieve a target threshold voltage for a particular gate length device. It is appreciated that, having determined the appropriate amount of indium and boron dopants, the order by which either is introduced may vary. [0025] In the above embodiment, a first halo (e.g., first halo 180) of an indium species is introduced and a second halo (e.g., second halo 190) is introduced. Thus, structure 100 includes two halos introduced into channel 120. The dopants described include indium and boron species. It is appreciated that other species may similarly be suitable for either NMOSFETS or PMOSFETS. In one example, indium is selected and introduced to its solid solubility in the context of reduced gate lengths (e.g., on the order of 70 nanometers or less) to achieve target threshold voltages, leakage currents and drive currents. Figure 3 shows a graphical representation of halo concentration in a silicon substrate versus gate length for a selected leakage current (Ioff) of, for example, 40 nA. Figure 3 shows that as gate lengths are decreased beyond approximately 100 nm, indium saturates and cannot, alone, achieve the desired leakage current. Figure 4 representatively shows halo concentration in a silicon substrate. Figure 3 demonstrates that a concentration required to meet a leakage current requirement (e.g., 3E18 cm"3) is greater than the indium solid solubility (e.g., on the order of 2E18 cm"3).
[0026] Figure 5 shows a graphical representation of threshold voltage versus dopant concentration. Figure 5 demonstrates that at its solid solubility, indium saturates. Figure 6 shows the graphical representation of leakage current versus threshold voltage. Figure 6 demonstrates that at its solid solubility, indium again saturates (e.g., on the order of 100 nanoamps/ μm). Thus, with respect to achieving target threshold voltages and target leakage currents, an additional halo implant, in addition to a halo implant including an indium species, is used. As shown in Figure 5 and Figure 6, a second halo implant of a boron species may be used to achieve the target threshold voltage and target leakage current.
[0027] Based on the above graphical representations, for example, where leakage current (Ioff) for a worst-case gate length device is, for example, 100 nanoamps/ μm, where a target gate length is, for example, 60 nanometers, an indium species may be introduced as a first halo to its solid solubility and a second halo of, for example, a boron species, may be introduced until a threshold voltage required to support the leakage current is established.
[0028] Figures 7 and 8 show graphical representations associated with threshold voltages and leakage currents for a particular gate length device. The graphical representations illustrate the manufacturing tolerances associated with fabricating devices, particularly the acceptable variations in gate length. Representatively, for purposes of explanation, a target gate length is 70 nanometers (nm) with a worst-case gate length on the order of -10 nm. A halo implant, as illustrated in Figure 7, tends to reduce the threshold voltage of the target size device while maintaining the threshold voltage of the worst case size device. However, the leakage current effects for various gate lengths are illustrated in Figure 8. Representatively, for the prior art indium halo and boron well-type (indium halo/ boron well) device, a worst-case gate length leakage current compared to a target gate length device, the difference between worst- case and target is on the order of a factor of 10. Thus, even though a worst-case device may dominate the total leakage current, a multiple halo device such as described tends to reduce the difference between the leakage current for a worst- case device and a target device by, representatively, a factor of two.
[0029] Although a worst-case gate length device tends to dominate leakage current, the target devices tend to dominate drive current. Figures 9 and 10 illustrate a multiple halo device such as described above and a prior art single halo/ boron well device. Figure 9 shows a representation of devices formed on a substrate and their corresponding gate length. The devices adopt essentially a bell-shaped curve. Figure 10 shows a typical drive current for the devices formed, in one case with a indium halo/boron well as in the prior art and, as multiple
(indium and boron) halo devices. Figure 10 shows that the multiple (indium and boron) halo devices tend to have higher drive currents at target gate lengths, because they have higher leakage currents at target gate lengths. Figure 11 shows a graphical representation of drive current versus leakage current for a transistor device.
[0030] In the preceding detailed description, specific embodiments are illustrated, including a dual halo device of separate indium and boron implants. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the claims. For example, indium and boron implants have been described for an N-type devices (P-type dopants). It is contemplated that other dopants for N-type devices may be introduced in a similar manner (e.g., multiple halo). Alternatively, for P-type devices, it is contemplated that N-type dopants such as arsenic and phosphorous may be introduced in a multiple halo process where effects such as, but not limited to, drive and leakage currents are to be optimized. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

CLAIMS What is claimed is:
1. A method comprising: forming a transistor device having a channel region; implanting a first halo into the cham el region; and implanting a second different halo into the channel region.
2. The method of claim 1, wherein the first halo comprises indium.
3. The method of claim 2, wherein the concentration of the first halo in the substrate is in an amount equivalent to the solid solubility of indium.
4. The method of claim 3, wherein an amount of the second halo is selected to achieve a leakage current less than a minimum leakage current achievable by implanting only the first halo.
5. The method of claim 4, wherein the second halo comprises boron.
6. A method comprising: implanting a first halo into a channel region of a transistor device; and implanting a second different halo into the channel region in an amount sufficient to achieve a target threshold voltage for the device.
7. The method of claim 6, wherein the first halo comprises indium.
8. The method of claim 7, wherein the concentration of the first halo in the substrate is in an amount equivalent to the solid solubility of indium.
9. The method of claim 8, wherein the second halo comprises boron.
10. A method comprising: forming a plurality of transistors on a substrate according to a targeted gate length; implanting a first halo into a channel region of each of the plurality of transistors; implanting a second halo into the channel region of each of the plurality of transistors in an amount sufficient to achieve a target threshold voltage for a worst case acceptable gate length from the targeted gate length,
11. The method of claim 10, wherein the first halo comprises indium.
12. The method of claim 11, wherein the concentration of the first halo in the substrate is in an amount equivalent to the solid solubility of indium.
13. The method of claim 12, wherein the second halo comprises boron.
14. An apparatus comprising: a gate electrode formed on a substrate; a channel region formed in the substrate below the gate electrode and between contact points; a first halo implant comprising a first species in the channel region; and a second halo implant comprising a different second species in the channel region.
15. The apparatus of claim 14, wherein the first halo comprises indium.
16. The apparatus of claim 14, wherein the second halo comprises boron.
17. The apparatus of claim 15, wherein the concentration of the first halo in the substrate is in an amount equivalent to the solid solubility of indium.
PCT/US2003/029769 2002-09-30 2003-09-19 Indium-boron dual halo for mosfet WO2004032241A1 (en)

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