WO2004042802A3 - A method of rapidly thermally annealing multilayer wafers with an edge - Google Patents

A method of rapidly thermally annealing multilayer wafers with an edge Download PDF

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Publication number
WO2004042802A3
WO2004042802A3 PCT/IB2003/005295 IB0305295W WO2004042802A3 WO 2004042802 A3 WO2004042802 A3 WO 2004042802A3 IB 0305295 W IB0305295 W IB 0305295W WO 2004042802 A3 WO2004042802 A3 WO 2004042802A3
Authority
WO
WIPO (PCT)
Prior art keywords
edge
thermally annealing
rapidly thermally
multilayer wafers
multilayer
Prior art date
Application number
PCT/IB2003/005295
Other languages
French (fr)
Other versions
WO2004042802A2 (en
Inventor
Eric Neyret
Christophe Malleville
Original Assignee
Soitec Silicon On Insulator
Eric Neyret
Christophe Malleville
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator, Eric Neyret, Christophe Malleville filed Critical Soitec Silicon On Insulator
Priority to JP2005502143A priority Critical patent/JP4772501B2/en
Priority to AT03772490T priority patent/ATE528790T1/en
Priority to AU2003280109A priority patent/AU2003280109A1/en
Priority to EP03772490A priority patent/EP1559136B1/en
Publication of WO2004042802A2 publication Critical patent/WO2004042802A2/en
Publication of WO2004042802A3 publication Critical patent/WO2004042802A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67103—Apparatus for thermal treatment mainly by conduction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Abstract

The invention provides a method of thermally treating a multilayer wafer (10) with an edge, the wafer being made of materials selected from semiconductive materials and the method being characterized in that during annealing heating is adapted locally and selectively at the edge to take account of the local difference in heat absorption by the edge.
PCT/IB2003/005295 2002-11-05 2003-11-03 A method of rapidly thermally annealing multilayer wafers with an edge WO2004042802A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2005502143A JP4772501B2 (en) 2002-11-05 2003-11-03 Method for rapid thermal annealing of multi-layer wafers with edges
AT03772490T ATE528790T1 (en) 2002-11-05 2003-11-03 METHOD FOR RAPID TEMPING MULTI-LAYER WAFERS WITH ONE EDGE
AU2003280109A AU2003280109A1 (en) 2002-11-05 2003-11-03 A method of rapidly thermally annealing multilayer wafers with an edge
EP03772490A EP1559136B1 (en) 2002-11-05 2003-11-03 A method of rapidly thermally annealing multilayer wafers with an edge

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
FR0213810A FR2846786B1 (en) 2002-11-05 2002-11-05 PROCESS FOR QUICK THERMAL RECOVERY OF CROWN WAFERS
FRFR02/13810 2002-11-05
FRFR03/00286 2003-01-13
FR0300286A FR2846787B1 (en) 2002-11-05 2003-01-13 PROCESS FOR QUICK THERMAL RECOVERY OF CROWN WAFERS

Publications (2)

Publication Number Publication Date
WO2004042802A2 WO2004042802A2 (en) 2004-05-21
WO2004042802A3 true WO2004042802A3 (en) 2004-08-12

Family

ID=32109208

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2003/005295 WO2004042802A2 (en) 2002-11-05 2003-11-03 A method of rapidly thermally annealing multilayer wafers with an edge

Country Status (10)

Country Link
US (2) US6853802B2 (en)
EP (2) EP2330616A3 (en)
JP (1) JP4772501B2 (en)
KR (1) KR100814998B1 (en)
CN (1) CN100541739C (en)
AT (1) ATE528790T1 (en)
AU (1) AU2003280109A1 (en)
FR (2) FR2846786B1 (en)
TW (1) TWI278937B (en)
WO (1) WO2004042802A2 (en)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2846786B1 (en) * 2002-11-05 2005-06-17 PROCESS FOR QUICK THERMAL RECOVERY OF CROWN WAFERS
US20080090309A1 (en) * 2003-10-27 2008-04-17 Ranish Joseph M Controlled annealing method
US7127367B2 (en) * 2003-10-27 2006-10-24 Applied Materials, Inc. Tailored temperature uniformity
US8536492B2 (en) * 2003-10-27 2013-09-17 Applied Materials, Inc. Processing multilayer semiconductors with multiple heat sources
JP4826994B2 (en) * 2004-09-13 2011-11-30 信越半導体株式会社 Manufacturing method of SOI wafer
US7788589B2 (en) * 2004-09-30 2010-08-31 Microsoft Corporation Method and system for improved electronic task flagging and management
DE602004022882D1 (en) * 2004-12-28 2009-10-08 Soitec Silicon On Insulator NER LITTLE DENSITY OF HOLES
FR2880988B1 (en) * 2005-01-19 2007-03-30 Soitec Silicon On Insulator TREATMENT OF A LAYER IN SI1-yGEy TAKEN
JP4786925B2 (en) * 2005-04-04 2011-10-05 東京エレクトロン株式会社 Substrate processing method and substrate processing apparatus
US7700376B2 (en) * 2005-04-06 2010-04-20 Applied Materials, Inc. Edge temperature compensation in thermal processing particularly useful for SOI wafers
DE602005009159D1 (en) * 2005-06-10 2008-10-02 Soitec Silicon On Insulator Calibration method for thermal treatment equipment
FR2895563B1 (en) * 2005-12-22 2008-04-04 Soitec Silicon On Insulator METHOD FOR SIMPLIFYING A FINISHING SEQUENCE AND STRUCTURE OBTAINED BY THE METHOD
JP5168788B2 (en) * 2006-01-23 2013-03-27 信越半導体株式会社 Manufacturing method of SOI wafer
FR2899382B1 (en) * 2006-03-29 2008-08-22 Soitec Silicon On Insulator METHOD OF MANUFACTURING SOIL STRUCTURES WITH LIMITATION OF SLIDING LINES
EP1918349A1 (en) * 2006-10-12 2008-05-07 SOLVAY (Société Anonyme) Light-emitting material
US8222574B2 (en) * 2007-01-15 2012-07-17 Applied Materials, Inc. Temperature measurement and control of wafer support in thermal processing chamber
US7860379B2 (en) * 2007-01-15 2010-12-28 Applied Materials, Inc. Temperature measurement and control of wafer support in thermal processing chamber
US8111978B2 (en) * 2008-07-11 2012-02-07 Applied Materials, Inc. Rapid thermal processing chamber with shower head
FR2941324B1 (en) * 2009-01-22 2011-04-29 Soitec Silicon On Insulator PROCESS FOR DISSOLVING THE OXIDE LAYER IN THE CROWN OF A SEMICONDUCTOR TYPE STRUCTURE ON AN INSULATION
US7927975B2 (en) * 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
CN102479690B (en) * 2010-11-23 2013-12-11 中芯国际集成电路制造(上海)有限公司 Method for improving uniformity of working current on wafer during source drain annealing
US9814099B2 (en) * 2013-08-02 2017-11-07 Applied Materials, Inc. Substrate support with surface feature for reduced reflection and manufacturing techniques for producing same
CN108603290B (en) * 2015-10-01 2021-09-10 环球晶圆股份有限公司 CVD apparatus

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4958061A (en) * 1988-06-27 1990-09-18 Tokyo Electron Limited Method and apparatus for heat-treating a substrate
EP0399662A2 (en) * 1989-05-01 1990-11-28 AT&T Corp. Procedure for annealing of semiconductors
US5937142A (en) * 1996-07-11 1999-08-10 Cvc Products, Inc. Multi-zone illuminator for rapid thermal processing
US6051512A (en) * 1997-04-11 2000-04-18 Steag Rtp Systems Apparatus and method for rapid thermal processing (RTP) of a plurality of semiconductor wafers
US6184498B1 (en) * 1996-03-25 2001-02-06 Sumitomo Electric Industries, Ltd. Apparatus for thermally processing semiconductor wafer
WO2001069656A2 (en) * 2000-03-17 2001-09-20 Mattson Thermal Products Inc. Localized heating and cooling of substrates
US20010036219A1 (en) * 1999-05-03 2001-11-01 Camm David Malcolm Spatially resolved temperature measurement and irradiance control
EP1197989A2 (en) * 2000-10-10 2002-04-17 Ushiodenki Kabushiki Kaisha Heat treatment device and process with light irradiation

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62128525A (en) * 1985-11-29 1987-06-10 Matsushita Electric Ind Co Ltd Annealing method for compound semiconductor substrate
EP0511294B1 (en) * 1990-01-19 1996-04-03 Applied Materials, Inc. Heating apparatus for semiconductor wafers or substrates
DE19936081A1 (en) * 1999-07-30 2001-02-08 Siemens Ag Device and method for tempering a multilayer body, and a multilayer body produced using the method
KR100789205B1 (en) * 2000-03-29 2007-12-31 신에쯔 한도타이 가부시키가이샤 Production method for silicon wafer and soi wafer, and soi wafer
JP2002184961A (en) * 2000-09-29 2002-06-28 Canon Inc Soi substrate and thermal treatment method therefor
TW540121B (en) * 2000-10-10 2003-07-01 Ushio Electric Inc Heat treatment device and process with light irradiation
FR2846786B1 (en) * 2002-11-05 2005-06-17 PROCESS FOR QUICK THERMAL RECOVERY OF CROWN WAFERS

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4958061A (en) * 1988-06-27 1990-09-18 Tokyo Electron Limited Method and apparatus for heat-treating a substrate
EP0399662A2 (en) * 1989-05-01 1990-11-28 AT&T Corp. Procedure for annealing of semiconductors
US6184498B1 (en) * 1996-03-25 2001-02-06 Sumitomo Electric Industries, Ltd. Apparatus for thermally processing semiconductor wafer
US6235543B1 (en) * 1996-03-25 2001-05-22 Sumitomo Electric Industries, Ltd. Method of evaluating a semiconductor wafer
US5937142A (en) * 1996-07-11 1999-08-10 Cvc Products, Inc. Multi-zone illuminator for rapid thermal processing
US6051512A (en) * 1997-04-11 2000-04-18 Steag Rtp Systems Apparatus and method for rapid thermal processing (RTP) of a plurality of semiconductor wafers
US20010036219A1 (en) * 1999-05-03 2001-11-01 Camm David Malcolm Spatially resolved temperature measurement and irradiance control
WO2001069656A2 (en) * 2000-03-17 2001-09-20 Mattson Thermal Products Inc. Localized heating and cooling of substrates
EP1197989A2 (en) * 2000-10-10 2002-04-17 Ushiodenki Kabushiki Kaisha Heat treatment device and process with light irradiation

Also Published As

Publication number Publication date
CN100541739C (en) 2009-09-16
TWI278937B (en) 2007-04-11
FR2846786B1 (en) 2005-06-17
EP1559136A2 (en) 2005-08-03
FR2846786A1 (en) 2004-05-07
JP4772501B2 (en) 2011-09-14
WO2004042802A2 (en) 2004-05-21
US6853802B2 (en) 2005-02-08
CN1711629A (en) 2005-12-21
FR2846787A1 (en) 2004-05-07
KR20050062653A (en) 2005-06-23
TW200416895A (en) 2004-09-01
EP2330616A2 (en) 2011-06-08
ATE528790T1 (en) 2011-10-15
US20040151483A1 (en) 2004-08-05
EP1559136B1 (en) 2011-10-12
US7049250B2 (en) 2006-05-23
FR2846787B1 (en) 2005-12-30
AU2003280109A1 (en) 2004-06-07
AU2003280109A8 (en) 2004-06-07
JP2006505959A (en) 2006-02-16
EP2330616A3 (en) 2011-12-07
KR100814998B1 (en) 2008-03-18
US20050094990A1 (en) 2005-05-05

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