WO2004049429A1

WO2004049429A1 - Probe for testing flat panel display and manufacturing method thereof

Info

Publication number: WO2004049429A1
Application number: PCT/KR2003/002524
Authority: WO
Inventors: Oug-Ki Lee; Byung-Ho Jo; Chul-Hwan Goo; Yong-Hwi Jo; Sung-Young Oh; Jung-Bae Lee; Ki-Joon Kim
Original assignee: Phicom Corporation
Priority date: 2002-11-22
Filing date: 2003-11-21
Publication date: 2004-06-10
Also published as: AU2003282421A1; JP2006507512A; TW200419159A; JP4430621B2; TWI242647B

Abstract

The present invention relates to a probe for testing a flat panel display device, in which a plurality of conductors having a parallel arrangement are stacked between a plurality of other conductors, a probe assembly having the probe, and a method of manufacturing the probe and the probe assembly. The present invention provides a probe for testing a flat panel display device comprising: a plate-like dielectric; a plurality of conductors being provided in parallel; and first trenches being provided on at least one plane of upper and lower planes of the dielectric to fix the plurality of conductors in the dielectric in a predetermined arrangement.

Description

PROBE FOR TESTING FLAT PANEL DISPLAY AND MANUFACTURING

METHOD THEREOF

TECHNICAL FIELD The present invention relates to a probe for testing a flat panel display device and a method of manufacturing the probe. More specifically, the present invention relates to a probe for testing a flat panel display device, in which a plurality of conductors having a parallel arrangement are stacked between a plurality of other conductors, a probe assembly comprising the probe, and a method of manufacturing the probe and the probe assembly

In particular, the present invention relates to a probe for testing a flat panel display device, wherein a process of adhering probe conductors by means of a bonding machine during a production process in an MEMS unit is removed, thereby obtaining an accurate alignment of the conductors, and a method of manufacturing the probe.

In addition, the present invention relates to a probe for testing a flat panel display device, wherein probe conductors are formed on both planes of a single sacrifice substrate by using an MEMS process on the single sacrifice substrate, and a method of manufacturing the probe.

BACKGROUND ART

In general, a TFT-LCD (Thin Film Transistor Liquid Crystal Display) device, which is a flat panel display device, comprises a lower plate having a predetermined size in which a number of thin film transistors (TFT) and the respective pixel electrodes are provided, a color filter for colorization which is separated in a predetermined distance from the lower plate, an upper plate which is separated in a predetermined distance from the lower plate and common electrodes are sequentially provided on, and liquid crystal which is interposed between the upper and lower plates. The TFT-LCD device comprises a plurality of TFTs, which are switching elements, capacitor regions and auxiliary capacitor regions which are generated by the liquid crystal between the upper and lower plates, gate driving electrodes for driving ON/OFF of the TFTs, and image signal electrodes for applying external image signals, thereby displaying a predetermined image (including a moving image).

In addition, after being manufactured, the flat panel display device such as the TFT-LCD device is subjected to a test process of contacting a probe assembly with electrode pads of the flat panel display device in order to verify normality of the flat panel display device and remove failure of the flat panel display device in advance.

The test is performed by using a probe instrument comprising a probe assembly. Various types of the probe instruments have been developed. The probe instruments include a needle type probe instrument, a blade type probe instrument, a film type probe instrument, and an MEMS (Micro Electro Mechanical System) probe instrument.

Recently, the line width of patterning lines in the flat panel display device has been extremely sharpened as the flat panel display devices are highly integrated.

Therefore, there is much need to develop a probe assembly having an excellent reproducibility and a high productivity as well as to cope with the fine pitch of the flat panel display device.

DISCLOSURE OF INVENTION

The present invention is contrived to meet the aforementioned demands in the development. An object of the present invention is to a probe for testing a flat panel display device capable of simplifying the manufacturing processes and thus reducing process time, and a method of manufacturing the probe.

Another object of the present invention is to a probe for testing a flat panel display device capable of removing a process of adhering probe conductors by means of a boding machine during a production process in an

MEMS unit and thus capable of aligning the probe conductors with a high accuracy, and a method of manufacturing the probe.

An object of the present invention is to a probe for testing a flat panel display device capable of forming probe conductors on both planes of a sacrifice substrate by using an MEMS process on a single sacrifice substrate, and a method of manufacturing the probe.

In order to achieve the aforementioned objects, an aspect of the present invention is to provide a probe for testing a flat panel display device comprising: a plate-like dielectric; a plurality of conductors being provided in parallel; and first trenches being provided on at least one plane of upper and lower planes of the dielectric to fix the plurality of conductors in the dielectric in a predetermined arrangement.

Another aspect of the present invention is to provide a probe for testing a flat panel display device comprising a plurality of unit contact members being disposed and fixed separately in a predetermined interval on a lower portion of a thin film, wherein the thin film having a predetermined size, each of the unit contact members comprising a beam element having a shape of a bar, and wherein an inspection tip is provided at one end of the beam element in an integrated manner.

Another aspect of the present invention is to provide a probe for testing a flat panel display device comprising: a sacrifice substrate; first trenches being formed by using a photolithography process and an etching process; conductors being disposed to have a predetermined interval in the first trenches on the sacrifice substrate by using a conductive film formation process; a first dielectric being formed above the conductors; second trenches being formed by using a photolithography process and an etching process to expose the conductors on a lower plane of the sacrifice substrate; a second dielectric being formed by burying a dielectric material in the third trenches. Another aspect of the present invention is to provide a probe formed by using a single sacrifice substrate comprising: a plate-like dielectric; and a plurality of conductors where trenches are formed by a photolithography process and an etching process, wherein a conductive material is buried in the trenches, wherein the plurality of conductors are disposed in a predetermined interval on the upper and lower planes of the dielectric, and wherein the conductors formed on the upper plane and the conductors formed on the lower plane are disposed in parallel.

Another aspect of the present invention is to provide a probe formed by using a single sacrifice substrate comprising: a plate-like first dielectric; a second dielectric being stacked, where a step difference is formed at an upper portion of the first dielectric; a plurality of conductors being provided in a predetermined interval to pass through the first and second dielectrics; and a conductive layer being formed by stacking a conductive material on one plane of each of the conductors by a predetermined plating method. Another aspect of the present invention is to provide a probe formed by using a single sacrifice substrate comprising: a dielectric being formed by stacking a ceramic plate on upper and lower planes of an epoxy; a plurality of conductors being formed in a predetermined interval on the upper and lower planes of the dielectric; a conductive layer being stacked on one plane of each of the conductors by a predetermined plating method; and support members being stacked on the upper and lower planes of the dielectric to fix locations of the conductors.

Another aspect of the present invention is to provide a probe formed by using a single sacrifice substrate comprising: a plate-like dielectric; a plurality of conductors being formed in a predetermined interval on upper and lower planes of the dielectric; a conductive layer being stacked on one plane of each of the conductors by a predetermined plating method; support members being stacked on the upper and lower planes of the dielectric to fix locations of the conductors. Another aspect of the present invention is to provide a method of manufacturing a probe for testing a flat panel display device, comprising steps of: a first trench formation step of forming first trenches on at least one plane of upper and lower planes of a dielectric, thereby fixing a plurality of conductors on the dielectric in a predetermined arrangement; and a support member formation step of stacking a support member on an upper plane or a lower plane of the dielectric, thereby fixing the conductors in the first trenches on the dielectric.

Another aspect of the present invention is to provide a method of manufacturing a probe for testing a flat panel display device comprising: a conductor formation step of forming photoresist patterns having a predetermined thickness on at least one plane of an upper plane and a lower plane of a single sacrifice substrate having a predetermined thickness by using a photolithography process and a conductive film formation process, thereby forming conductors; a dielectric formation step of forming photoresist patterns to open a central portion of each of the conductors by using a photolithography, and forming a dielectric on the opened central portion of each of the conductors; a trench formation step of forming trenches to expose the lower plane of each of the conductors by using a photolithography and an etching process; a support member formation step of forming a support member by burying a support material in the trenches; and a finishing step of removing the sacrifice substrate.

Another aspect of the present invention is to provide a method of manufacturing a probe for testing a flat panel display device comprising: a first trench formation step of forming first trenches having bottoms being subjected to a rounding process by using a photolithography process and first and second etching processes; a conductor formation step of opening central portions including the first trenches by using a photolithography process and then burying a conductive material in the opened regions, thereby forming conductors; a dielectric formation step of forming a dielectric on an upper portion of each of the conductors by using a photolithography process and a dielectric film formation process; and a finishing process of removing the sacrifice substrate.

Another aspect of the present invention is to provide a method of manufacturing a probe sheet for testing a flat panel display device comprising step of: forming a first passivation film pattern on a sacrifice substrate, thereby defining regions where tips of a plurality of unit contact members are to be formed; forming trenches on the sacrifice substrate by performing an etching process using the first passivation film pattern as an etching mask; removing the first passivation film pattern; forming a second passivation film pattern on the sacrifice substrate where the first passivation film is removed, thereby defining regions where beam elements of the unit contact members are to be formed; forming beam elements of the unit contact members by forming a metallic film on the sacrifice substrate where the second passivation film pattern is formed; opening the beam elements of the unit contact members by removing the second passivation film pattern; slicing the sacrifice substrate, where the beam elements of the unit contact members are opened, in a predetermined size; locating a thin film having a predetermined size ^"on the sliced sacrifice substrate, and attaching and fixing the beam elements of the unit contact members on the lower portion of the thin film; and opening the tips of the unit contact members by removing the sacrifice substrate where the thin film is attached and fixed.

Another aspect of the present invention is to provide a method of manufacturing a probe by using a single sacrifice substrate comprising: a first trench formation step of forming first trenches on upper and lower planes of the single sacrifice substrate by using a photolithography process and etching process, wherein the single sacrifice substrate has a predetermined thickness; a conductor formation step of forming conductors by burying a conductive material in the first trenches; a second trench formation step of forming second trenches on the lower portions of the conductors by using a photolithography process and an etching process; a dielectric formation step of forming a dielectric by burying a dielectric material in the second trenches; a support member formation step of forming a support member on at least one plane of the upper and lower planes of the sacrifice substrate where the dielectric is formed; and a finishing step of removing the sacrifice substrate. Another aspect of the present invention is to provide a method of manufacturing a probe by using a single sacrifice substrate comprising: a first passivation film formation step of forming a first passivation film above the single sacrifice substrate, wherein the single sacrifice substrate has a predetermined thickness, wherein the first passivation film pattern is used to form conductors; a upper conductor formation step of forming upper conductors by burying a conductive material in the first passivation film pattern; a second passivation film formation step of forming a second passivation film above the sacrifice substrate where the conductors are formed, wherein the second passivation film is used to form a support member; an upper support formation step of forming an upper support member in the second passivation film pattern; a trench formation step of forming trenches on a lower plane of the sacrifice substrate by using a photolithography process and an etching process to expose the upper conductors; a dielectric formation step of forming a dielectric by burying a dielectric material in the trenches; and a step of removing the sacrifice substrate. Another aspect of the present invention is to provide a method of manufacturing a probe by using a single sacrifice substrate comprising: a first trench formation step of forming first trenches on a predetermined portion of the single sacrifice substrate, wherein the single sacrifice substrate are made up of a predetermined material and are subjected to a polishing process to have a predetermined thickness, wherein the trenches are used to form a dielectric; a dielectric formation step of forming the dielectric by burying a dielectric material in the first trenches; a conductor formation step of forming conductors by forming a passivation film pattern on upper and lower planes of the sacrifice substrate where the dielectric is formed and then burying a conductive material in the passivation film pattern; and a finishing step of removing the sacrifice substrate.

Another aspect of the present invention is to provide a method of manufacturing a probe by using a single sacrifice substrate comprising: a trench formation step of forming trenches having predetermined depths on a predetermined region of an upper plane of a single sacrifice substrate; a first passivation film pattern formation step of forming a first passivation film pattern on the sacrifice substrate where the trenches are formed, thereby opening the trenches; a trench burying step of burying a trench burying material into the trenches which are opened by the first passivation film pattern, wherein the trench burying material is removed by an etching process; a second passivation film pattern formation step of forming a second passivation film on upper and lower planes of the sacrifice substrate by using a photolithography process, wherein the second passivation film pattern is used to form conductors; a conductor formation step of forming conductors at specific locations which are defined by the second passivation film pattern; a third passivation film pattern formation step of forming a third passivation film pattern on the upper and lower planes of the sacrifice substrate where the conductors are formed, wherein the third passivation film pattern is used to form a support member; a support member formation step of forming a support member at specific locations which are defined by the third passivation film pattern; and a finishing step of removing portions of the sacrifice substrate partitioned by the trench burying material and then removing the trench burying material.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, advantages and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which: Fig. l a is a perspective view for explaining a probe for testing a flat panel display device and a method of manufacturing the probe according to an embodiment of the present invention, Fig. lb is a longitudinal cross-sectional view of Fig. l a, and Fig. lc is a transverse cross-sectional view of Fig. la;

Figs. 2a and 2b are perspective views illustrating processes of another embodiment of a probe for testing a flat panel display device manufactured in accordance with Figs, la to lc, Fig. 2b is a longitudinal cross-sectional view of Fig. 2a, and Fig. 2c is a transverse cross-sectional view of Fig. 2a;

Figs. 3a to 3e are perspective views illustrating another embodiment of a probe for testing a flat panel display device manufactured in accordance with Figs. 2a to 2c; Fig. 4a and 4b are perspective views illustrating a double-layered probe for testing a flat panel display device manufactured according to an MEMS process of the present invention;

Fig. 5a is perspective view illustrating a single-layered probe for testing a flat panel display device manufactured according to an MEMS process of the present invention, and Fig. 5b is a longitudinal cross-sectional view of Fig. 5a;

Figs. 6a to 6p are cross-sectional views for explaining a method of manufacturing a probe for testing a flat panel display device according to another embodiment;

Figs. 7a to 7i are cross-sectional views for explaining a method of manufacturing a probe for testing a flat panel display device according to another embodiment;

Figs. 8a to 8t are cross-sectional views for explaining a method of manufacturing a probe for testing a flat panel display device according to another embodiment;

Fig. 9 is a perspective view for explaining a method of manufacturing a probe for testing a flat panel display device according to another embodiment; Fig. 10a is an exploded perspective view for explaining a probe according to another embodiment and Fig. 10b is a cross-sectional view thereof;

Fig. 1 1 is a perspective view for explaining a probe for testing a flat panel display device according to another embodiment; Figs. 12a to 12i are cross-sectional views for explaining a method of manufacturing a probe for testing a flat panel display device according to another embodiment;

Figs. 13a to 13d are cross-sectional views of individual processes for explaining a method of manufacturing a probe for testing a flat panel display device according to another embodiment;

Fig. 14 is a perspective view of a probe manufactured according to the method illustrated in Figs. 13a to 13d;

Figs. 15a to 15e are cross-sectional views of individual processes for explaining a method of manufacturing a probe for testing a flat panel display device according to another embodiment;

Fig. 16 is a perspective view of a probe manufactured according to the method illustrated in Figs. 15a to 15e;

Figs. 17a to 17c are cross-sectional views of individual processes for explaining a method of manufacturing a probe for testing a flat panel display device according to another embodiment;

Figs. 18a to 18c are cross-sectional views of individual processes for explaining a method of manufacturing a probe for testing a flat panel display device according to another embodiment;

Figs. 19a to 19d are cross-sectional views of individual processes for explaining a method of manufacturing a probe for testing a flat panel display device according to another embodiment;

Fig. 20 is a perspective view of a probe manufactured according to the method illustrated in Figs. 17a to 17d;

Fig. 21 a is a perspective view and a cross-sectional view illustrating a ceramic plate used in the present invention, of which cross section has a shape of a parallelogram, and Fig. 21b is a perspective view and a cross-sectional view illustrating a ceramic plate used in the present invention, of which cross section has a shape of a step;

Fig. 22a is a perspective view for explaining a first probe assembly comprising a probe for testing a flat panel display device according to the present invention, and Fig. 22b is a cross-sectional view thereof;

Fig. 23 is a view for explaining a connection between a TCP (Tape Carrier Package) and the unit conductor member shown in Figs. 22 and 24;

Fig. 24a is a perspective view for explaining a second probe assembly comprising a probe for testing a flat panel display device according to the present invention, and Fig. 24b is a cross-sectional view thereof;

Fig. 25 is a perspective view illustrating a probe assembly comprising a probe according to the present invention; and

Fig. 26 is a cross-sectional view illustrating a probe assembly comprising a probe according to the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

In the specification of the present invention, it is noted that a "probe" referred to in the present invention means a "probe structure." Firstly, before the detailed description of the embodiments of the probe for testing a flat panel display device according to the present invention, the conceptual construction of the probe will be described.

As shown in Figs, la tol c and Figs. 2a to 2c, a dielectric 10, which has a plate-like shape, is made up of a dielectric material such as a ceramic. The dielectric 10 preferably has a thickness of 240 tm. In addition, both ends of the dielectric 10 preferably have a step-difference shape or a slanted shape. In addition, since the dielectric 10 has a function of maintaining the shape of the probe as well as a function of insulation, it is preferable that the dielectric is made up of a hard material. Conductors 20a and 20b, which are made up of nickel (Ni) or a nickel alloy, have a shape of a bar of which both distal portions have an acute shape.

There are different methods of fabricating the conductors in accordance with the embodiments. In a first embodiment, trenches in which the conductors are to be inserted are formed by using a dicing saw process, the conductors having acute distal portions are attached and fixed in the respective trenches, whereby the conductors are provided on the dielectric 10.

In a second embodiment, the conductors, of which locations and sizes are determined based on a photolithography process, are disposed in a predetermined interval on at least one plane of the upper and lower planes of the dielectric.

The conductors 20a and 20b are provided to be in contact with the upper and lower planes of the dielectric 10, respectively. Although two rows of the conductors are formed on the upper and lower planes of the dielectric, respectively, one row of the conductors may be provided within the dielectric 10.

In addition, in the case that one row of conductors is provided within the dielectric, a single layer probe is formed, as shown in Figs. 2a to 2c.

As the probe being viewed from the upper portion of the probe, the conductors 20a and 20b are disposed so that the each of the conductors 20a provided on the upper plane of the dielectric 10 can be located between adjacent conductors 20b of the lower plane of the dielectric 10.

In addition, the length of each of the conductors 20a provided on the upper plane of the dielectric 10 has the same as that of each of the conductors

20b provided on the lower plane of the dielectric, the left and right protruding portions of the conductors 20a and 20b, which are externally protruded from the dielectric 10, have all the same lengths.

As shown in Fig. lc, the distal portions of the conductors 20a provided on the upper plane of the dielectric 10 are protruded more than the distal portions of the conductors 20b provided on the lower plane of the dielectric 10. In particular, the conductors 20a and 20b are preferably formed so that a line 11 connecting the distal portions of the conductors 20a provided on the upper plane of the dielectric 10 to the distal portions of the conductors 20b provided on the lower plane of the dielectric 10 can have an angle of 30° to 60°with reference to the surface of each of the conductors. Each of the conductors 20a and 20b which are fabricated to have a thickness of 60± 5 m is used.

There are mainly two embodiments in a method of manufacturing the probe for testing a flat panel display device comprising the conductors 20a and 20b provided on the dielectric 10, as described later. The first embodiment is a method of manufacturing the probe by using a dicing saw process, and the second embodiment is a method of manufacturing the probe by using an MEMS process.

In the case of using the MEMS process, it is possible to form thin conductive materials 40a and 40b, which have better electrical conductivity than that of the conductors, on the surfaces of the conductors 20a and 20b. The conductive material is preferably formed with a gold plating layer. The conductive materials 40a and 40b are formed in order to improve the conductivity of each of the conductors.

In addition, provided are support members 30a and 30b which are formed with an epoxy, a ceramic plate, or a combination of the epoxy and the ceramic plate. The support members are in contact with the upper portions of the conductors 20a and 20b in order to reinforce the conductors 20a and 20b.

In addition, the present invention discloses a single-layered probe as well as the double-layered probe. As shown in Figs. 2a to 2c, the single- layered probe comprises a plate-like dielectric 80 having a predetermined size, a plurality of conductors 50 being provided in a certain interval in parallel passing through the dielectric, and a plate-like support member 60 being formed to be in contact with one plane of upper and lower planes of the dielectric 80.

In the case of using the MEMS process, a conductive material having an excellent electrical conductivity may be formed on the one plane of each of the conductors 50 in the single-layered probe. The conductive material is preferably gold, thereby a gold plating layer 70 being formed.

The components of the single-layered probe are the same as those of the double-layered probe, and also have the same functions as those thereof. Therefore, the detailed description of them will be omitted.

(First Embodiment)

According to the First embodiment, a probe for testing a flat panel display device is manufactured by forming trenches (slits) on a rectangular reinforcement plate made up of a hard material by using a dicing saw process and inserting and fixing conductors into the trenches, whereby the conductors are used as needles for testing a flat panel display device.

Now, the first embodiment will be described with reference to Figs 3 to 5. Figs. 3a to 3e are perspective views illustrating a probe for testing a flat panel display device in accordance with the first embodiment of the present invention and a process flow for explaining a method of manufacturing the probe.

In the probe for testing a flat panel display device in accordance with the present invention and the method of manufacturing the probe, as shown in Fig. 3a, a support plate 90 having a rectangular plate shape are prepared. The support plate is made up of a hard material such as a ceramic. A central groove 93 are formed in a longitudinal direction form one side to the opposite side of an upper plane of the support plate 90, so that a first protrusion region 91 and a second protrusion region 95 can be formed to face each other on the upper plane of the support plate 90.

The central groove 93 may be formed with a dicing saw, or the like.

Next, as shown in Fig. 3b, a plurality of trenches 97a and 97b, each of which has a needle shape, are formed on the upper surfaces of the first and second protrusion regions 91 and 95 on the support plate 90, respectively, by using a dicing saw process. The plurality of trenches 97a and 97b are connected to the central groove 14.

In addition, the trenches 97a and 97b, which are formed on the first and second protrusion regions 91 and 95, respectively, have the same interval in order to face each other as shown in Fig. 3c. Otherwise, the trenches may be formed in a manner that the trenches 97a formed on the first protrusion region 91 has a fine interval and the trenches 97b formed on the second protrusion regions 95 has a coarse interval, or vice versa.

In particular, with respect to the depths of the trenches 97a and 97b, the trenches are preferably formed to be on an equal level with that of the central groove 93, or the trenches are more deeply formed than the central groove 93, so that the evenness of the conductors provided in the trenches 97a and 97b can be determined based on the evenness of the central groove 93.

Subsequently, as shown in Fig. 3d, the conductors 98 having a predetermined length and a predetermined diameter, each of which has acute- shaped distal portions, are located in the trenches 97a and 97b which are formed on the first protrusion region 91 and the second protrusion region 95 of the support plate 90, respectively.

Each of the conductors 98 has a predetermined length to be protruded externally from the support plate 90, so that one distal portion of each of the conductors can be used as a contact member for being directly in contact with the test position of the flat panel display device and the other distal portion can be used as a connect member. The conductors 98 are made up of tungsten or a tungsten alloy. As shown in Fig. 3e, an adhesive is applied above the support plate 90 where the needles, or the conductors (needles) 98, are provided to be inserted in the trenches 97a and 97b formed on the first and second protrusion regions 91 and 95, and then the adhesive such as an epoxy is applied and cured to be attached on the conductors on the support plate, whereby the probe is manufactured. Now, an embodiment of a method of manufacturing the probe which is described with reference to Fig. 3 will be described with reference to Figs. 4 and 5.

Fig. 4a and 4b are perspective views for explaining a probe for testing a flat panel display device according to another embodiment of the present invention and a method of manufacturing the probe.

In the probe for testing a flat panel display device in accordance with the embodiment of the present invention and the method of manufacturing the probe, as shown in Fig. 4a, the other support plate 100 on which the secondary probe are formed are provided above the support plate 90 in the first embodiment. Herein, the support plate 100 is manufactured with the same manufacturing method as that of the support plate 90.

The probe located at the upper portion, which is referred to as an upper probe, is formed with the same manufacturing method as that of the probe in the first embodiment, which is referred to as a lower probe. That is, trenches 107a which are formed on a first protrusion region 101 are connected to a central groove 103, and conductors 108 which are located in the trenches 107a are attached and fixed with an adhesive such as an epoxy 109. And also, the other trenches are formed on a second protrusion region 105, but they are not shown in Fig. 4a.

Next, as shown in Fig. 4b, the upper probe and the lower probe are attached to overlap each other by using an adhesive such as an epoxy (not shown).

The conductors 108 of the upper probe (hereinafter, sometimes referred to as upper conductors) and the conductors 98 of the lower probe (hereinafter, sometimes referred to as lower conductors) are formed to be alternately disposed. The one distal portion of each of the conductors 108 of the upper probe is externally protruded more than the corresponding distal portion of each of the conductors 98. The total length of the externally protruded portions of the upper conductors is the same as that of the lower conductors, so that the upper and lower conductors can have the same physical conditions. The one distal portion of each of the conductors 108 and 98 is used as a contact member for directly being in contact with the test positions of the flat panel display device, and the other distal portion is used as a connect member. Although a double-layered probe is described in the embodiment, it can be understood that a three-or-more-layered probe can be manufactured according to a manufacturer's intention.

In addition, the attachment locations of the upper and lower probes can be also selectively determined according to the manufacturer's intention. Therefore, the support plate 100 of the upper probe may be attached and fixed directly on the support plate 90 of the lower probe.

Fig. 5a is perspective view for explaining a probe for testing a flat panel display device in accordance with another embodiment of the present invention and a method of manufacturing the probe, and Fig. 5b is a cross- sectional view of Fig. 5a.

In the probe for testing a flat panel display device in accordance with another embodiment of the present invention and the method of manufacturing the probe, as shown in Figs. 5a and 5b, the following processes are performed on the lower plane of the support plate 90. Namely, like the first embodiment, a process of forming a central groove 112, a first protrusion region 110, and a second protrusion region 114, a process of forming first trenches 116a and second trenches (not shown in Fig. 5a), a process of providing lower conductors 118 (having a predetermined length) passing through the first trenches 116a, the second trenches (not shown), and the central groove 112, thereby both distal portions being protruded externally, and a process of attaching and fixing the lower conductors 118 on the lower plane of the support plate 90 by using an adhesive such as an epoxy are further performed on the lower plane of the support plate.

The conductors 98 on the upper plane of the support plate 90 and the conductors 118 on the lower plane of the support plate 118 are formed to be vertically alternated. The one distal portion of each of the conductors 98 on the upper plane of the support plate is externally protruded more than the corresponding distal portion of each of the conductors 118 on the lower plane of the support plate. The total length of the externally protruded portions of the upper conductors 98 is the same as that of the lower conductors 118.

(Second Embodiment)

The second embodiment is a method of manufacturing a probe by using an MEMS process. Firstly, the common steps in the method of manufacturing the probe will be described before the specific examples of the method of manufacturing the probe is described.

In a sacrifice substrate preparation step, a sacrifice substrate which is constructed with a silicon (Si) wafer or a substrate made up of a ceramic material is prepared. In general, the sacrifice substrate preferably has a

thickness of 400 to 500j-aπ. Next, in a dielectric formation step, trenches are formed on predetermined regions of upper and lower planes of the sacrifice substrate by using a dry etching process. And then, a dielectric is inserted or molded in the trenches, whereby the dielectric is formed on the sacrifice substrate. The dielectric includes a ceramic, an epoxy, or the like. In other words, the epoxy is applied in the trenches, and ceramic plates, which are previously fabricated to have the same size as that of the respective trenches, are inserted and attached in the trenches before the epoxy are cured, whereby the dielectric is formed. Otherwise, the ceramic plates which are previously fabricated to have the same size as that of the respective trenches are inserted, and then an epoxy is applied in gaps between the trenches and the ceramic plates, so that the trenches and the ceramic plates can be attached, whereby the dielectric is formed.

Although the ceramic plate has a shape of a rectangular parallelepiped, it may have a shape of a parallelogram or a step, as shown in Figs. 21 a and 21b.

A process of etching predetermined portions of the upper and lower planes of the sacrifice substrate includes a dicing process and a dry etching process, in which the sacrifice substrate is etched by using a passivation film pattern formed by using a photoresist.

Herein, in the case of using a ceramic as the sacrifice substrate, since the sacrifice substrate itself is a dielectric, the process of forming a dielectric on the upper portion of the sacrifice substrate may be omitted.

Next, in a conductor formation step, patterns having the same shape as that of the conductors are formed on the upper and lower planes of the sacrifice substrate, and then the conductors are formed on the respective locations by using the patterns accurately. The conductors preferably made up of nickel (Ni) or a nickel alloy.

Firstly, patterns having the same shape as those of the conductors are formed at accurate locations on the sacrifice substrate, where the conductors are to be formed, by using a photoresist. And then, by using the patterns, the conductors are formed with an electrolytic plating method. As a result, the probe according to the present invention has an excellent accuracy and reproducibility with respect to the arrangement interval, the locations, the distance between the upper and lower conductors on the upper and lower planes of the dielectric, so that failure ratio of products can be lowered in comparison to the case of manually performing a bonding process.

Since the conductors are formed by a plating process, a seed layer is necessarily formed on the surface of the sacrifice substrate prior to the plating process in order to facilitate the performing of the plating process. Herein, the seed layer may be formed by using a sputtering method. In addition, the seed layer is preferably made up of titanium (Ti) and copper (Cu). The titanium layer has a function of increasing an adhesive property between the sacrifice substrate and the copper layer, and the copper layer functions as a seed layer of the plating in the subsequent plating process.

In addition, the conductors are made up of nickel (Ni) or a nickel alloy.

In a support member formation step, a support member is attached and molded on the sacrifice substrate where the conductors are formed. The support member is made up of an epoxy or a ceramic. In particular, the preferable support member can be obtained by applying the epoxy in advance and attaching a ceramic plate thereon before the epoxy is cured.

In other words, the support member patterns are formed by using a photoresist, and then a support material is applied in the support member pattern, whereby the support member is formed. Finally, in a finishing step, the remaining portions of the sacrifice substrate are removed by using a wet etching process, whereby the probe is obtained.

On the other hand, in the case of using a hard material such as a ceramic as the sacrifice substrate, a method of manufacturing a probe comprises a groove formation step of forming a groove having a predetermined depth at a predetermined portion of upper and lower planes of a single sacrifice substrate made up of a dielectric material, which is formed to have a predetermined thickness by using a polishing process; a dielectric- formation-supplement means formation step of forming dielectric-formation- supplement means by forming a passivation film pattern to open the groove on the sacrifice substrate and burying a metal material in the groove, wherein the metal material is a material which can be selectively removed by using a wet etching process; a conductor formation step of forming passivation film patterns having the same shape as the conductors on the sacrifice substrate and then forming conductors at accurate locations by using the patterns; a support member formation step of forming a support member on the upper and lower planes of the sacrifice substrate where the conductors are formed; and a step of removing the dielectric-formation-supplement means out of the sacrifice substrate. Herein, the hard material includes a ceramic, a glass, and the like. Now, a construction of a probe for testing a flat panel display device and a method of the probe will be described with reference to the accompanying drawings.

(Embodiment 2-1)

Figs. 6a to 6p are cross-sectional views for explaining a method of manufacturing a probe for testing a flat panel display device according to another embodiment. In the method of manufacturing the probe in accordance with the embodiment described with reference to the Figs. 6a to 6p, conductors and align keys are provided on an upper plane of a sacrifice substrate in order to facilitate processes performed on a lower pane thereof by using the align keys. As shown in Fig. 6a, a seed layer 126 is formed to have a predetermined thickness on the sacrifice substrate 120 made up of silicon, or the like, by using a deposition process such a sputtering process, and then a first photoresist 128 functioning as a passivation film is coated to have a predetermined thickness on the seed layer 126.

The seed layer 126 is constructed with a titanium layer 122 having a thickness of 500 A and a copper layer 124 having a thickness of 5, 000 A . The copper layer 124 substantially functions as a seed layer 126 in the subsequent plating process. The titanium layer 122 is provided in order to improve an adhesive property of the sacrifice substrate 120 and the copper layer 124. Next, as shown in Fig. 6b, first photoresist patterns 129 are formed to define predetermined regions for forming the conductors and the align keys in the subsequent process. Each of the conductors is a contact member of being directly in contact with a flat panel display device which is to be tested.

The first photoresist patterns 129 can be formed by exposing a first photoresist 128, which is formed on the sacrifice substrate 120, by using a mask on which predetermined circuit patterns are designed to form the conductors and the align keys, and then developing thereof.

Subsequently, as shown in Fig. 6c, a conductive film 131 is formed by depositing a conductive material such as nickel (Ni) and a nickel alloy (Ni-Co, Ni-W-Co) on the sacrifice substrate 120, where the first photoresist patterns

129 are formed, by using a plating process. And then, the upper plane of the sacrifice substrate 120 is planarized by using a planarization process.

The planarization process is performed by using a CMP (Chemical Mechanical Polishing) method and a grinding method, etc. The copper layer 124 in the seed layer 126 during the plating process for forming the conductive film 131 functions as a seed for the plating material.

In particular, in a case where the conductive film 131 is formed only inside the opened portions of the first photoresist patterns 129 on the course of an ideal plating process for forming the conductive film 131 , the planarization process may be omitted.

In addition, in a case where a method such as a PVD (Physical Vapor Deposition) method and a CVD (Chemical Vapor Deposition) other than the plating process is used to form the conductive film 131, the previously- performed process of forming the seed layer 126 may be omitted. Next, as shown in Fig. 6d, some portions of the copper layer 124 are exposed by removing the first photoresist patterns 129, whereby the conductors and the align keys 132a and 132b are formed. The first photoresist patterns can be removed by a method such as a wet etching process or a dry etching process using chemicals. Subsequently, as shown in Fig. 6e, the seed layer 126, which is constructed with the titanium layer 122 and the copper layer 124 exposed by removing the first photoresist patterns 129, are removed by using the conductors 130 and the align keys 132a and 132b as the mask in such a wet etching process using chemical, whereby the conductors 130 and the align keys 132a and 132b are completely externally exposed.

Next, as shown in Fig. 6f, a certain amount of second photoresist 134 is coated on the sacrifice substrate 120, where the conductors 130 and the align keys 132a and 132b are completely externally exposed.

Herein, while the sacrifice substrate 120 which is mounted on the spin chuck is being rotated, the second photoresist 134 are sprayed on the sacrifice substrate 120 through a nozzle, whereby a certain amount of the second photoresist 134 can be coated.

Subsequently, as shown in Fig. 6g, a mask where predetermined circuit patterns are provided is located on the sacrifice substrate 120 on which the second photoresist 134 is coated, and then, it is exposed and developed, whereby the second photoresist patterns 136 for completely opening the central portions of the conductors 130 and the align keys 132a and the 132b can be formed.

Next, as shown in Fig. 6h, a support plate 138 is formed by closing the central portions of the conductors 130, which is completely opened with the second photoresist patterns 136, with a dielectric material such as an epoxy.

Herein, the epoxy used as the support plate 138 may be formed by using a printing method, or the like.

Subsequently, as shown in Fig. 6i, the upper plane of the sacrifice substrate 120, where the central portions of the conductors are completely closed with the support plate 138 made up of a dielectric material such as an epoxy, is planarized by a grinding process.

Herein the grinding process is performed in order to facilitate the subsequent grinding process performed on the rear plane of the sacrifice substrate 120.

Next, as shown in Fig. 6j, the sacrifice substrate 120 are faced down, and the rear plane of the sacrifice substrate 120 is grinded to have a predetermined thickness, whereby the etching depth of the sacrifice substrate 120 is adjusted in a low level at the subsequent trench formation process. Subsequently, as shown in Fig. 6k, third photoresist 140 having a predetermined thickness is coated on the rear plane of the sacrifice substrate 120, which is grinded to have a predetermined thickness.

Herein, the third photoresist 140 is coated with the same method as that of the first and second photoresists 128 and 134. Next, as shown in Fig. 61, third photoresist patterns 142 for opening a central portion of the rear plane of the sacrifice substrate are formed by exposing the third photoresist 140 by using a mask on which certain circuit patterns are provided, and then developing thereof.

Subsequently, as shown in Fig. 6m, an etching process is performed by using the third photoresist patterns 142 as a mask to completely etch the seed layer 126, whereby trenches 144 for opening sacrifice substrate 120 are formed.

Herein, the etching process is a dry etching process using a mixed gas in which SF₆, C₄F₈ and O₂ gases are mixed with a certain ratio. More specifically, the etching process is performed by using the so- called Bosh process, which is an RIE (Reactive Ion Etching) process out of deep trench etching methods.

Next, as shown in Fig. 6n, a certain amount of adhesive 146, an epoxy, is applied in the trenches 144, which are formed on the rear plane of the sacrifice substrate 120, and then a support plate 148, which is constructed with a predetermined size of a ceramic plate, is pressured and inserted into the trenches 144, whereby the support plate 148 is buried and attached in the trenches 144.

Next, as shown in Fig. 6o, the support plate 148, the dielectric plate 130, and the conductors 138 are externally opened by removing the second photoresist patterns 136 and the third photoresist patterns 142 of Fig. 6n.

Herein, the second photoresist patterns 136 and the third photoresist patterns 142 are removed by a dry etching process or a wet etching process using chemicals. Finally, as shown in Fig. 6p, both of the distal portions of each of the conductors 138 are external exposed by performing a wet etching process using chemicals on the sacrifice substrate 120. The central portion of the lower plane of each of the conductors 138 is insulated with the dielectric plate 130, and the central portion of the upper plane of each of the conductors 138 are supported by the support plate 148, whereby the probe is obtained. Herein, the align keys 132a and 132b and the remaining seed layer 126 shown in Fig. 6o are removed.

(Embodiment 2-2) Figs. 7a to 7i are cross-sectional views for explaining a method of manufacturing a probe for testing a flat panel display device according to another embodiment.

In the method of manufacturing the probe in accordance with the embodiment, as shown in Fig. 7a, a seed layer 206 is formed to have a predetermined thickness on the sacrifice substrate 200 made up of silicon, or the like, by using a deposition process such a sputtering process, and then a first photoresist 208 functioning as a passivation film is coated to have a predetermined thickness on the seed layer 206.

The seed layer 206 is constructed with a titanium layer 202 and a copper layer 204. The copper layer 204 substantially functions as a seed in the subsequent plating process. The titanium layer 202 is provided in order to improve an adhesive property of the sacrifice substrate 200 and the copper layer 204.

Next, as shown in Fig. 7b, first photoresist patterns 210 are formed to define predetermined regions for forming the conductors in the subsequent process.

The first photoresist patterns 210 can be formed by locating a mask, on which predetermined circuit patterns are designed to form the conductors, on a first photoresist 208 of Fig. 7a, which is formed on the sacrifice substrate 200, and then exposing and developing thereof. Subsequently, as shown in Fig. 7c, a conductive film 212 used as a contact member is formed by depositing a conductive material such as nickel (Ni) and a nickel alloy (Ni-Co, Ni-W-Co) on the sacrifice substrate 200, where the first photoresist patterns 210 are formed, by using a plating process. And then, the upper plane of the sacrifice substrate 200 is planarized by using a planarization process.

The planarization process is performed by using a CMP (Chemical Mechanical Polishing) method and a grinding method, etc. The copper layer 204 during the plating process for forming the conductive film 212 functions as a seed for the plating material. In particular, in a case where the conductive film 212 is formed only inside the opened portions of the first photoresist patterns 210 on the course. of an ideal plating process for forming the conductive film 212, the planarization process may be omitted. In addition, in a case where a method such as a PVD (Physical Vapor Deposition) method and a CVD (Chemical Vapor Deposition) other than the plating process is used to form the conductive film 212, the previously-performed process of forming the seed layer 206 may be omitted.

Next, as shown in Fig. 7d, after the second photoresist patterns 210 are removed, the seed layer 206, which are constructed with a titanium layer 202 and a copper layer 204 being remaining on the lower portion of the second photoresist patterns 210 of Fig. 7c, are removed by performing an etching process using the conductive film 212, which are formed in the opened portion of the second photoresist patterns 210 of Fig. 7c, as a self-aligned mask.

Herein, the second photoresist patterns 210 can be removed by using a wet etching method or a dry etching method, and the seed layer 206 can also be removed by using a wet etching method or a dry etching method.

Subsequently, as shown in Fig. 7e, a certain amount of the third photoresist 214 is coated on the sacrifice substrate 200 where the second photoresist patterns 210 of Fig. 7c are removed. Herein, the third photoresist 214 can be coated by using a general photoresist spin-coating method, or the like.

Next, as shown in Fig. 7f, third photoresist patterns 222 for opening a central portion of the conductive film 212, which is used as a contact member, are formed by locating a mask, on which certain circuit patterns are provided, on the sacrifice substrate 200 where the third photoresist 214 is coated, and then exposing and developing thereof.

Subsequently, as shown in Fig. 7g, a certain amount of adhesive 216 such as an epoxy is applied in the opened portions, which are opened by using the third photoresist patterns 222, and then a support plate 218, which is made up of a dielectric material such as a ceramic having a predetermined size, is inserted and attached in the opened portion of the third photoresist patterns 222.

Next, as shown in Fig. 7h, the conductors constructed with the support plate 218 and the conductive film 212 are externally opened by removing the third photoresist patterns 222 of Fig. 7g.

Finally, as shown in Fig. 7i, the sacrifice substrate 200 of Fig. 7h, where the support plate 218 and the conductive film 212 are externally opened, and the seed layer 206 on the lower portion of the conductive film 212 are removed by using a wet etching process, or the like, whereby the probe comprising the conductive film is completed. Herein, it is preferable that the sacrifice substrate 200 and the seed layer 206, which is constructed with the copper layer 202 and the titanium layer 204, are sequentially removed by a series of wet etching processes using different chemicals. In addition, a process of attaching a dielectric material such as an epoxy on the rear plane of the conductive film 212 of the completed probe is additionally preformed.

(Embodiment 2-3) Figs. 8a to 8t are cross-sectional views for explaining a method of manufacturing a probe for testing a flat panel display device according to another embodiment.

In the method of manufacturing the probe in accordance with the embodiment described, as shown in Fig. 8a, a first photoresist 252 is coated on a sacrifice substrate 250, which is made up of silicon, or the like.

Herein, the first photoresist 252 can be coated by using a well-known photoresist spin-coating method, or the like.

Next, as shown in Fig. 8b, first photoresist patterns 254 are formed to define align keys and to shape contact members by performing a subsequent process in the sacrifice substrate 250.

Herein, the first photoresist patterns 254. are formed by aligning a predetermined mask on the sacrifice substrate 250, and then exposing and developing thereof.

Subsequently, as shown in Fig. 8c, an etching process is performed by using the first photoresist patterns 254 on the sacrifice substrate 250 as a mask, whereby first trenches 256a and 256b and second trenches 258, which are used to form the align key and contact members in the sacrifice substrate 250, are formed.

Herein, the process of forming the first trenches 256a and 256b and the second trenches 258 are performed by a dry etching process using a reactive gas.

Next, as shown in Fig. 8d, after the first photoresist pattern 254 on the sacrifice substrate 250, where the first trenches 256a and 256b and the second trenches 258 are formed, are removed, a seed layer 260 having a predetermined thickness are formed by using a deposition process such as a sputtering process.

The seed layer 260 is constructed with a titanium layer 261 having a thickness of 500 A and a copper layer 262 having a thickness of 5,000 A . The copper layer 262 substantially functions as a seed layer 260 in the subsequent plating process. The titanium layer 261 is provided in order to improve an adhesive property of the sacrifice substrate 250 and the copper layer 262.

Next, as shown in Fig. 8e, a certain amount of second photoresist 264 is coated on the sacrifice substrate 250, where the seed layer 260 is formed. Herein, the second photoresist 264 can be coated by using a well- known photoresist spin-coating method, or the like.

Subsequently, as shown in Fig. 8f, the second photoresist 264, where the sacrifice substrate 250 is formed, are exposed and developed, whereby second photoresist patterns 265 are formed to define regions where first trenches 256a and 256b and second trenches 258 are to be formed. Subsequently, as shown in Fig. 8g, a conductive film 266 is formed by depositing a conductive material such as nickel (Ni) and a nickel alloy (Ni-Co, Ni-W-Co) on the sacrifice substrate 250, where the second photoresist patterns 265 are formed, by using a plating process. Herein, the copper layer 262 in the seed layer 260 during the plating process for forming the conductive film 266 functions as a seed for the plating material.

Next, as shown in Fig. 8h, the upper plane of the sacrifice substrate

250, where the conductive film 266 is formed, is planarized. The planarization process of the upper plane of the sacrifice substrate 250 is performed by using a CMP (Chemical Mechanical Polishing) method and a grinding method, etc.

In addition, in a case where the conductive film 266 is formed only inside the opened portions of the second photoresist patterns 265 on the course of an ideal plating process for forming the conductive film 266, the planarization process may be omitted.

Next, as shown in Fig. 8i, a certain amount of third photoresist-268 is coated on the sacrifice substrate 250, where the planarization process is completed. Herein, the third photoresist 268 can be coated by using a well-known photoresist spin-coating method, or the like.

Next, as shown in Fig. 8j, third photoresist patterns 270 for opening a central portion of the conductive film 266, which is formed on the sacrifice substrate 250, is formed. Herein, the third photoresist patterns 270 may be formed by an exposing process using a mask and a developing process.

Next, as shown in Fig. 8k, a dielectric plate 272 is formed by burying a dielectric material such as an epoxy in the opened portion, which is opened by the third photoresist patterns 270. Subsequently, as shown in Fig. 81, the upper plane of the sacrifice substrate 250, where the dielectric plate 272 is formed, is planarized. The planarization is performed by using a CMP (Chemical Mechanical Polishing) method and a grinding method, etc.

Next, as shown in Fig. 8m, the sacrifice substrate 250 is faced down, and the rear plane of the sacrifice substrate 250 is grinded to have a predetermined thickness. The grinding process is performed in order to adjust the etching depth of the sacrifice substrate 250 in a low level at the subsequent trench formation process.

Subsequently, as shown in Fig. 8n, fourth photoresist 274 having a predetermined thickness is coated on the rear plane of the sacrifice substrate 250, which the grinding process is performed. The fourth photoresist 274 may be formed by using a well-known photoresist coating method.

Next, as shown in Fig. 8o, fourth photoresist patterns 276 for opening a central portion of the rear plane of the sacrifice substrate 250, which is a central portion of the sacrifice substrate 250, are formed by exposing the fourth photoresist 274, which is formed on the sacrifice substrate 250, and then developing thereof.

Subsequently, as shown in Fig. 8p, an etching process is performed by using the fourth photoresist patterns 276 as a mask, whereby third trenches 278 for opening the conductive film 266 are formed on the rear plane of the sacrifice substrate 250. Herein, the etching process is a dry etching process using a mixed gas in which SF₆, C₄F₈ and O₂ gases are mixed with a certain ratio.

More specifically, the etching process is performed by using the so- called Bosh process, which is an RIE (Reactive Ion Etching) process out of deep trench etching methods.

Subsequently, as shown in Fig. 8q, a certain amount of adhesive 280 such as an epoxy is applied in the third trenches 278 which are formed on the rear plane of the sacrifice substrate 250, and then a support plate 282, which is made up of a ceramic having a predetermined size, is pressured and inserted into the third trenches 278, whereby the support plate 282 is buried and attached in the third trenches 278.

Next, as shown in Fig. 8r, the rear plane of the sacrifice substrate 250, where the support plate 282 is buried in the third trenches 278, is planarized with a planarization process.

The planarization process is performed by using a CMP (Chemical Mechanical Polishing) method or a grinding method.

Subsequently, as shown in Fig. 8s, the third photoresist patterns 270, the fourth photoresist patterns 276, and the seed layer 260 are removed. Finally, as shown in Fig. 8t, the sacrifice substrate 250 is removed by using an etching process, whereby the probe comprising the support member 282, which is attached on the upper portion of the conductors 284 with an adhesive 280, and the dielectric plate 272, which is provided on the lower portion of the conductors 284, is completed. Fig. 9 is a perspective view for explaining a method of manufacturing a probe for testing a flat panel display device according to another embodiment.

In the method of manufacturing the probe in accordance with the embodiment, a first sacrifice substrate 280 and a second sacrifice substrate 282 where the conductors 130 of Fig. 6o are externally completely opened are prepared, or a first sacrifice substrate 280 and a second sacrifice substrate 282 where the conductors 284 of Fig. 8t are externally completely opened are prepared.

Herein, the align keys 288, the dielectric plate 284, and the conductors 286 are externally exposed on the first sacrifice substrate 280 and the second sacrifice substrate 282.

Next, the first sacrifice substrate 280 and the second sacrifice substrate 282 are attached to each other by matching the conductors 284 of the first sacrifice substrate 280 with the conductors 284 of the second sacrifice substrate 282 with reference to the align keys 288 or with operator's eyes, and then attaching each other with an adhesive.

The plurality of conductors 286 formed on the second sacrifice substrate 282 are vertically disposed in gap spaces between the plurality of adjacent conductors 286 formed on the first sacrifice substrate 280, whereby each of the conductors 286 of the second sacrifice substrate 282 is vertically disposed between the adjacent conductors 286 of the first sacrifice substrate 280, and the distal portion of each of the conductors 286 of the second sacrifice substrate 280 is horizontally protruded more than the distal portion of each of the conductors 286 of the first sacrifice substrate 280 in which the conductors are formed in a multi-layered structure. After that, the first and second sacrifice substrates 280 and 282 are removed by using the same wet etching process as the aforementioned embodiments, whereby the multi-layered probe, where the probes are stacked, can be manufactured. Although a double-layered probe is described in the embodiment, it can be understood that a three-or-more-layered probe can be manufactured according to a manufacturer's intention.

Fig. 10a is a perspective view for explaining a probe according to another embodiment, and Fig. 10b is a cross-sectional view thereof. As shown in Figs. 10a and 10b, the probe according to the embodiment of the present invention is constructed with a double-layered structure, in which a first probe 300 and a second probe 310 are stacked, by attaching dielectric plates 306 and 316, which are formed on the first probe 300 and the second probe 310, with an adhering means such as an adhesive. In the first probe 300 and the second probe 310, a plurality of conductors 302 and 312 are attached separately in predetermined intervals on lower portions of support plates 308 and 3 18 which are made up of a ceramic, or the like, respectively, and the dielectric plates 306 and 316 which are made up of a dielectric material such as an epoxy 304 and 314 are attached on lower central portions of the conductors 302 and 312, respectively.

More specifically, each of the conductors 312 of the second probe 310 are vertically disposed in a gap space between adjacent conductors 302 of the first probe 300, whereby the interval between the conductors 302 and the conductors 3 12 of the multi-layered probe are adjusted to be very short. In the stacked structure, the distal portion of each of the conductors 3 12 of the second probe 3 10 is protruded in the horizontal direction more than that of each of the conductors 302 of the first probe 300.

In addition, in another embodiment, support plates 308 and 318 which are formed on the first probe 300 and the second probe 310, respectively, are attached to each other by an adhering means such as an adhesive, whereby a double-layered structure, in which the first probe 300 and the second probe

310 are stacked, may be manufactured.

In addition, in still another embodiment, dielectric plates 306 and 316 of the first probe 300 or the second probe 310 and support plates 308 and 318 of the first probe 300 or the second probe 310 are attached to each other by an adhering means such as an adhesive, whereby a double-layered structure, in which the first probe 300 and the second probe 310 are stacked, may be manufactured.

Therefore, the multi-layered probe, in which the first and second probes 300 and 310 are provided in a stacked structure, are incorporated into a probe assembly (not shown) to verify the normality of the flat panel display device which are obtained through a series of production processes.

The one distal portion of each of the conductors 302 and 3 12 of the probe is in contact with a test position of the flat panel display device, that is, a pad electrode, and the other distal portion thereof are connected to a TCP

(Tape Carrier Package) which is connected to a drive chip, whereby the normality of the flat panel display device is verified.

(Embodiment 2-4) Fig. 11 is a perspective view illustrating a probe for testing a flat panel display device according to another embodiment. As shown in Fig. 11 , the probe comprises a plurality of unit conductors 320 each of which has a beam element 322 having a shape of a bar, an inspection tip 324a provided at one end of the beam element 322 in an integrated manner, and a connection tip 324b provided at the other end of the beam element 322 in an integrated manner. The plurality of unit conductors are disposed separately in a predetermined interval.

Herein, the beam element 322 and tips 324a and 324b are made up of a metal material having excellent conductivity and elasticity such as nickel (Ni) and a nickel alloy (Ni-Co, Ni-W-Co), and the distal portion of each of the tips 324a and 324b are subjected to a rounding process in order to suppress occurrence of particles.

In addition, a transparent thin film 342 having a predetermined size, which is made up of a transparent material such as an epoxy and a parylene, is attached on the plurality of the unit conductors 320 by using a pressing process and a heating process.

Therefore, the probe sheet, where the plurality of unit conductors 320 are attached with the thin film 342, are incorporated into a probe assembly to verify the normality of the flat panel display device which are obtained through a series of production processes.

The connection tips 324b of the probe sheet are connected to a TCP (Tape Carrier Package), which is connected to a drive chip, and the inspection tips 324a of the probe sheet are repeatedly in contact with a test position of the flat panel display device, that is, a pad electrode, whereby the normality of the flat panel display device is verified. In addition, in another embodiment, the connection tip 324b of the beam element 322 of each of the unit contact members may be omitted. Each of the unit conductors 320, in which the connection tip 324b is omitted, may be connected to TCP (Tape Carrier Package) through ACF (Anisotropic Conductive Film).

Figs. 12a to 12i are cross-sectional views for explaining a method of manufacturing a probe for testing a flat panel display device shown in Fig. 11.

Now, the method of manufacturing the probe for testing a flat panel display device according to the present invention with reference to Fig. 12. Firstly, first photoresist patterns 332 for forming first trenches 334a and second trenches 334b in the subsequent processes are formed on a sacrifice substrate 330 which is made up of silicon having certain directionality such as (1, 0, 0).

The first photoresist patterns 332 are constructed with a photoresist having a high photo-sensitivity. The first photoresist patterns 332 are formed by using a spin coating process of spin-coating the photoresist on the front plane of the substrate 330 with a thickness of about 2 im, and then performing an exposing process and a developing process.

Next, as shown in Fig. 12b, a first etching process is performed by using the first photoresist patterns 332, which are formed on the sacrifice substrate 330, as an etching mask, whereby the first trenches 334a and the second trenches 334b, in which the inspection tips 324a and the connection tips 324b are to be formed, respectively, are formed.

The first etching process of forming the trenches 334a and 334b may be a wet etching process using a chemical in which potassium hydroxide (KOH) and deionized water are mixed with a predetermined ratio. The sacrifice substrate 330 having a certain directionality are anisotropically etched by the wet etching process using the chemical, whereby the first trenches 334a and the second trenches 334b having a shape of a truncated pyramid or a truncated cone are formed.

Subsequently, as shown in Fig. 12c, a second etching process is preformed by using the first photoresist patterns 332 as an etching mask, whereby the first trenches 334a and the second trenches 334b having a shape of a truncated pyramid or a truncated cone have deep depths and the bottoms of the trenches 334a and 334b are subjected to a rounding process.

Herein, the second etching process is a dry etching process using a mixed gas in which SF₆, C₄F₈ and O₂ gases are mixed with a certain ratio.

More specifically, the second etching process is performed by using the so-called Bosh process, which is an RIE (Reactive Ion Etching) process out of deep trench etching methods.

Next, the first trenches 334a and the second trenches 334b having a shape of a truncated pyramid or a truncated cone, which are previously subjected to the first etching process, have deep depths of 30JMΠ to 500j-an and the bottoms of the trenches 334a and 334b are subjected to a rounding process. Subsequently, as shown in Fig. 12d, after the first photoresist patterns

332 of Fig. 12c are removed by using a wet etching process, a copper layer functioning as a seed layer 336 in the subsequent process are formed to have a thickness of 2,000 A to 3,000 A on the sacrifice substrate 330, which is previously subjected to the second etching process. Herein, the copper layer may be formed by using a physical deposition method such as a sputtering process.

Next, as shown in Fig. 12e, second photoresist patterns 338 for opening regions, where the beam elements 332 are to be formed in the subsequent process, are formed. The second photoresist patterns 338, which are constructed with a photoresist having a high photo-sensitivity like the first photoresist patterns 332, are formed by using a spin coating process, an exposing process, and a developing process.

Subsequently, as shown in Fig. 12f, a metallic film having a predetermined thickness is made up of a metal material having excellent conductivity and elasticity such as nickel (Ni) and a nickel alloy (Ni-Co, Ni- W-Co) by using a plating process, and then the beam element 340 is formed by planarizing the upper plane of the sacrifice substrate 330 with a CMP (Chemical Mechanical Polishing) method, an etchback method, a grinding method, and the like.

However, the process of forming the seed layer 336 used in the plating process of the previously-performed processes may be omitted, and a metallic film made up of Ni, Ni-Co, Ni-W-Co, or the like are formed to have a predetermined thickness by using a CVD (Chemical Vapor Deposition) method, a PVD (Physical Vapor Deposition) method, or the like, whereby the beam element 340 may be formed.

In addition, after the planarization process is performed, it is preferable that organic materials and particles on the sacrifice substrate 330 are removed by performing an additional cleaning process. Next, as shown in Fig. 12g, after the second photoresist patterns 338 of Fig. 12f are removed by using a wet etching process, the sacrifice substrate where the second photoresist patterns 338 are removed are sliced.

Subsequently, as shown in Fig. 12h, a thin film 342 which is made up of a transparent material such as an epoxy or parylene is disposed on the sliced sacrifice substrate 330, and then the thin film 342 are attached on the upper planes of the beam elements 340 which are formed on the sacrifice substrate 330 by using a pressing process and a heating process.

Herein, the upper portion of the beam element 340, which is constructed with a metallic film formed on the sacrifice substrate 330 by the pressing and heating of the thin film 342, are inserted and attached into the thin film 342.

Finally, as shown in Fig. 12i, the sacrifice substrate 330 are removed by a wet etching process using chemicals, whereby a probe sheet comprising the bar-like beam element 340, of which the one end and the other end are provided with a contact tip 324a and a connection tip 324b, are completed.

(Embodiment 2-5)

In the first embodiment of a method of manufacturing a probe for testing a flat panel display device according to the present invention, as shown in Fig. 13a (a), a silicon (Si) wafer of which both planes are polished to have a predetermined thickness is used as a sacrifice substrate 400. The sacrifice substrate 400 has a thickness of about 400 to 500^111 by using a grinding process or a polishing process.

Next, as shown in Fig. 13a(b), first photo resist patterns 402a and 402b corresponding to a shape of the probe are formed on both planes of the sacrifice substrate 400 by using photolithography process. Herein, since the patterns 402a and 402b are formed by using the photolithography process, they can be accurately formed on the desired locations. Therefore, errors can be further removed in comparison to the manual operation. That is, a plurality of conductors having the same dimension can be formed in the same interval on the sacrifice substrate 400, and in particular, the conductors 412a formed on the upper plane A of the sacrifice substrate 400 and the conductors 412b formed on the lower B of the sacrifice substrate 400 can be formed at the accurate locations to be alternated from each other. Therefore, as shown in Fig. 13a (b), the first photoresist patterns 402a and the 402b, which are formed on the upper and lower planes A and B of the sacrifice substrate 400, are formed in an asymmetrical structure where the later-formed probes are formed in an alternate manner.

Subsequently, as shown in Fig. 13a (c), regions on the upper plane A of the sacrifice substrate 400, which are opened by using the first photoresist patterns 402a, are etched by using an anisotropic dry etching process, whereby grooves 404 having a shape of a probe are formed on the upper plane A of the sacrifice substrate 400.

Next, as shown in Fig. 13a (d), the lower plane B of the sacrifice substrate 400 is also etched by using the same process as that in the upper plane, whereby grooves 406 having a shape of a probe are formed. Herein, the grooves 406 formed on the lower plane B of the sacrifice substrate 400 and the grooves 404 formed on the upper plane A of the sacrifice substrate 400 have an asymmetrical structure where the grooves 404 and 406 are alternated from each other. In addition, the etching depths of the grooves 404 and 406 formed on the upper and lower planes A and B of the sacrifice substrate 400, respectively, are in a range of 70 to 100j--m in consideration of the depths which are to be removed in the subsequent planarization process, whereby the etching depths is relatively deeper that the depth of to-be-obtained conductors, that is, 60 μm

Subsequently, as shown in Fig. 13a (e), the first photoresist patterns 402a and 402b, which are remaining on the upper and lower planes A and B of the sacrifice substrate 400, are removed with a wet etching process using a chemical solvent. Next, as shown in Fig. 13a (f), seed layers 408a and 408b are formed to perform a plating process for forming conductors on both of the planes of the sacrifice substrate 400. Herein, the seed layer are constructed with a titanium layer having a thickness of 500 A and a copper layer having a thickness of 5,000 A . The copper layer functions as a seed layer of the plating in the subsequent plating process, and the titanium layer has a function of increasing an adhesive property between the sacrifice substrate 400 and the copper layer.

Subsequently, as shown in Fig. 13a (g), the second photoresist patterns 410a and 410b are formed by using a photolithography process in order to open predetermined portions on both planes A and B of the sacrifice substrate 450.

Next, as shown in Fig. 13b (h), conductors 412a and 412b are formed on both planes A and B of the sacrifice substrate 400, which are opened by using the second photoresist patterns 410a and 410b, by using an electrolytic plating process. That is, the conductors 412a and 412b are formed on the sacrifice substrate 400 by depositing a conductive material such as nickel (Ni) or a nickel alloy (Ni-Co, Ni-W-Co) with an electrolytic plating method by using the second photoresist patterns 410a and 410b as a mold.

Figs. 13b (i) to (p) illustrate longitudinal views and transverse view in order to clearly explain the present invention.

As shown in Fig. 13 (i), portions which are protruded form the second photoresist patterns 410a and410b and both planes A and B of the sacrifice substrate 400 are removed, whereby both planes A and B of the sacrifice substrate 400 are planarized. Herein, the planarization process is performed by using a CMP (Chemical Mechanical Polishing) method, grinding method, a lapping method, and a polishing method, etc. However, in a case where the conductors 412a and 412b are formed only inside the grooves 404 and 406 having a shape of a probe, which are opened by using the second photoresist patterns 410a and410b on the course of an ideal plating process for forming the conductors 412a and 412b, the planarization process may be omitted. In addition, after the conductors 412a and 412b are planarized, a gold plating layer is formed on the upper plane thereof by a gold-plating process, whereby the conductivities of the conductors can be improved.

In addition, in a case where a method such as a PVD (Physical Vapor Deposition) method and a CVD (Chemical Vapor Deposition) other than the plating process is used to form the conductors 412a and 412b, the previously- performed process of forming the seed layers 408a and 408b is not necessary.

Next, as shown in Fig. 13b (j), the third photoresist patterns 414 are formed by using a photolithography process in order to open a central portion on the upper plane A of the sacrifice substrate 400. Next, as shown in Fig. 13b (k), the regions, which are opened by using the third photoresist patterns 414, are etched by using an isotropic dry etching process. Herein, the etching is performed up to a half of the depth of the entire sacrifice layer including the portion where the conductors 412a are formed, whereby the first trenches 416 are formed.

Next, as shown in Fig. 13c (1), after the thermo-setting epoxy 420, which is used as a dielectric, is applied in the first trenches 416, before the epoxy 420 is cured, a ceramic plate 418 used for supporting is adhered on the upper portion thereof. Sine the ceramic plate 418 is made up of a hard material, the ceramic plate have a function of a support member for preventing deformation of the probe against a certain external force which is exerted on the probe as well as a function of maintaining the shape of the probe, which is to be obtained,

When the process of forming the epoxy 420 and the ceramic plate 418 are completed, the processes on the upper plane A of the sacrifice substrate 400 are completed.

Now, the remaining processes on the lower plane B of the sacrifice substrate 400 will be described.

Next, as shown in Fig. 13c (m), the fourth photoresist patterns 424 are formed by using a photolithography process in order to open a central portion on the lower plane B of the sacrifice substrate 400.

Next, as shown in Fig. 13c (n), the regions, which are opened by using the fourth photoresist patterns 424, are etched by using an isotropic dry etching process. Herein, the etching is performed up to a half of the depth of the entire sacrifice layer including the portion where the conductors 412b are formed, whereby the second trenches 426 for exposing the epoxy 420 are formed.

Subsequently, as shown in Fig. 13d (o), a thermo-setting epoxy 428, which is used as a dielectric, is applied in the second trenches 426. Next, as not shown in the figure, a ceramic plate made up of a hard material is also attached on the upper portion of the epoxy 428 in the lower plane B of the sacrifice substrate 400 similar to the upper plane A thereof.

In addition, as shown in Fig. 13d (p), the photoresist patterns 414 and 424 on the upper and lower planes of the sacrifice substrate 400 are simultaneously removed by using predetermined chemicals, and then the remaining sacrifice substrate 400 is selectively etched by using chemicals such as which potassium hydroxide (KOH) and TMAH (Tetra-methyl ammonium hydroxide).

As a result, the probe for testing a flat panel display device, where the upper and lower conductors 412a and 412b are disposed in an alternate manner, is completed in accordance with the MEMS process.

On the other ^"hand, the isotropic dry etching process for forming the trenches 416 and 426 shown in Fig. 13b (k) and (n), is a dry etching process using a mixed gas in which SF₆, C₄F₈ and O₂ gases are mixed with a certain ratio. More specifically, the etching process is performed by using the so- called Bosh process, which is an RIE (Reactive Ion Etching) process out of deep trench etching methods.

After all the processes performed on the upper and the lower planes A and B of the sacrifice substrate 400 are completed, the sacrifice substrate 400 is cut so that the plurality of conductors formed o the upper plane of the sacrifice substrate 400 can be divided into probe groups in a predetermined unit including a predetermined number of conductors.

In other words, as shown in Fig. 25, the sacrifice substrate 400 is cut so that each of the conductors groups can include 12 conductors, and then, the probe is formed.

In particular, the one distal portion of each of the conductors formed on the upper plane A is formed to be protruded externally more that that of each of the conductors formed on the lower plane B, and the lengths of the externally-protruded portions are all the same. Therefore, the probe manufactured by the aforementioned method has an advantage of facilitating the probing operation since the same pressures are exerted on the upper and lower probes.

The probe manufactured in accordance with the aforementioned method has the shape shown in Fig. 14. Fig. 14 is a perspective view illustrating a probe using a single sacrifice substrate, which are manufactured by the process shown in Fig. 13.

As shown in Fig. 14, conductors 360a and 360b are disposed in corresponding predetermined intervals in parallel on upper and lower planes of the sacrifice substrate, respectively. The conductors 360a and 360b are formed by burying a conductive material in the first trenches, which are formed on the upper and lower planes of the silicon sacrifice substrate by using a photolithography process and an etching process. In addition, conductive layers, each of which is a thin layer made up of a material having a higher electrical conductivity than that of the conductors, are provided on one plane of each of the conductors 360a and 360b in order to improve the conductivities of the conductors 360a and 360b.

In addition, dielectrics 362a and 362b are formed on the upper and lower portions of the probe. The dielectrics 362a and 362b are formed by applying a dielectric material in the second trenches which are formed on both planes of the sacrifice substrate by an etching process. Herein, the dielectric material is preferably an epoxy.

Finally, a support member 364 is provided in the probe. The support member 364 is formed on at least one of outer planes of the dielectrics 362a and 362b. The support member 364 is preferably made up of a hard material. The support member is preferably formed by attaching a ceramic plate on the dielectrics 362a and 362b.

(Embodiment 2-6)

As shown in Fig. 15a (a), a planar silicon (Si) wafer, of which both planes are polished, is prepared as a sacrifice substrate 450. The sacrifice substrate 450 has a depth of 400 to 500 m which is obtained by using a grinding process or a polishing process.

Subsequently, as shown in Fig. 15a (b), a first seed layer 452 is formed on the entire upper plane A of the sacrifice substrate 450 by using a sputtering process. Herein, the first seed layer 452 is constructed with a titanium layer having a thickness of 500 A and a copper layer having a thickness of 5,000 A .

The copper layer substantially functions as a seed layer in the subsequent plating process. The titanium layer is provided in order to improve an adhesive property of the sacrifice substrate 450 and the copper layer. Next, as shown in Fig. 15a (c), the first photoresist patterns 454 are formed by using a photolithography process in order to open predetermined portions on an upper plane A of the sacrifice substrate 450, where the conductors are to be formed.

Next, as shown in Fig. 15a (d), the first conductors 456 are formed by depositing a conductive material such as nickel (Ni) or a nickel alloy (Ni-Co, Ni-W-Co) with an electrolytic plating method.

Next, as shown in Fig. 15a (e), the upper plane of the first conductor

456 is planarized by removing the uneven portion of the upper plane thereof.

The planarization process is performed by using a CMP (Chemical Mechanical Polishing) method, a grinding method, a lapping method, a polishing method, and a grinding method, etc.

However, in a case where the first conductors 456 are formed only inside portions which are opened by using the first photoresist patterns 454 on the course of an ideal plating process for forming the first conductors 456, the planarization process may be omitted.

In addition, in a case where a method such as a PVD (Physical Vapor Deposition) method and a CVD (Chemical Vapor Deposition) other than the plating process is used to form the first conductors 456, the previously- performed process of forming the first seed layer 452 may be omitted. After that, as shown in Fig. 15a (e), a gold plating process is performed on the upper portion of the first conductors 456, whereby a first gold plating layer 458 is formed. The object of this process is to improve the conductivity of the probe.

Subsequently, as shown in Fig. 15a (f), the first photoresist patterns 454 are removed by using a wet etching process. Herein, the exposed portions of the first seed layer 452 are also removed.

Next, as shown in Fig. 15a (g), the second photoresist patterns 460 are formed by using a photolithography process in order to open predetermined portions of the first conductors 456. Next, as shown in Fig. 15a (h), a thermo-setting epoxy 462 having a function of an adhesive is applied on the portions of the first conductors 456, which are opened by using the second photoresist patterns 460.

Subsequently, as shown in Fig. 15a (h), before the epoxy 462 is cured, a ceramic plate 464 is attached on the upper portion of the epoxy 462. Next, as shown in Fig. 15b (j), the upper plane of the ceramic plate 464 is planarized by using a grinding process. Herein, the planarization process may be the same as that of the first embodiment. When the planarization process is completed, the processes on the upper plane A of the sacrifice substrate 450 are completed. Now, the processes on the lower plane B of the sacrifice substrate 450 will be described.

Firstly, as shown in Fig. 15b (k), the sacrifice substrate 450 is faced down.

Next, as shown in Fig. 15b (1), the lower plane B of the sacrifice substrate 450 are removed up to a half of the original depth of the sacrifice substrate 450by using a grinding process. Therefore, after the grinding process, the depth of the remaining sacrifice substrate is in a range of about

240 to 250 μsa.

Next, as shown in Fig. 15b (m), the third photoresist patterns 466 are formed by using a photolithography process in order to open predetermined portions on the lower plane B of the sacrifice substrate 450, where the dielectric is to be formed.

Subsequently, as shown in Fig. 15b (n), predetermined portions of the sacrifice substrate 450, which are opened by using the third photoresist patterns 466, are removed by using an anisotropic dry etching process, whereby the trenches 467 are formed. At the same time, the seed layer 452 is also removed.

Subsequently, as shown in Fig. 15b (o-l), a thermo-setting epoxy 468 which is used as a dielectric is applied in the trenches 467. After that, as shown in Fig. 15b (p-1), the upper plane of the epoxy

468 is planarized by using a grinding process.

Next, as shown in Fig. 15c (q-1), the second photoresist patterns 460 and the third photoresist patterns 466 are removed by a wet etching process, and the remaining portions of the sacrifice substrate 450 are removed by a wet etching process using KOH, whereby the single-layered probe according to the present invention is completed.

Herein, the conductors may be formed to have the same lengths of portions which are protruded from the center to both sides of the ceramic plate 464. Now, a method of manufacturing a double-layered probe according to the present invention will be described.

Next, as shown in Fig. 15c (o-2), in the state of completion of the process of Fig. 15b (n), after an epoxy 470, which functions as a dielectric and an adhesive, is applied in the trenches 467, before the epoxy 470 is cured, a ceramic plate 472 is attached. Although the attached ceramic plate has a shape of a rectangular parallelepiped similar to the shape of the trenches 467, it may be a ceramic plate 810 having a shape of a parallelogram, in which both ends 811 and 812 are slanted as shown in Figs. 21a, or a ceramic plate 820 having a shape of a step, where both ends 821 and 822 are step-shaped as shown in Figs. 21b. As a result, in the manufactured probe, the externally- protruded portions of the conductors have the same lengths, so that the same pressures can be exerted on all the probe needles during the probing operation. Next, as shown in Fig. 15c (p-2), the upper plane of the ceramic plate 472 is planarized by using a grinding process. Herein, the planarization process may be the same as that of the first embodiment.

Subsequently, as shown in Fig. 15d (q-2), when the lower plane B of the sacrifice substrate 450 are planarized, a second seed layer 474 for a conductor-formation plating process is formed on the entire lower plane B of the sacrifice substrate 450. Herein, the second seed layer 474 is constructed with a titanium layer having a thickness of 500 A and a copper layer having a thickness of 5, 000 A . The copper layer substantially functions as a seed layer in the subsequent plating process. The titanium layer is provided in order to improve an adhesive property of the sacrifice substrate 450 and the copper layer. Next, as shown in Fig. 15d (q-2), when the second seed layer 474 is formed, the fourth photoresist patterns 476 are formed by using a photolithography process in order to open predetermined portions on the lower plane B of the sacrifice substrate 450, where the conductors are to be formed.

Next, as shown in Fig. 15d (r-2), the second conductors 478 are formed by depositing a conductive material such as nickel (Ni) or a nickel alloy (Ni- Co, Ni-W-Co) with an electrolytic plating method.

Next, as shown in Fig. 15d (s-2), the upper plane of the second conductor 478 is planarized by removing the uneven portion of the upper plane thereof. Herein, the planarization process is performed by using the same method as that of the first embodiment. However, in a case where the conductors are formed only inside the opened portions of the fourth photoresist patterns 476 on the course of an ideal plating process for forming the second conductors 478, the planarization process may be omitted.

In addition, in a case where a method such as a PVD (Physical Vapor Deposition) method and a CVD (Chemical Vapor Deposition) other than the plating process is used to form the second conductors 478, since the aforementioned seed layer is not necessary, the process of forming the second seed layer 474 may be omitted. After that, a gold plating process is performed on the upper portion of the second conductors 478, whereby a second gold plating layer 480 is formed. The object of this process is to improve the conductivity of the probe.

Subsequently, as shown in Fig. 15d (t-2), the fourth photoresist patterns 467 are removed by using a wet etching process. At this time, the second seed layer 474, which are externally exposed from the conductors 478, are also removed. Next, the fifth photoresist patterns 482 are formed by using a photolithography process in order to open predetermined portions of the second conductors 478, where the support member is to be formed.

Next, as shown in Fig. 15d (u-2), a thermo-setting epoxy 484 is applied on the portions of the second conductors 478, which are opened by using the fifth photoresist patterns 482. After that, as shown in Fig. 15e (v-2), the upper plane of the applied epoxy 484 is planarized by using a grinding process. Herein, the planarization process is the same as that of the first embodiment.

Subsequently, as shown in Fig. 15e (w-2), the fifth and second photoresist patterns 482 and 460 are removed by using a wet etching process.

Finally, as shown in Fig. 15e (x-2), the remaining portions of the silicon sacrifice substrate 450 are removed by a wet etching process using KOH.

The probe manufactured in accordance with the aforementioned method has the shape shown in Fig. 16.

Fig. 16 is a perspective view illustrating a structure of a probe using a single sacrifice substrate, which are manufactured by the process shown in Fig. 15.

The probe which is manufactured in accordance with the processes in Fig. 15 comprises a dielectric 370 at a central portion, as shown in Fig. 16. The dielectric 370 is formed by attaching an epoxy 370a and a ceramic plate 370b. In other words, trenches are formed on predetermined portions of a sacrifice substrate by using an etching process, the epoxy 370a is applied in the trenches, and the ceramic plate 370b is inserted and attached before the epoxy is cured, whereby the dielectric 370 is formed. Herein, the epoxy 370a is used as an adhesive.

In addition, conductors 372a and 372b are disposed in parallel in a predetermined interval on upper and lower planes of the dielectric 570. First passivation film patterns are formed on predetermined portions on the upper and lower planes of the sacrifice substrate by using a photolithography process, and then a conductive material is deposited on regions which are opened by using the first passivation film patterns, whereby the conductors 372a and 372b are formed. . Herein, in a case that the conductive material is formed by an electrolytic plating method, seed layers are formed on the upper and lower planes of the sacrifice substrate in advance.

In addition, conductive layers 374a and 374b, each of which is made up of a material having a higher electrical conductivity than that of the conductors, are provided on one plane of each of the conductors 372a and 372b in order to improve the conductivities of the conductors. Herein, the conductive material is preferably gold (Au).

Finally, the conductors 372a and 372b are protected and fixed by forming support members 376a and 376b on the upper and lower planes of the dielectric. The support members 376a and376b are preferably constructed with an epoxy or a ceramic which is attached and fixed by an epoxy. The reference numeral 378 indicates a support plate.

(Embodiment 2-7)

As shown in Fig. 17a (a), a silicon wafer of which both planes are polished is prepared as a sacrifice substrate 550. The sacrifice substrate 550 has a thickness of 400 to 500 m by using a grinding process or a polishing process.

Subsequently, as shown in Fig. 17a (b), first photoresist patterns 552 are formed by using a photolithography process in order to open predetermined portions of the sacrifice substrate 550 where the dielectric are to be formed. Subsequently, as shown in Fig. 71a (c), trenches 551 are formed by etching the upper plane A of the sacrifice substrate 550 up to a predetermined depth by using the first photoresist patterns 552. Herein, the etching depth is in a range of 240 to 250 m, which is slightly deeper than the thickness of the to-be-formed dielectric, that is, 240 tτn.

Next, as shown in Fig. 17a (d), after an epoxy 554, which functions as a dielectric and an adhesive, is applied in the trenches 551 , before the epoxy 554 is cured, a ceramic plate 556 is attached. Although the attached ceramic plate has a shape of a rectangular parallelepiped similar to the shape of the trenches 551 , it may be a ceramic plate 820 having a shape of a parallelogram, in which both ends 811 and 812 are slanted as shown in Figs. 21 a, or a ceramic plate 820 having a shape of a step, where both ends 821 and 822 are step-shaped. As a result, in the manufactured probe, the externally-protruded portions of the conductors have the same lengths, so that the same pressures can be exerted on all the probe needles during the probing operation.

After that, as shown in Fig. 17a (e), the upper plane of the ceramic plate 556 are planarized by using a grinding process. Herein, the planarization process is the same as that of the first embodiment. When the upper plane of the ceramic plate 556 is planarized, a first seed layer 558 for a^' conductor-formation plating process is formed on the entire upper plane A of the sacrifice substrate 550 by using a sputtering process.

Herein, the first seed layer 558 is constructed with a titanium layer having a thickness of 500 A and a copper layer having a thickness of 5,000 A . The copper layer substantially functions as a seed layer in the subsequent plating process. The titanium layer is provided in order to improve an adhesive property of the sacrifice substrate 550 and the copper layer.

Next, as shown in Fig. 17a (f), the second photoresist patterns 560 are formed by using a photolithography process in order to open predetermined portions on the upper plane A of the sacrifice substrate 550, where the conductors are to be formed.

Next, as shown in Fig. 17a (g), the first conductors 562 are formed by depositing a conductive material such as nickel (Ni) or a nickel alloy (Ni-Co, Ni-W-Co) with an electrolytic plating method.

Next, as shown in Fig. 17a (h), the upper plane of the first conductor 562 is planarized by removing the uneven portion or the excessively-formed portion of the upper plane thereof. Herein, the planarization process is the same method as disclosed in the first embodiment.

However, in a case where the conductors are formed only inside the opened portions of the second photoresist patterns 560 on the course of an ideal plating process for forming the first conductors 562, the planarization process may be omitted.

In addition, in a case where a method such as a PVD (Physical Vapor Deposition) method and a CVD (Chemical Vapor Deposition) other than the plating process is used to form the first conductors 562, the process of forming the first seed layer 558 may be omitted.

After that, as shown in Fig. 17b (i), a gold plating process is performed on upper portion of the first conductors 562, whereby a first gold plating layer

564 is formed. The object of this process is to improve the conductivity of the probe. Subsequently, as shown in Fig. 17b (j), a first passivation film 566 are formed to protect first conductors 562, which are formed on the upper plane A of the sacrifice substrate 550, and a first gold plating layer 564. Herein, a tape or a photoresist is used for the passivation film.

As a result, the processes on the upper plane A of the sacrifice substrate 550 is finished, and then the processes on the lower B thereof are started.

Firstly, as shown in Fig. 17b (k), the sacrifice substrate 550 is faced down, and then the lower plane B of the sacrifice substrate 550 are removed by using a grinding method or a polishing method. The sacrifice substrate 550 is removed up to such a thickness that the ceramic plate 556 can be exposed.

Next, as shown in Fig. 17b (1), s second seed layer 568 for a conductor- formation plating process is formed on the entire lower plane B of the sacrifice substrate 550. Subsequently, third photoresist patterns 570 are formed by using a photolithography process in order to open predetermined portions on the lower plane B of the sacrifice substrate 550 where the conductors are to be formed.

Subsequently, as shown in Fig. 17b (m), second conductors 572 is formed on the portions which are opened by using the third photoresist patterns 570.

Next, as shown in Fig. 17b (n), if the upper plane of the second conductor 572 is uneven, a planarization process is performed on the upper plane thereof. Herein, the planarization process is the same method as disclosed in the first embodiment. However, in a case where the second conductors 572 are formed only inside the opened portions of the second photoresist patterns 570 on the course of an ideal plating process for forming the second conductors 572, the planarization process may be omitted.

In addition, in a case where a method such as a PVD (Physical Vapor Deposition) method and a CVD (Chemical Vapor Deposition) other than the plating process is used to form the second conductors 572, since the seed layer is not necessary, the previously-performed process of forming the second seed layer 568 may be omitted.

After that, as shown in Fig. 17b (o), a gold plating process is performed on the upper plane of the second conductors 572, whereby a second gold plating layer 574 is formed. The object of this process is to improve the conductivity of the probe. Subsequently, the first passivation film which is formed on the upper plane A of the sacrifice substrate 550 is removed, and the second and third photoresist patterns 560 and 570 are simultaneously removed by using a wet etching process. Herein, the exposed portions of the second seed layer 568 are also removed.

After that, as shown in Fig. 17c (p), a second passivation film 576 is formed on the upper plane A of the sacrifice substrate 550 in order to protect the upper plane A. Subsequently, fourth photoresist patterns 578 are formed by using a photolithography process in order to open predetermined portions on the second conductors 572 where the support member is to be formed.

Next, as shown in Fig. 17c (q), a thermo-setting epoxy 580 is applied on the portions which are opened by using the fourth photoresist patterns 578. . After that, as shown in Fig. 17c (r), the upper plane of the epoxy 580 is planarized by using a grinding process. The planarization process is the same as that of the first embodiment.

Subsequently, as shown in Fig. 17c (s), the second passivation film 576 on the upper plane A of the sacrifice substrate 550 is removed. Next, fifth photoresist patterns 582 are formed in order to open predetermined portions of the first conductors 562, where the supper member is to be formed.

Next, as shown in Fig. 17c (t), a thermo-setting epoxy 584 is applied on the portions which are opened by using the fifth photoresist patterns 582, and then the upper plane of the epoxy 584 is planarized by using a grinding process. Finally, as shown in Fig. 17c (u), the fourth and fifth photoresist patterns 578 and 582 are simultaneously removed by a wet etching process, and the remaining portions of the sacrifice substrate 550 between the first and second conductors 562 and 572 are selectively removed by a wet etching process using KOH. When the sacrifice substrate 500 is removed, the probe of the present invention is completed.

(Embodiment 2-8)

As shown in Fig. 18a, a silicon wafer of which both planes are polished is prepared as a sacrifice substrate 650. The sacrifice substrate 650 has a thickness of 240 /m by using a grinding process or a polishing process.

Next, as shown in Fig. 18a (b), the lower plane B of the sacrifice substrate 650 is attached with a tape for preventing contamination, or it is coated with a coating material 652 such as a photoresist. Next, as shown in Fig. 18a (c), the central portion of the sacrifice substrate 650 is cut in a predetermined shape along the incision portions 653 by using a dicing process.

Next, as shown in Fig. 18a (d), the sacrifice substrate blocks 654 having a predetermined size, that is, center silicon blocks, which are created by the dicing process, are removed form the sacrifice substrate 650. As a result, trenches 655 are formed on the central portion of the sacrifice substrate

650.

Next, as shown in Fig. 18a (e), a ceramic plate 656 which is used as a dielectric is inserted in the trenches 655, and then, an epoxy 658 is applied to bury the gaps between the ceramic plate 656 and the sacrifice substrate 650.

Herein, the epoxy has a function of attaching the ceramic plate 565 and the sacrifice substrate 650.

Next, as shown in Fig. 18a (f), the upper plane A of the sacrifice substrate 650 is planarized. Next, as shown in Fig. 18a (g), the coating material 652 formed on the lower plane B of the sacrifice substrate 650 is removed, and the lower plane B of the sacrifice substrate 650 is planarized like the upper plane A thereof.

Next, as shown in Fig. 18a (h), first seed layers 660 and 662 for a conductor-formation plating process are formed on the entire lower plane B of the sacrifice substrate 650.

Herein, the first seed layers 660 and 662 are constructed with a titanium layer having a thickness of 500 A and a copper layer having a thickness of 5,000 A . The copper layer substantially functions as a seed layer in the subsequent plating process. The titanium layer is provided in order to improve an adhesive property of the sacrifice substrate 650 and the copper layer.

Next, as shown in Fig. 18a (i), the first passivation film 667 for protecting the seed layer 662 is formed on the lower plane B of the sacrifice substrate 650, and the first photoresist patterns 664 are formed on the upper plane A of the sacrifice substrate 650 by using a photolithography process in order to open predetermined portions of the sacrifice substrate 650 where the conductors are to be formed.

Subsequently, as shown in Fig. 18a (j), the first conductors 666 are formed on portions where are opened by using the first photoresist patterns 664. Herein, the first conductors 666 are formed by depositing a conductive material such as nickel (Ni) or a nickel alloy (Ni-Co, Ni-W-Co) with an electrolytic plating method.

Next, as shown in Fig. 18b (k), the upper plane of the first conductor 666 is planarized by removing the uneven portion of the upper plane thereof. Herein, the planarization process is the same method as disclosed in the first embodiment.

However, in a case where the first conductors 666 are formed only inside the opened portions of the first photoresist patterns 664 on the course of an ideal plating process for forming the first conductors 666, the planarization process may be omitted.

After that, a gold plating process is performed on entire upper portion of the first conductors 666, whereby a first gold plating layer 668 is formed.

In addition, in a case where a method such as a PVD (Physical Vapor

Deposition) method and a CVD (Chemical Vapor Deposition) other than the plating process is used to form the first conductors 666, since the seed is not necessary, the process of forming the first seed layer 660 may be omitted.

Next, as shown in Fig. 18b (1), a second passivation film 670 for protecting the upper plane A of the sacrifice substrate 650, where the first conductors 666 are formed, is formed by using a tape or a photoresist. When the formation of the second passivation film 670 is completed, the first process on the upper plane A of the sacrifice substrate 650 is completed. After that, the sacrifice substrate is faced down, and then the passivation film 667 for protecting the lower plane of the sacrifice substrate 650 is removed.

Now, the processes on the lower plane B of the sacrifice substrate 650 will be described.

Next, as shown in Fig. 18b (m), the second photoresist patterns 672 are formed by using a photolithography process in order to open predetermined portions on the lower plane B of the sacrifice substrate 650, where the conductors are to be formed. Subsequently, as shown in Fig. 18b (n), the second conductors 674 are formed on portions where are opened by using the second photoresist patterns 672. Herein, the second conductors 674 are formed by depositing a conductive material such as nickel (Ni) or a nickel alloy (Ni-Co, Ni-W-Co) with an electrolytic plating method. Next, as shown in Fig. 18b (o), the upper plane of the second conductor 674 is planarized by removing the uneven portion of the upper plane thereof. Herein, the planarization process is the same method as disclosed in the first embodiment. After the planarization process is completed, a gold plating process is performed on entire upper portion of the second conductors 674, whereby a second gold plating layer 676 is formed. However, in a case where the conductors are formed only inside portions which are opened by using the second photoresist patterns 672 on the course of an ideal plating process for forming the second conductors 674, the planarization process may be omitted. In addition, in a case where a method such as a PVD (Physical Vapor

Deposition) method and a CVD (Chemical Vapor Deposition) other than the plating process is used to form the second conductors 674, since the seed is not necessary, the previously-performed process of forming the seed layer 662 be omitted. Subsequently, as shown in Fig. 18b (p), the second photoresist patterns

672 are removed by using a wet etching process. Herein, the exposed portion of the second seed layer 662 is also removed. In addition, the first photoresist patterns 664, which are protected by the second passivation film 670, may be simultaneously removed. Next, as shown in Fig. 18b (q), the third photoresist patterns 678 are formed by using a photolithography process in order to open predetermined portions of the second conductors 674, where the support member is to be formed.

Next, as shown in Fig. 18c (r), an epoxy 680 is applied on the opened portion of the second conductors 674 by using the third photoresist patterns 678 as a mold.

Subsequently, as shown in Fig. 18c (s), the upper plane of the epoxy 680 is planarized by using a grinding process.

Subsequently, as shown in Fig. 18c (t), the second passivation film 670, which are formed on the upper plane A of the sacrifice substrate 650, are removed. Next, the first photoresist patterns 664 are removed by using a wet etching process, and the exposed portions of the seed layer 660 are also removed.

Next, as shown in Fig. 18c (u), the fourth photoresist patterns 682 are formed by using a photolithography process in order to open predetermined portions of the first conductors 666, where the support member is to be formed. Subsequently, an epoxy 684 is applied on the opened portions of the conductors 666 by using the fourth photoresist patterns 682. After that, the upper plane of the epoxy 684 is planarized by using a grinding process. Subsequently, as shown in Fig. 18c (v), the third and fourth photoresist patterns 678 and 682 are simultaneously removed by using a wet etching process, and the remaining portions of the sacrifice substrate 650 are also removed by a wet etching process using KOH.

Next, as shown in Fig. 18c (w), when the epoxy 658 is removed, the probe of the present invention is completed.

(Embodiment 2-9)

As shown in Fig. 19a (a), a ceramic plate of which both planes are polished is prepared as a sacrifice substrate 750. The sacrifice substrate 750 has a thickness of 400 to 500/im by using a grinding process or a polishing process.

Subsequently, as shown in Fig. 19a (b), two trenches 752 are formed on predetermined portions on an upper plane A of the sacrifice substrate 750 by using a dicing process. Next, as shown in Fig. 19a (c), a first seed layer 754 for a copper plating-structure-formation plating process, in which the copper plating structure is used as a trench burying material, is formed on the upper plane A of the sacrifice substrate 750, where the trenches 752 are formed, and the trenches. Herein, the first seed layer 754 is constructed with a titanium layer and a copper layer.

Subsequently, as shown in Fig. 19a (d), the first photoresist patterns 756 are formed by using a photolithography process in order to open predetermined portions on the upper plane A of the sacrifice substrate 750, where the trenches 752 are formed. Next, as shown in Fig. 19a (e), the copper plating structure 758 as the trench burying material is formed on the trenches, which are opened by the first photoresist patterns 756, by using a plating process.

Next, as shown in Fig. 19a (f), the first photoresist patterns 756 and the portions of the copper plating structure 758, which are upwardly protruded form the sacrifice substrate 750, are removed, whereby the upper plane A of the sacrifice substrate 750 is planarized. The planarization process is performed up to the surface where the upper plane A of the sacrifice substrate 750 and the copper plating structure 758 are abutted on each other.

Subsequently, as shown in Fig. 19a (g), a second seed layer 760 for a conductor-formation plating process is formed on the upper plane of the sacrifice substrate 750. Herein, the second seed layer 760 is constructed with a titanium layer having a thickness of 500 A and a copper layer having a thickness of 5, 000 . The copper layer substantially functions as a seed layer in the subsequent plating process. The titanium layer is provided in order to improve an adhesive property of the sacrifice substrate 750 and the copper layer.

Next, as shown in Fig. 19b (h), the second photoresist patterns 762 are formed by using a photolithography process in order to open predetermined portions of the sacrifice substrate 750, where the conductors are to be formed. Subsequently, as shown in Fig. 19b (i), the first conductors 764 are formed on portions where are opened by using the second photoresist patterns

762. Herein, the first conductors 764 are formed by depositing a conductive material such as nickel (Ni) or a nickel alloy (Ni-Co, Ni-W-Co) with an electrolytic plating method. Next, as shown in Fig. 19b (j), the upper plane of the first conductor

764 is planarized by removing the uneven portion of the upper plane thereof.

Herein, the planarization process is the same method as disclosed in the first embodiment.

However, in a case where the conductors are formed only inside the opened portions of the second photoresist patterns 762 on the course of an ideal plating process for forming the first conductors 764, the planarization process may be omitted.

In addition, in a case where a method such as a PVD (Physical Vapor

Deposition) method and a CVD (Chemical Vapor Deposition) other than the plating process is used to form the first conductors 764, since the seed is not necessary, the previously-performed process of forming. the second seed layer

760 may be omitted.

After that, as shown in Fig. 19b (k), a gold plating process is performed on entire upper portion of the first conductors 764, whereby a first gold plating layer 766 is formed. Next, as shown in Fig. 19b (1), a passivation film 768 for protecting the first conductors 764, which are formed on the upper plane A of the sacrifice substrate 750, and the first gold plating layer 766 is formed.

By the aforementioned process being completed, the process on the upper plane A of the sacrifice substrate 750 is completed.

Now, the process on the lower plane B of the sacrifice substrate 750 will be described.

Firstly, as shown in Fig. 19b (m), the sacrifice substrate 750 is removed by a grinding process up to such a level that the lower plane B of the sacrifice substrate 750 and the lower plane of the copper plating structure 758 can be exposed.

Subsequently, as shown in Fig. 19b (n), a third seed layer 770 for a conductor-formation plating process is formed on the entire lower plane of the sacrifice substrate 750. Herein, the third seed layer 770 is constructed with a titanium layer having a thickness of 500 A and a copper layer having a thickness of 5,000 . The copper layer substantially functions as a seed layer in the subsequent plating process. The titanium layer is provided in order to improve an adhesive property of the sacrifice substrate 750 and the copper layer. Next, third photoresist patterns 772 are formed by using a photolithography process in order to open predetermined portions on the upper plane of the sacrifice substrate 750, where the conductors are to be formed.

Next, as shown in Fig. 19c (o), the second conductors 774 are formed on portions where are opened by using the third photoresist patterns 772.

Herein, the third conductors 774 are formed by depositing a conductive material such as nickel (Ni) or a nickel alloy (Ni-Co, Ni-W-Co) with an electrolytic plating method.

Next, as shown in Fig. 19c (p), the upper plane of the second conductor 774 is planarized by removing the uneven portion of the upper plane thereof. Herein, the planarization process is the same method as disclosed in the first embodiment. After the planarization process is completed, a gold plating process is performed on entire upper portion of the second conductors 774, whereby a second gold plating layer 776 is formed.

However, in a case where the conductors are formed only inside the opened portions of the third photoresist patterns 772 on the course of an ideal plating process for forming the second conductors 774, the planarization process may be omitted.

In addition, in a case where a method such as a PVD (Physical Vapor Deposition) method and a CVD (Chemical Vapor Deposition) other than the plating process is used to form the second conductors 774, the previously- performed process of forming the third seed layer 770 be omitted.

Next, as shown in Fig. 19c (q), the passivation film 768 is removed, and the second and third photoresist patterns 762 and 772 are simultaneously removed by using a wet etching process. Herein, the exposed portions of the second and third seed layers 760 and 770 are also removed. Next, as shown in Fig. 19c (r), fourth and fifth photoresist patterns 778 and 780 are formed by using a photolithography process in order to open predetermined portions of the first and second conductors 764 and 774, where the support members are to be formed.

Next, as shown in Fig. 19c (s), a thermo-setting epoxy 782 is applied on the portions of the second conductors 774, which are opened by using the fourth photoresist patterns 778.

After that, as shown in Fig. 19d (t), the upper plane of the epoxy 782 is planarized by using a grinding process.

Next, as shown in Fig. 19d (u), an epoxy layer 784 is formed on the upper plane of the sacrifice substrate 750 by using the same process. Subsequently, as shown in Fig. 19d (v), the upper plane of the epoxy 784 is planarized by using a grinding process.

Subsequently, as shown in Fig. 19d (w), the fourth and fifth photoresist patterns 778 and 780, which are remaining on the upper and lower planes of the sacrifice substrate 750, are simultaneously removed by using a wet etching process.

Finally, the sacrifice substrate 750 is removed by applying an external force on the remaining sacrifice substrate 750, and the trench burying material 758 is removed by using a selective etching process, whereby the probe of the present invention is completed.

On the other hand, Fig. 20 illustrates the structure of the probe manufactured in accordance with the method shown in Figs. 17, 18 and 19.

Fig. 20 is a perspective view illustrating a probe formed by using a single sacrifice substrate manufactured according to an embodiment of the present invention.

As shown in Fig. 20, a dielectric 380 is provided at central portion of the probe, and conductors 382a and 382b are disposed in corresponding predetermined intervals on upper and lower planes of the dielectric 380, respectively. In addition, support members 384a and 384b are attached on the upper and lower planes of the dielectric 380, respectively, where the conductors 382a and the 382b are disposed. In addition, thin layers 386a and 386b, each of which are made up of a material having a higher electrical conductivity than that of the conductors, are provided on respective external planes of the conductors 382a and 382b. Trenches used for formation of the dielectric are formed on predetermined portions of the sacrifice substrate, and then the trenches are buried with a dielectric material, whereby the dielectric 380 is formed. The dielectric material is preferably a ceramic. The dielectric may has a cross section of which both ends have a step-difference shape or a slanted shape. T first passivation films are formed on both planes of the dielectric 380 by using a photolithography process, and then the conductors 382a and 382b are formed by depositing a conductive material on regions which are opened by using the first passivation films. In addition, second passivation films are formed by using a photolithography process on both planes of the sacrifice substrate where the conductors 382a and 382b are formed, and then a support material is buried in regions which are opened by using the second passivation films, whereby the support members 384a and 384b are formed.

In addition, the probe using a single sacrifice substrate, which is manufactured in accordance with the embodiment 2-6, has the same structure as that of Fig. 25. Therefore, the detailed description of the structure of the probe is omitted.

Fig. 21 a is a perspective views and a cross-sectional view illustrating a ceramic plate used in the present invention, of which cross section has a shape of a parallelogram, and Fig. 21b is a perspective views and a cross-sectional view illustrating a ceramic plate used in the present invention. These shapes can be adapted to all the embodiment of the present invention.

(First Embodiment of a Probe Assembly)

Fig. 22a is a perspective view for explaining a first probe assembly comprising the aforementioned probe for testing a flat panel display device according to the present invention, and Fig. 22b is a cross-sectional view thereof. Herein, the description of the specific construction of the aforementioned probe sheet and the method of manufacturing the same will be omitted. Referring to Figs 22a and 22b, in a probe assembly in accordance with the first embodiment of the present invention, a probe where the plurality of unit structures are attached and fixed on a transparent film 901, is fixed on a lower portion of a probe block 904. Herein, each of the unit structure comprises a beam element 900 having an inspection tip 902 and a connection tip (not shown).

The probe and the probe block 904 are attached and fixed to each other by using a double-sided tape or an adhesive. The probe block 904 is made up of a transparent material such as an acryl in order to ensure its transparency.

In addition, a first interface board 908 is provided above the probe block 904, and they are fixed to each other by engagement of anchor bolts 904. A second interface board 910 and a probe holder 912 are sequentially provided above the first interface board 908, and they are fixed to each other by engagement of an anchor bolt 914.

In addition, the first and second interface boards 908 and 910 are engaged with a fixing pin 907 to further increase an engaging force therebetween. The second interface board 910 and the probe holder 912 are also engaged with a fixing pin 911 to further increase an engaging force therebetween.

The connection tips (not shown), which are provided at the one distal portions of the beam elements 900 of the probe sheet, are connected to patterns provided on a TCP (Tape Carrier Package) 932 through a guide film 930.

More specifically, the structure are constructed by disposing the probe, where the connection tips are formed, on the lower portion of the first interface board 980, and then by engaging the probe and the first interface board with a fixing member 922 and an anchor bolt 924.

More specifically, an upper close-adhesion member 926 and a lower close-adhesion member 928, which are made up of an insulating ceramic material, are inserted between the probe and the first interface board 908 and between the TCP 932 and the fixing member 922, respectively. In addition, the connection tip 902b of the probe and the TCP 932 are connected to each other through the guide film 930 between the upper and lower close-adhesion members 926 and 928.

In addition, a pressing anchor bolt 929 is further provided at the lower portion of the fixing member 922, so that the connection tip 902b of the probe and the TCP 932 can be more intensively connected to each other through the guide film 932 by means of rotational pressing of the anchor bolt 929.

In addition, the probe holder 912 and a manipulator 916 are engaged to each other by means of an anchor bolt 920. The probe holder 912, which is connected to the manipulator 916, can be moved up and down by an up-down physical force F during a test process.

More specifically, the one side of the probe holder 912 and the one side of the manipulator 916 are engaged to each other by means of a guide rail

918, so that the first interface board 908, the second interface board 910 connected to the probe holder 912, and the probe block 904 can be moved up and down by the up-down physical force F during the test process.

In particular, a spring 921 having a predetermined elastic force is provided around the fixing member 920 connecting the probe holder 912 and the manipulator 916, so that the first interface board 908, the second interface board 910 connected to the probe holder 912, and the probe block 904, which are moved up and down by the up-down physical force F during the test process, can be restored to their original positions by means of the elastic force of the spring 921.

In anther embodiment, as shown in Fig. 23, the aforementioned fixing member provided on the lower portion of the first interface board 908 is omitted. In addition, a probe beam element having no connection tip and the TCP 932 are disposed on an anisotropic conductive film (ACF) 935 and connected to each other by using a pressing process and a heating process.

Therefore, after the flat panel display device, which is obtained by a series of processes of manufacturing the flat panel display device, is mounted on a probing instrument, electrical test processes are performed on the flat panel display device by moving the probe block 904 with a moving means and applying a predetermined physical force on the electrode pads of the flat panel display device. At that time, the inspection tips 902 at the lower portion of the probe block 904 are contacted to the electrode pads of the flat panel display device. Electrical signals, which are input to the probing instrument, are applied to the electrode pads of the flat panel display device through the TCP 932, the probe beam elements, and the inspection tips 902.

(Second Embodiment of a Probe Assembly)

Fig. 24a is a perspective view for explaining a second probe assembly comprising the aforementioned probe for testing a flat panel display device according to the present invention, and Fig. 24b is a cross-sectional view thereof. The detailed description of the construction of the aforementioned probe and method of manufacturing the probe is omitted.

Referring to Figs 24a and 24b, in the second probe assembly in accordance with the second embodiment of the present invention, a metal plate 936 having a high elasticity, which is made up of a metal such as a stainless steel, is used in place of the probe block made up of a transparent material at the lower portion of the first interface board 908 in the first probe assembly. The metal plate 936 is fixed at the lower portion of the first interface board 908 by means of an anchor bolt 903, and the probe is fixed on the lower portion of the metal plate 936 through a high elastic rubber 938 by means of an adhesive.

Therefore, in the second probe assembly where the elastic metal plate 936 and the rubber 938 at the lower portion of the first interface board 908, the electrical test processes are performed by applying a predetermined physical force F on the electrode pads of the flat panel display device, it is possible to increase the elasticity. (Third Embodiment of a Probe Assembly)

Fig. 25 is a perspective view for explaining a probe assembly comprising the aforementioned probe for testing a flat panel display device according to the present invention, and Fig. 26 is a cross-sectional view thereof.

Referring to Figs 25 and 26, in a probe assembly in accordance with the third embodiment of the present invention, a multi-layered probe is provided in a stacked structure. As described above, the multi-layered probe comprises conductors 960 of an upper probe and conductors 950 of a lower probe, which are stacked to be alternated and not to be overlapped to each other. The one distal portions of each of the conductors 960 of the upper probe is externally protruded more than that of the each of the conductors 950, and the externally-exposed portions of the upper and lower conductors have the same length in order to have the same electrical and physical properties and conduction.

The probes in the stacked structure are fixed to each other on a slanted plane of the probe block 955 by using an attaching-fixing means such as an anchor bolt. The probe block 955 may be made up of a transparent material such as an acryl in order to ensure its transparency.

In addition, a first interface board 965 is provided above the probe block 955. A probe holder 970 is provided above the first interface board 965, and they are fixed to each other by engagement of an anchor bolt 967.

The first interface board 965 and the probe holder 970 are engaged with a fixing pin 967 to further increase an engaging force therebetween. In addition, a second interface board 975 is also fixed at the back of the probe block 955 on the lower plane of the first interface board 965 by engagement of a fixing pin 967. A TCP 972 is attached and fixed on the lower plane of the second interface board 975. With respect to the connection of the TCP 972 and the conductors 950 and 960 of the multi-layered probe which is attached and fixed on the slanted plane of the probe block 955, the one end of each of the conductors 950 and 960 of the multi-layered probe is connected to the corresponding pattern, which are provided on the TCP 972, by the guidance of a hole (not indicated by a reference numeral) which is formed on a guide film 974.

In addition, the probe holder 970 and a manipulator 980 are engaged to each other by means of an anchor bolt 982. The probe holder 970, which is connected to the manipulator 980, can be moved up and down by an up-down physical force F during a test process. More specifically, the one side of the probe holder 970 and the one side of the manipulator 980 are engaged to each other by means of a guide rail 984, so that the first interface board 965 connected to the probe holder 970 and the probe block 955 can be moved up and down by the up-down physical force F during the test process. In particular, a spring 986 having a predetermined elastic force is provided around the fixing member 982 connecting the probe holder 970 and the manipulator 980, so that the first interface board 965 connected to the probe holder 970 and the probe block 955, which are moved up and down by the up-down physical force F during the test process, can be restored to their original positions by means of the elastic force of the spring 986. Therefore, after the flat panel display device, which is obtained by a series of processes of manufacturing the flat panel display device, is mounted on a probing instrument, electrical test processes are performed on the flat panel display device by moving the probe block 955 with a moving means and applying a predetermined physical force on the electrode pads of the flat panel display device.

At that time, needles 950 and 960 of the multi-layered probe at the lower portion of the probe block 955 are contacted to the electrode pads of the flat panel display device. Electrical signals, which are input to the probing instrument, are applied to the electrode pads of the flat panel display device through the TCP 972, the probe beam elements, and the needles 950 and 960 of the probe.

INDUSTRIAL AVAILABILITY According to the present invention, the probe can be easily manufactured on the support plate made up of a hard material by using a dicing saw process and a process of attaching conductors having a shape of a needle, so that it is advantageously possible to reduce time of a process of manufacturing the probe and to increase the corresponding productivity. In addition, according to the present invention, the process of adhering a plurality of conductors with an epoxy can be removed and misalignment of a probe, which have been generated due to difference of thermal expansion coefficient in an adhering process and a manual operation in the prior art, can be prevented by using a photo-aligner, so that it is advantageously possible to align the probe with a higher accuracy. Furthermore, according to the present invention, unlike the process in the prior art, a single sacrifice substrate can be used, the number of highly- difficult processes can be reduced, and the yield can be increased due to the reduction of the processes and the improvement of the accuracy, so that it is advantageously possible to reduce the production price of the probe and to improve the process yield and the productivity.

Although the present invention and its advantages have been described in details, it should be understood that the present invention is not limit to the aforementioned embodiment and the accompanying drawings and it should be understood that various changes, substitutions and alterations can be made herein by the skilled in the arts without departing from the sprit and the scope of the present invention as defined by the appended claims.

Claims

WHAT IS CLAIMED IS:

1. A probe for testing a flat panel display device comprising: a plate-like dielectric; a plurality of conductors being provided in parallel; and first trenches being provided on at least one plane of upper and lower planes of the dielectric to fix the plurality of conductors in the dielectric in a predetermined arrangement.

2. The probe for testing a flat panel display device according to claiml, wherein first and second protrusion regions having a predetermined area are provided on both end portions of one plane of the dielectric and a central groove is provided on the one plane; and wherein the first trenches on the first and second protrusion regions are connected to the central groove.

3. The probe for testing a flat panel display device according to claim 1 , wherein a secondary probe is provided to overlap the probe; and wherein conductors of the overlapped probes are disposed in parallel to each other.

4. The probe for testing a flat panel display device according to claim 2, wherein the central groove is formed by using a dicing process.

5. The probe for testing a flat panel display device according to claim 1. wherein the conductors have acute distal portions

6. The probe for testing a flat panel display device according to claim 2, wherein the interval of the first trenches formed on the first protrusion regions are different from that of the first trenches formed on the second protrusion regions.

7. The probe for testing a flat panel display device according to claim 1 , wherein the dielectric is made up of a ceramic material.

8. The probe for testing a flat panel display device according to claim 1 , wherein the probe further comprises a support member which is stacked on the upper plane or the lower plane of the dielectric to fix the conductors in the first trenches on the dielectric.

9. The probe for testing a flat panel display device according to claim 1 , wherein the first trenches are formed by using a photolithography process and first and second etching processes.

10. The probe for testing a flat panel display device according to claim 9, wherein each of the first trenches which are subjected to the first etching process has a shape of a truncated pyramid or a truncated cone; and wherein, each of the first trenches having a shape of a truncated pyramid or a truncated cone are further etched up to a predetermined depth by the second etching process and a bottom of each of the first trenches is subjected to a rounding process.

11. A probe for testing a flat panel display device comprising a plurality of unit contact members being disposed and fixed separately in a predetermined interval on a lower portion of a thin film, wherein the thin film having a predetermined size, each of the unit contact members comprising a beam element having a shape of a bar, and wherein an inspection tip is provided at one end of the beam element in an integrated manner.

12. The probe for testing a flat panel display device according to claim 11 , wherein a connection tip is provided at the other end of the beam element.

13. The probe for testing a flat panel display device according to claim 12, wherein the thin film is made up of an epoxy or a parylene.

14. A probe for testing a flat panel display device comprising: a sacrifice substrate; first trenches being formed by using a photolithography process and an etching process; conductors being disposed to have a predetermined interval in the first trenches on the sacrifice substrate by using a conductive film formation process; a first dielectric being formed above the conductors; and second trenches being formed by using a photolithography process and an etching process to expose the conductors on a lower plane of the sacrifice substrate; a second dielectric being formed by burying a dielectric material in the third trenches.

15. The probe for testing a flat panel display device according to claim 14, wherein the first dielectric is made up of an epoxy.

16. The probe for testing a flat panel display device according to claim 14, wherein the second dielectric is a ceramic plate which is adhered with an epoxy.

17. A probe formed by using a single sacrifice substrate comprising: a plate-like dielectric; and a plurality of conductors where trenches are formed by a photolithography process and an etching process, wherein a conductive material is buried in the trenches, wherein the plurality of conductors are disposed in a predetermined interval on the upper and lower planes of the dielectric, and wherein the conductors formed on the upper plane and the conductors formed on the lower plane are disposed in parallel.

18. The probe formed by using a single sacrifice substrate according to claim 17, wherein the probe further comprises a plate-like support member being stacked on the upper plane or the lower plane of the dielectric to fix the locations of the conductors.

19. The probe formed by using a single sacrifice substrate according to claim 17, wherein the plurality of conductors have the same length.

20. The probe formed by using a single sacrifice substrate according to claim 19, wherein the conductors formed on the upper plane of the dielectric having the same length are shifted in a predetermined distance toward one side of the dielectric, whereby each of the conductors formed on the upper plane of the dielectric has one end which is further protruded and the other end which is further recessed in comparison to each of the conductors formed on the lower plane of the dielectric

21. The probe formed by using a single sacrifice substrate according to claim 17, wherein both ends of the dielectric have a step-difference shape, whereby the conductors formed on the upper and lower planes of the dielectric are protruded externally from the dielectric in the same length.

22. The probe formed by using a single sacrifice substrate according to claim 17, wherein both ends of the dielectric have a slanted shape, whereby the conductors formed on the upper and lower planes of the dielectric are protruded externally from the dielectric in the same length.

23. The probe formed by using a single sacrifice substrate according to claim 17, wherein each of the conductors formed on the upper plane of the dielectric is disposed between two adjacent conductors formed on the lower plane of the dielectric.

24. A probe formed by using a single sacrifice substrate comprising: a plate-like first dielectric; a second dielectric being stacked, where a step difference is formed at an upper portion of the first dielectric; a plurality of conductors being provided in a predetermined interval to pass through the first and second dielectrics; and a conductive layer being formed by stacking a conductive material on one plane of each of the conductors by a predetermined plating method.

25. The probe formed by using a single sacrifice substrate according to claim 24, wherein the probe further comprises a support member being stacked on at least one plane of the upper plane of the first dielectric and the lower plane of the second dielectric.

26. A probe formed by using a single sacrifice substrate comprising: a dielectric being formed by stacking a ceramic plate on upper and lower planes of an epoxy; a plurality of conductors being formed in a predetermined interval on the upper and lower planes of the dielectric; a conductive layer being stacked on one plane of each of the conductors by a predetermined plating method; and support members being stacked on the upper and lower planes of the dielectric to fix locations of the conductors.

27. A probe formed by using a single sacrifice substrate comprising: a plate-like dielectric; a plurality of conductors being formed in a predetermined interval on upper and lower planes of the dielectric; a conductive layer being stacked on one plane of each of the conductors by a predetermined plating method; support members being stacked on the upper and lower planes of the dielectric to fix locations of the conductors.

28. A method of manufacturing a probe for testing a flat panel display device, comprising steps of: a first trench formation step of forming first trenches on at least one plane of upper and lower planes of a dielectric, thereby fixing a plurality of conductors on the dielectric in a predetermined arrangement; and a support member formation step of stacking a support member on an upper plane or a lower plane of the dielectric, thereby fixing the conductors in the first trenches on the dielectric.

29. The method of manufacturing a probe for testing a flat panel display device, according to claim 28, wherein the method further comprises a central groove formation step of forming a central groove on a central region of the dielectric, thereby forming a first protrusion region and a second protrusion region on both side portions of the dielectric, the first and second protrusion regions having a predetermined area; and wherein the first trenches on the first and second protrusion regions are connected to the central groove.

30. The method of manufacturing a probe for testing a flat panel display device, according to claim 28, wherein a secondary probe is stacked on the probe, and wherein conductors of the secondary probe and the conductors of the probe are disposed in parallel.

31. The method of manufacturing a probe for testing a flat panel display device, according to claim 29, wherein the first trenches and the central groove are formed by using a dicing process.

32. The method of manufacturing a probe for testing a flat panel display device, according to claim 29, wherein the interval of the first trenches formed on the first protrusion region is different form that of the first trenches formed on the second protrusion region.

33. The method of manufacturing a probe for testing a flat panel display device according to claim 28, wherein a support member is formed on the upper plane or the lower plane of the dielectric to fix the conductors in the first trenches on the dielectric.

34. A method of manufacturing a probe for testing a flat panel display device comprising: a conductor formation step of forming photoresist patterns having a predetermined thickness on at least one plane of an upper plane and a lower plane of a single sacrifice substrate having a predetermined thickness by using a photolithography process and a conductive film formation process, thereby forming conductors; a dielectric formation step of forming photoresist patterns to open a central portion of each of the conductors by using a photolithography, and forming a dielectric on the opened central portion of each of the conductors; a trench formation step of forming trenches to expose the lower plane of each of the conductors by using a photolithography and an etching process; a support member formation step of forming a support member by burying a support material in the trenches; and a finishing step of removing the sacrifice substrate.

35. The method of manufacturing a probe for testing a flat panel display device, according to claim 34, wherein, prior to the conductor formation step, the method further comprises a seed layer formation step of forming a seed layer on the upper portion of the sacrifice substrate.

36. The method of manufacturing a probe for testing a flat panel display device, according to claim 34, wherein, in the conductor formation step, the conductors and align keys are simultaneously formed, the align keys being in a certain distance apart from the conductors

37. The method of manufacturing a probe for testing a flat panel display device, according to claim 34, wherein, in the conductor formation step, before the conductors are formed, a seed layer is formed on an upper portion of the sacrifice substrate.

38. The method of manufacturing a probe for testing a flat panel display device, according to claim 34, wherein, in the dielectric formation step and the support member formation step, after the dielectric and the support member are formed, the dielectric and the support member are grinded.

39. A method of manufacturing a probe for testing a flat panel display device comprising: a first trench formation step of forming first trenches having bottoms being subjected to a rounding process by using a photolithography process and first and second etching processes; a conductor formation step of opening central portions including the first trenches by using a photolithography process and then burying a conductive material in the opened regions, thereby forming conductors; a dielectric formation step of forming a dielectric on an upper portion of each of the conductors by using a photolithography process and a dielectric film formation process; and a finishing process of removing the sacrifice substrate.

40. The method of manufacturing a probe for testing a flat panel display device, according to claim 39, wherein, after the first trench formation step prior to the conductor formation step, the method further comprises a seed layer formation step of forming a seed layer.

41. The method of manufacturing a probe for testing a flat panel display device, according to claim 37, wherein each of the first trenches which are subjected to the first etching process has a shape of a truncated pyramid or a truncated cone; wherein, each of the first trenches having a shape of a truncated pyramid or a truncated cone are further etched up to a predetermined depth by the second etching process and a bottom of each of the first trenches is subjected to a rounding process.

42. A method of manufacturing a probe sheet for testing a flat panel display device comprising step of: forming a first passivation film pattern on a sacrifice substrate, thereby defining regions where tips of a plurality of unit contact members are to be formed; forming trenches on the sacrifice substrate by performing an etching process using the first passivation film pattern as an etching mask; removing the first passivation film pattern; forming a second passivation film pattern on the sacrifice substrate where the first passivation film is removed, thereby defining regions where beam elements of the unit contact members are to be formed; forming beam elements of the unit contact members by forming a metallic film on the sacrifice substrate where the second passivation film pattern is formed; opening the beam elements of the unit contact members by removing the second passivation film pattern; slicing the sacrifice substrate, where the beam elements of the unit contact members are opened, in a predetermined size; locating a thin film having a predetermined size on the sliced sacrifice substrate, and attaching and fixing the beam elements of the unit contact members on the lower portion of the thin film; and opening the tips of the unit contact members by removing the sacrifice substrate where the thin film is attached and fixed.

43. The method of manufacturing a probe for testing a flat panel display device, according to claim 42, wherein the first and second passivation film patterns are formed by: a step of coating photoresist on the sacrifice substrate; and a step of exposing and developing the photoresist.

44. The method of manufacturing a probe for testing a flat panel display device, according to claim 42, wherein the thin film is made up of an epoxy or a parylene.

45. A method of manufacturing a probe by using a single sacrifice substrate comprising: a first trench formation step of forming first trenches on upper and lower planes of the single sacrifice substrate by using a photolithography process and etching process, wherein the single sacrifice substrate has a predetermined thickness; a conductor formation step of forming conductors by burying a conductive material in the first trenches; a second trench formation step of forming second trenches on the lower portions of the conductors by using a photolithography process and an etching process; a dielectric formation step of forming a dielectric by burying a dielectric material in the second trenches; a support member formation step of forming a support member on at least one plane of the upper and lower planes of the sacrifice substrate where the dielectric is formed; and a finishing step of removing the sacrifice substrate.

46. The method of manufacturing a probe by using a single sacrifice substrate according to claim 45, wherein the sacrifice substrate is a silicon wafer.

47. The method of manufacturing a probe by using a single sacrifice substrate according to claim 45, wherein the dielectric is formed by applying an epoxy in the trenches and then inserting and attaching ceramic plates in the first trenches before he epoxy is cured, wherein the ceramic plate are previously prepared in a size suitable for being inserted in the trenches.

48. The method of manufacturing a probe by using a single sacrifice substrate according to claim 45, wherein the dielectric is formed by inserting ceramic plates in the trenches and then by applying and attaching an epoxy in gaps formed between the trenches and the ceramic plates, wherein the ceramic plate are previously prepared in a size suitable for being inserted in the trenches.

49. The method of manufacturing a probe by using a single sacrifice substrate according to claim 45, wherein, in the conductor formation step, the conductors are formed by forming a seed layer above the sacrifice substrate and then performing an electrolytic plating process.

50. The method of manufacturing a probe by using a single sacrifice substrate according to claim 45, wherein the method further comprises a conductive layer formation step of forming an conductive layer by stacking a conductive material on upper planes of the conductors by using a plating process.

51. A method of manufacturing a probe by using a single sacrifice substrate comprising: a first passivation film formation step of forming a first passivation film above the single sacrifice substrate, wherein the single sacrifice substrate has a predetermined thickness, wherein the first passivation film pattern is used to form conductors; a upper conductor formation step of forming upper conductors by burying a conductive material in the first passivation film pattern; a second passivation film formation step of forming a second passivation film above the sacrifice substrate where the conductors are formed, wherein the second passivation film is used to form a support member; an upper support formation step of forming an upper support member in the second passivation film pattern; a trench formation step of forming trenches on a lower plane of the sacrifice substrate by using a photolithography process and an etching process to expose the upper conductors; a dielectric formation step of forming a dielectric by burying a dielectric material in the trenches; and a step of removing the sacrifice substrate.

52. The method of manufacturing a probe by using a single sacrifice substrate according to claim 51 , wherein, prior to the step of removing the sacrifice substrate, the method further comprises a lower conductor formation step of forming lower conductors by forming a third passivation film pattern above the dielectric which is formed in the dielectric formation step and then burying a conductive material in the third passivation film pattern; and wherein, after the lower conductor formation step, the method further comprises a lower support member formation step of forming a fourth passivation film pattern above the lower conductor and then forming a lower support member in the fourth passivation film pattern.

53. The method of manufacturing a probe by using a single sacrifice substrate according to claim 51 , wherein the sacrifice substrate is a silicon wafer.

54. The method of manufacturing a probe by using a single sacrifice substrate according to claim 51, wherein the dielectric is formed by applying an epoxy in the trenches and then inserting and attaching ceramic plates in the first trenches before the epoxy is cured, wherein the ceramic plate are previously prepared in a size suitable for being inserted in the trenches.

55. The method of manufacturing a probe by using a single sacrifice substrate according to claim 51 , wherein the dielectric is formed by inserting ceramic plates in the trenches and then by applying and attaching an epoxy in gaps formed between the trenches and the ceramic plates, wherein the ceramic plate are previously prepared in a size suitable for being inserted in the trenches.

56. The method of manufacturing a probe by using a single sacrifice substrate according to claim 51 , wherein, in the conductor formation step, the conductors are formed by forming a seed layer above the sacrifice substrate and then performing an electrolytic plating process.

57. The method of manufacturing a probe by using a single sacrifice substrate according to claim 51 , wherein the method further comprises a conductive layer formation step of forming a conductive layer by stacking a conductive material on upper planes of the conductors by using a plating process.

58. The method of manufacturing a probe by using a single sacrifice substrate according to claim 51 , wherein, in the support member formation step, trenches are formed by using a photolithography process and an etching process, and then a support material is applied in the trenches, thereby forming the support member.

59. A method of manufacturing a probe by using a single sacrifice substrate comprising: a first trench formation step of forming first trenches on a predetermined portion of the single sacrifice substrate, wherein the single sacrifice substrate are made up of a predetermined material and are subjected to a polishing process to have a predetermined thickness, wherein the trenches are used to form a dielectric; a dielectric formation step of forming the dielectric by burying a dielectric material in the first trenches; a conductor formation step of forming conductors by forming a passivation film pattern on upper and lower planes of the sacrifice substrate where the dielectric is formed and then burying a conductive material in the passivation film pattern; and a finishing step of removing the sacrifice substrate.

60. The method of manufacturing a probe by using a single sacrifice substrate according to claim 59, wherein the sacrifice substrate is a silicon wafer.

61. The method of manufacturing a probe by using a single sacrifice substrate according to claim 59, wherein the first trenches are formed by using a dry etching process.

62. The method of manufacturing a probe by using a single sacrifice substrate according to claim 59, wherein the first trenches are formed by using a dicing process.

63. The method of manufacturing a probe by using a single sacrifice substrate according to claim 59, wherein the dielectric is formed by applying an epoxy in the first trenches and then inserting and attaching ceramic plates in the first trenches before the epoxy is cured, wherein the ceramic plate are previously prepared in a size suitable for being inserted in the first trenches.

64. The method of manufacturing a probe by using a single sacrifice substrate according to claim 59, wherein the dielectric is formed by inserting ceramic plates in the first trenches and then by applying and attaching an epoxy in gaps formed between the first trenches and the ceramic plates, wherein the ceramic plate are previously prepared in a size suitable for being inserted in the first trenches.

65. The method of manufacturing a probe by using a single sacrifice substrate according to claim 59, wherein, in the conductor formation step, the conductors are formed by forming a seed layer above the sacrifice substrate and then performing an electrolytic plating process.

66. The method of manufacturing a probe by using a single sacrifice substrate according to claim 59, wherein the method further comprises a support member formation step of forming a support member on one plane of the upper and lower planes of the sacrifice substrate.

67. The method of manufacturing a probe by using a single sacrifice substrate according to claim 66, wherein, in the support member formation step, an epoxy is applied, and then a ceramic plate is attached on an upper plane of the epoxy.

68. The method of manufacturing a probe by using a single . sacrifice substrate according to claim 66, wherein, in the support member formation step, trenches are formed by using a photolithography process, and then a support material is applied in the trenches, thereby forming the support member.

69. The method of manufacturing a probe by using a single sacrifice substrate according to claim 59, wherein the method further comprises a conductive layer formation step of forming a conductive layer by stacking a conductive material on the upper planes of the conductors by using a plating process.

70. A method of manufacturing a probe by using a single sacrifice substrate comprising: a trench formation step of forming trenches having predetermined depths on a predetermined region of an upper plane of a single sacrifice substrate; a first passivation film pattern formation step of forming a first passivation film pattern on the sacrifice substrate where the trenches are formed, thereby opening the trenches; a trench burying step of burying a trench burying material into the trenches which are opened by the first passivation film pattern, wherein the trench burying material is removed by an etching process; a second passivation film pattern formation step of forming a second passivation film on upper and lower planes of the sacrifice substrate by using a photolithography process, wherein the second passivation film pattern is used to form conductors; a conductor formation step of forming conductors at specific locations which are defined by the second passivation film pattern; a third passivation film pattern formation step of forming a third passivation film pattern on the upper and lower planes of the sacrifice substrate where the conductors are formed, wherein the third passivation film pattern is used to form a support member; a support member formation step of forming a support member at specific locations which are defined by the third passivation film pattern; and a finishing step of removing portions of the sacrifice substrate partitioned by the trench burying material and then removing the trench burying material.

71. The method of manufacturing a probe by using a single sacrifice substrate according to claim 70, prior to forming the conductors, the method further comprises a planarization step of removing the passivation film patterns which are formed on the upper plane of the sacrifice substrate and the trench burying material which is protruded upwards from the sacrifice substrate by using a grinding process.

72. The method of manufacturing a probe by using a single sacrifice substrate according to claim 70, wherein, prior to forming the conductors on the lower plane of, the sacrifice substrate in the second passivation film pattern formation step, the method further comprises a planarization step of removing the sacrifice substrate by using a grinding process to expose the dielectric.

73. The method of manufacturing a probe by using a single sacrifice substrate according to claim 70, wherein the sacrifice substrate is made up of a ceramic material.

74. The method of manufacturing a probe by using a single sacrifice substrate according to claim 70, wherein the trenches are formed by a dicing process.

75. The method of manufacturing a probe by using a single sacrifice substrate according to claim 70, wherein the trench burying material is formed by an electrolytic plating process.

76. The method of manufacturing a probe by using a single sacrifice substrate according to claim 70, wherein the conductor formation step comprises a seed layer formation step of forming seed layers on the upper and lower planes of the sacrifice substrate prior to forming the conductors.

77. The method of manufacturing a probe by using a single sacrifice substrate according to claim 70, wherein the method further comprises a conductive layer formation step of stacking conductive layers on upper planes of the respective conductors by using a conductive material.

78. The method of manufacturing a probe by using a single sacrifice substrate according to claim 77, wherein, in the conductive layer formation step, the conductive material is stacked on upper planes of the conductors by a sputtering process.

79. The method of manufacturing a probe by using a single sacrifice substrate according to claim 70, wherein, in the finishing step, the trench burying material is selectively removed by a wet etching process.