WO2004053835A1

WO2004053835A1 - Improvements in correlation architecture

Info

Publication number: WO2004053835A1
Application number: PCT/AU2003/001602
Authority: WO
Inventors: Leslie Edward Doherty
Original assignee: Elvoice Pty Ltd
Priority date: 2002-12-09
Filing date: 2003-12-01
Publication date: 2004-06-24
Also published as: AU2003302778A1; RU2005108198A

Abstract

An architecture for correlation processing is described with improved efficiencies in both speed of operation and hardware resources; for correlation vectors of length k, only k multiplication and additions are required to implement the process. The same architecture can be adapted to perform the absolute magnitude difference function (AMDF) and can be configured for either cross-correlation or auto-correlation of time-series data. An improvement to an AMDF implementation is also disclosed whereby the second derivative of the AMDF output is used to select the best correlation index.

Description

IMPROVEMENTS IN CORRELATION ARCHITECTURE

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to correlation apparatus and methods including cross- correlators, auto-correlators and more particularly to architectures of correlators and methods of producing correlation vectors from numerical and symbolic data.

2. Description of the Related Art

Cross-correlation techniques are now used in many fields. In some cases the techniques are used to improve the quality of a signal corrupted by unwanted noise signals. In the majority of cases, however, cross-correlation is used to determine the time delay between two or more signals when the signal to noise ratio of the signals is poor. Auto-correlation is a similar process except that it is used to determine cyclic repetitions within the one signal or data stream and is often used for velocity or distance measurement. Correlation is a process designed to find the best agreement in two data sets. The technique generally used is to move two data sets relative to each other to find an alignment where the most corresponding elements in both data sets match each other. More often than not, from a correlation perspective it is not the content of the data that is important, but the relative position of matching parts of the data. For example, the outputs of two microphone sensors, given identical cable lengths, will be ahgned when a sound source is placed at an equal distance from both sensors. Sampled signals from other positions having unequal distances from the sensors will be misaligned in time according to the relative distances of the source from the two sensors. Some correlation method is used to measure the error and re-align the data. When an alignment with maximum agreement has been found, the direction of the signal can be ascertained. The direct correlation method performs a summation of the product of two time sampled data sets x and y: n+

Cn m ( ,y) =i k ∑ ^χ, ^χ y_1+m n>0; m=0,k-l t=n,

This direct correlation process chooses subsets of length k of : and y data sets starting at x_n and y_n for n = 1 to the length of the data - k. The y data is offset relative to the x data by m. For each correlation coefficient, y_n, m is systematically increased from 1 to k. The whole process is then repeated for n = 2, 3, and so on. This is very computationally intensive so in practice fast Fourier transform (FFT) methods are often used to perform correlation. For the direct method, k x k multiplication and addition operations are required for each data shift; even using the FFT correlation about 2k x Log₂ (2k) operations are required because the data has to be padded with k zeros to change the FFT process from a circular to a linear correlation. The absolute magnitude difference function (AMDF) can be used as an alternative to direct correlation by replacing the x, x y_1+m operation with | x, - y_1+m |. The AMDF was used historically because it was much faster to subtract than to multiply in primitive computers. Since the introduction of parallel multipliers, most digital signal processors (DSPs) multiply instructions are as fast as addition, therefore, for DSP implementations, there is no speed advantage in using the AMDF. However, the AMDF has an advantage that the correlation point is more sharply defined than in the other correlation methods.

Correlation may also be performed on single bit streams of digital data using the "exclusive or" logical function instead of the multiplication or AMDF.

SUMMARY OF THE INVENTION

The basic correlation process can be considered as the multiplication and addition of a number of elements :

Cι,ι = ^χι ^χ yι + ^χ2 ^χ y₂ +-..+ Xk ^χ yk Cι_j2 = ^χι ^χ y₂ + ^χ ₂ y₃ +...+ ^χ _k ^χ yk+ι

Cι,_k = ^χι x yk + ^χ ₂ yk+i +•••+ Xk x y +k-i and the next step in the process is:

C₂,ι = ^χ ₂ x y₂ + ^χ ₃ x y₃ +...+ ^χ _k+ι y C₂,₂ = ^χ ₂ x y₃ + x₃ x y +...+ X +ι x y_k+2 C_2Jk = x₂ x y_k+ι + x₃ x y_k+2 + ... + x_k+ι x y_k+k

An alternative view of this process is:

Cι,(i tok) C2_; i _{to k}) ••■ C ,(i tok) ^χι (yι, y2, , yk) X2 (y2, y3, ,yk+t) k (y , yk+ι_> ,y_k+k-t)

+ + +

X2 (y2, y3, ,yk+ι) X3 (y₃, y , ,y_k+2) ^χ _k+ι (y_k+ι, y_k+2, N_k+_k)

^χ (y_k, y_k+ι, ,yk+k-ι) ^χk+ι(y_k+t,y +2, ,y _+k) ^χ2k-ι fok, y2 +ι. ,y₂k+k-ι)

This alternative organization shows that the first element of the second correlation vector, C_2>ι= x₂(y₂, y_3> ,y_k+ι)_. is exactly the same as the second element of the first correlation vector, Cι_ι2. This redundancy is such that the first element of any correlation vector is contained within the last k-l previously calculated correlation vectors if they exist. For instance, the first element of C_k is exactly the same as the k* element of C_\ .

This invention is a new architecture for the practical implementation of correlation based on this alternative organization for the calculation of correlation or AMDF vectors so that the process requires as few as k operations. Practical advantages can be obtained by inverting the processing order of one of the data sets relative to the other and processing elements in the order x_n ^χy_n+k, x„_+] ^χy_n+k.ι , ... x_n+_k-ι xy_n-t - x-i+kxy-i- This alternative architecture uses two shift registers and the outputs from the sensors are clocked in from opposite directions. Numerically, this "reflex" correlation technique is performed between two vectors, one of which is a reflex translation of the original vector. This means that for each shift of the registers, only part of the correlation is done and the summations are done serially, rather than in parallel.

A number of shifts are required to complete a correlation and it is therefore necessary to have an accumulator or low pass filter for each element of the shift register. With this technique, if a correlation is present, the selection logic detects a consistent maximum at the output of one of the accumulators (or integrators). Reflex correlation is a continuous process and the selection logic may be used to track the correlation. If a low pass filter is used, its critical frequency is independent of k and can be adjusted to meet particular operational scenarios .

In the reflex correlation method both data sets are shifted simultaneously and because of this one set of comparisons is being missed for each shift. To ensure that no comparisons are missed and optimise the correlation result the correlation may also be performed simultaneously with neighbouring data (x_nxy--+_k. x--xy_n+ -ι- x-i+ixy-i+k-i- x-ι+ιxy-ι+k-2 ••• Xn+k-ixy-i-i- Xn+k-ixyn. n+_k yn)- This optimisation can be used to halve both the sampling rate and the number of shift register elements.

One problem when using the AMDF is that very low-level signals produce a low- level output that can be confused with a correlation indication. This problem can be overcome by using the second derivative of the AMDF output vector instead of the direct AMDF output. A practical implementation of this invention is also included in this specification.

BRIEF DESCRIPTION OF THE DRAWINGS

The following drawings are provided to clarify the detailed description of the preferred embodiments of the invention: Figure 1 is a block schematic illustrating the correlation process;

Figure 2 is a schematic block diagram of a digital accumulator;

Figure 3 is a block schematic of the preferred digital embodiment of the invention;

Figure 4 is a diagram demonstrating a method of reducing memory requirements;

Figure 5 is a block schematic illustrating the preferred analogue embodiment of the invention;

Figure 6 is a schematic diagram of the AMDF circuit and

Figure 4 is a circuit schematic of the double differentiator.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The overall architecture of a digital correlator implementation is shown in Figure 1. Sampled signals, X input 1 and Y input 2 are inputs to the correlator. Y input 2 is connected to the input of a shift register 3, which has multiple outputs 4 according to the number of operations required. The shift register 3 is shifted for each new input sample by the sample clock 5. The multiple shift register outputs 4 are correlated with X input 1 by the operation block 6. Operation block 6 may perform either a multiplication or, if the AMDF is required, a subtraction of X input 1 with each shift register output 4. For the AMDF, negating the resulting value if the subtraction result is negative generates the absolute value of the subtraction. The multiple operation block outputs 7 are fed into a multiple accumulator block 8 by the sample clock 5. There is an accumulator for operation block output 7 and each accumulator produces an output 9 that is an input to the selection logic 10. The selection logic 10 is generally application specific but often consists of a circuit or process that determines which of the multiple accumulator outputs 9 has the highest value and indicates the selection at C output 11. There are a number of identical accumulator circuits in the accumulator block 8 and the detail of one of these is shown in Figure 2. An output of the operation block 7 is input to the accumulator shift register 12 on each sample clock 5. The number of elements in the accumulator shift register 12 depends on the application, the geometry of the system and the frequency of the sample clock 5. Adder circuit 13 adds the same operation block output 7 to the accumulator shift register negated output 14. The resulting difference output 15 is added to the accumulator output 9 by a second adder 16. The second adder output 17 is input to register 18 at each sample clock 5.

Figure 3 illustrates an embodiment of this invention in the form of a digital reflex correlation apparatus that includes an X shift register 19. The multiple X shift register outputs 20 are input to the operation block 6 in such a way that the first X shift register output 20(1) and the last Y shift register output 4(n) are multiplied together or subtracted in the case of the AMDF. Similarly the X shift register output 20(2) and the last Y shift register output 4(n-l) are multiplied together, through to X shift register output 20(n) and the last Y shift register output 4(1). The remainder of the implementation, accumulators and selection logic 21 and C output 11, is identical to the implementation shown in Figure 1.

Digital correlation implementations with lengthy correlation vectors or accumulation over many samples require very large numbers of memory cells. Figure 4 demonstrates a method of reducing the memory requirements by performing the correlation twice. A primary correlation process 22 is performed as shown in Figure 3 but not including the accumulators and selection logic 21. The X input 1 is also connected through a delay 24 to the X input 25 of a delayed correlation process 23, which is the same process as the said primary correlation process 22. Similarly the Y input 2 is also connected through a delay 26, equal in length to delay 24, to the Y input 27 of the delayed correlation process 23. The correlation vector 7 of the primary correlation process is added to the accumulators 21 through adders 28 and the correlation vector 29 of the delayed correlation process 23. The outputs 30 of the adders 28 are accumulated through adders 16 and registers 18 to produce the accumulator vector output 9 which can then be used by the selection logic. The accumulation length is determined by the length of delays 24 and 25; these can be adjusted to suit the application.

An analogue reflex correlator implementation according to this invention using the AMDF is shown in Figure 5. The X shift register 20 is replaced by the X delay line 31 which has a number of progressive delayed outputs 31(1) to 31(n) and the Y shift register 4 is replaced by the Y delay line 32 which has a number of progressive delayed outputs 32(1) to 32(n). The AMDF logic 33, illustrated in Figure 5 converts the delayed outputs of the X shift register 31 and the Y shift register 32 into an AMDF output vector 34. Optionally, the double differentiator circuit 35, details of which are given in Figure 7, converts the output into the D2AMDF correlation vector output 36. The AMDF logic 33 consists of a number of identical circuits, one of which for arbitrary X delay line input (i) 31(i) is shown in Figure 6. X delay line input (i) 31(i) is buffered by an amplifier to ensure minimal delay line loading and Y delay line input (n-i- 1) 32(n-i-l) is similarly buffered. Detector circuit 33a(i) differentially amplifies the buffered signals to implement the AMDF and the low pass filter circuit 33b(i) operates as an accumulator to produce the AMDF output (i) 34 (i).

Figure 7 illustrates the operation of the double differentiator 35 detailing 2 of the several identical circuits used to differentiate AMDF outputs (i) 34 (i) to AMDF outputs (i+2) 34 (i+2). AMDF output (i) 34 (i) is differentially amplified with AMDF output (i+1) 34 (i+1) by amplifier 35a(i). Similarly AMDF output (i+1) 34 (i+1) is differentially amplified with AMDF output (i+2) 34 (i+2) by amplifier 35a(i+l). The differential outputs of amplifier 35a(i) and amplifier 35a(i+l) are in turn differentiated by amplifier 35b(i) to produce the D2AMDF output 27(i). It can be seen in Figure 7 that AMDF output (i+1) 34 (i+1) is connected to both differential amplifiers 35a(i) and 35a(i+l). All AMDF outputs except the first 34(1) and the last 34 (n) are connected in this way. The circuit connection to the previous stage is indicated by connector 37 and to the next stage by connector 38. Similarly differential amplifier output (i+1) 35a(i+l) is connected to both differential amplifiers 35b(i) and 35b(i+l). All differential amplifier outputs 35b are connected in this way. The circuit connection to the previous stage is indicated by connector 39 and to the next stage by connector 40.

Correlating one subsection of a data set with another subsection of the same data set performs auto-correlation, which is a method of detern-tining if there are cyclic repetitions in a waveform. Auto-correlation can be achieved using an embodiment of this invention. In Figure 1, if the X input 1 and the Y input 2 are connected together, either directly or through a delay circuit such as several shift register stages or a first-in-first-out register, the apparatus will perform an auto-correlation. To implement auto-correlation with the reflex correlation architecture shown in Figure 3, the last output of the X shift register 20(n) is connected to the Y input 2, either directly or through a delay circuit. With an analogue implementation of the invention as shown in Figure 5, connecting the end of the X delay line 31(n) to the Y input 2 can perform auto-correlation. To maintain the level through the Y delay line 32, the terminating resistor of X delay line 31 needs to be removed along with the source resistor at the beginning of the Y delay line 32. As with the other implementations, a fixed or variable delay may be inserted between the end of the X delay line 31(n) and the Y input 2. Alternative implementations include:

1. Application specific integrated circuit design with or without an embedded controller may be used to implement the correlator

2. Field programmable logic arrays or electrically programmable logic devices may be used to implement the digital circuits 3. Using acoustic wave delay lines and amplifiers to implement the analogue circuits

4. implementation by computer software.

Claims

CLAIMS What is claimed is:

1. An apparatus for processing a first signal and a second signal comprising: a means of delaying the first signal with a plurality of progressive delay stages, a means of delaying the second signal with an equal number of progressive delay stages as implemented for the first signal, for each delay stage a multiplier, one input of the said multiplier connected to the output of a first signal delay stage and the other input of the said multiplier connected to a second signal delay stage so that the outputs of the second signal delay stages are connected to the said multipliers in reverse delay order to outputs of the first signal delay stages, an accumulator for each of the said multipliers that integrates the output of the said multiplier for a period of time.

2. An apparatus according to claim 1 , wherein: for each delay stage except one a second multiplier, one input of the said second multiplier connected to the output of a first signal delay stage except the last first signal delay stage and the other input of the said second multiplier connected to a second signal delay stage so that the outputs of the second signal delay stages are connected to the said multipliers adjacent to the output of the second signal delay stage connected to the first multiplier, an accumulator for each of the second set of multipliers that integrates the output of the said multiplier for a period of time.

3. An apparatus for processing a first signal and a second signal comprising: a means of delaying the first signal with a plurality of progressive delay stages, a means of delaying the second signal with an equal number of progressive delay stages as are implemented for the first signal, for each first signal delay stage a means of performing the exclusive-or function between the output of the first signal delay stage and the output of a second signal delay stage so that the outputs of the second signal delay stages are processed in reverse delay order with outputs of the first signal delay stages, an accumulator for each of the said exclusive-or outputs that integrates the output of the said exclusive-or outputs for a period of time.

4. An apparatus according to claim 3, wherein: for each delay stage except one a second means of performing the exclusive-or function, one input of the second exclusive-or function connected to the output of a first signal delay stage except the last first signal delay stage and the other input of the said second exclusive-or function connected to a second signal delay stage so that the outputs of the second signal delay stages are connected to the said exclusive-or function adjacent to the output of the second signal delay stage connected to the first exclusive-or function, an accumulator for each of the second set of exclusive-or functions that integrates the second set of exclusive-or outputs for a period of time.

5. An apparatus for processing a first signal and a second signal comprising: a means of delaying the first signal with a plurality of progressive delay stages, a means of delaying the second signal with an equal number of progressive delay stages as are implemented for the first signal, for each first signal delay stage a means of subtracting the output of the first signal delay stage from the output of a second signal delay stage so that the outputs of the second signal delay stages are subtracted in reverse delay order to outputs of the first signal delay stages, an accumulator for each of the said delay stages which integrates the absolute value of the subtraction result for a period of time.

6. An apparatus according to claim 5, wherein: for each delay stage except one a second means of subtracting the output of a first signal delay stage except the last first signal delay stage from an output a second signal delay stage adjacent to the output of the second signal delay stage connected to the first means of subtracting, an accumulator for each of the second means of subtracting that integrates the output of the said second means of subtracting for a period of time.

7. An apparatus for processing a first signal and a second signal comprising: a means of performing the absolute magnitude difference function of the first and second signal, a means of differentiating the absolute magnitude difference function output to produce a first differential output and a means of differentiating the said first differential output.

8. An apparatus according to claim 1,2, 3 or 4, wherein: a means of delaying the first signal and connecting the delayed first signal output to the second signal input.

9. An apparatus according to claim 5 or 6, wherein: a means of delaying the first signal and connecting the delayed first signal output to the second signal input.

10. Two sets of apparatus according to claims 1 through 9, and with: a means of delaying the signals applied to the first apparatus before they are applied to the second apparatus and a means of subtracting the accumulated totals of the second apparatus from the accumulated totals of the first apparatus.

11. An apparatus according to claim 1 , 2, 3, 4, 7, 8 or 10 wherein: a means of comparing accumulator output levels and determining which accumulator output has the highest value.

12. An apparatus according to claim 5, 6, 9 or 10, wherein: a means of comparing accumulator output levels and determining which accumulator output has the lowest value.