WO2004053961A1 - Manufacturing process for a multilayer structure - Google Patents

Manufacturing process for a multilayer structure Download PDF

Info

Publication number
WO2004053961A1
WO2004053961A1 PCT/IB2003/006397 IB0306397W WO2004053961A1 WO 2004053961 A1 WO2004053961 A1 WO 2004053961A1 IB 0306397 W IB0306397 W IB 0306397W WO 2004053961 A1 WO2004053961 A1 WO 2004053961A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
level
sige
support substrate
implantation
Prior art date
Application number
PCT/IB2003/006397
Other languages
French (fr)
Inventor
Carlos Mazure
Original Assignee
S.O.I.Tec Silicon On Insulator Technologies
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by S.O.I.Tec Silicon On Insulator Technologies filed Critical S.O.I.Tec Silicon On Insulator Technologies
Priority to EP03789590A priority Critical patent/EP1568073A1/en
Priority to JP2004558309A priority patent/JP4762547B2/en
Priority to AU2003294170A priority patent/AU2003294170A1/en
Publication of WO2004053961A1 publication Critical patent/WO2004053961A1/en
Priority to US11/106,135 priority patent/US7510949B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Definitions

  • the target substrate 20 can be made of silicon.

Abstract

The present invention relates to a production process for a multilayer structure made of semiconductor materials, said structure comprising a substrate (20) made of a first semiconductor material and a superficial thin layer made of a second semiconductor material, the two semiconductor materials having substantially different lattice parameters, characterised in that the process comprises the following steps: -producing a layer (110) comprising said superficial thin layer on a support substrate (100), -creating an embrittlement zone in the ensemble (10) formed by said support substrate and said deposited layer, -bonding said ensemble with a target substrate (20), -detaching at the level of this embrittlement zone, -treating the surface of the resulting structure.

Description

MANUFACTURING PROCESS FOR A MULTILAYER STRUCTURE
The present invention relates to a manufacturing process for a multilayer structure made of semiconductor materials, said structure comprising a substrate made of a first semiconductor material and a superficial thin layer made of a second semiconductor material, the two semiconductor materials having substantially different lattice parameters.
Processes of this type are already known.
It is therefore known to produce structures comprising a substrate made of a material such as silicon, and a superficial thin layer made of a material such as silicon-germanium (SiGe) , or even germanium
(Ge) .
Patent application FR 0208600 in the name of the applicant relates to a process for producing a structure comprising a thin layer of semiconductor material from a wafer comprising a lattice parameter adaptation layer comprising an upper layer made of semiconductor material having a first lattice parameter, characterised in that it comprises the following stages: (a) growth on the upper layer of the adaptation layer of a film of semiconductor material having a second nominal lattice parameter substantially different to the first lattice parameter, with a sufficiently minimal thickness to keep the first lattice parameter of the upper layer of the underlying adaptation layer and therefore be strained,
(b) growth on the film of a relaxed layer of semiconductor material having a nominal lattice parameter substantially identical to the first lattice parameter,
(c) removal of at least a part of the wafer on the side of the adaptation layer relative to the relaxed layer comprising the following operations: • formation of an embrittlement zone to the side of the adaptation layer relative to the relaxed layer,
• power supply at the embrittlement zone to detach from the wafer a structure comprising the relaxed layer.
The process of this patent application therefore employs a layer transfer technique (in particular of the
SMARTCUT® type or the ELTRAN® type) to constitute the desired wafer.
And a starting element of this process is a wafer comprising a lattice parameter adaptation layer corresponding to a region of the wafer presenting on its surface a layer of substantially relaxed material, without a large number of structural defects, such as dislocations .
It is specified that relaxed layer is understood to mean any layer of a semiconductor material which has a non-strained crystallographic structure, that is, one which has a lattice parameter substantially identical to the nominal lattice parameter of the material making up the layer.
Inversely, a strained layer is referred to as any layer of a semiconductor material whereof the crystallographic structure is strained in traction or in compression during crystalline growth, such as epitaxy, obliging at least a lattice parameter to be substantially different to the nominal lattice parameter of this material. The process of patent application FR 0208600 constitutes an advantageous solution to constitute structures such as mentioned at the start of this text.
The object of the present invention is to provide a certain complement to the teaching of this patent application.
To attain this aim the invention proposes a production process for a multilayer structure made of semiconductor materials, said structure comprising a substrate made of a first semiconductor material and a superficial thin layer made of a second semiconductor material, the two semiconductor materials having substantially different lattice parameters, characterised in that the process comprises the following steps: • producing a layer comprising said superficial thin layer on a support substrate,
• creating an embrittlement zone in the ensemble formed by said support substrate and said deposited layer, • bonding said ensemble with a target substrate,
• detaching at the level of this embrittlement zone, • treating the surface of the resulting structure.
Other aspects, aims and advantages of the invention will emerge more clearly from the following description of the invention, given with reference to the attached diagrams, in which Figures la to If illustrate the principal steps for implementing an embodiment of the invention.
With reference firstly to Figure la, this shows a support substrate 100, on which a layer 105 (shown in hatching) has been deposited.
The support substrate 100 is made of a semiconductor material having a first lattice parameter. It can be made of silicon, for instance. The layer 105 is a layer made of a material having a second lattice parameter different to the first lattice parameter mentioned hereinabove.
The layer 105 can therefore be made of SiGe, or even of Ge . It is said that the layer 105 is deposited by a technique allowing:
• depositing of a desired thickness of a material whereof the lattice parameter is substantially different to the lattice parameter of the support substrate on which the deposit is made,
• while constituting a superficial layer of such a deposit which is virtually exempt from defects of dislocation type.
The document WO 00/15885 teaches for example a process allowing SiGe or Ge to be deposited on silicon. Such a deposit process can therefore for example be done according to a first mode in which monocrystalline Ge is deposited on a support substrate of monocrystalline silicon, by putting into effect the following steps:
• temperature stabilisation of the substrate of monocrystalline silicon at a first preset stabilised temperature of 400°C to 500°C, preferably 430°C to 460°C,
• chemical deposition in the steam phase (CVD) of Ge at said first preset temperature until a base layer of Ge is obtained on the support substrate of a preset thickness of less than a final desired thickness,
• increase of the temperature of the chemical deposition in the steam phase of the Ge from the first preset temperature to a second preset temperature ranging from 750°C to 850°C, preferably from 800°C to 850°C, and
• continuing chemical deposition in the steam phase of Ge at said second preset temperature until a final desired thickness is obtained for the layer of monocrystalline Ge .
Such a deposit process can also be carried out according to variants - for example those disclosed by the document WO 00/15885.
Other methods for obtaining a thin layer of relaxed SiGe or relaxed Ge, directly on a support substrate which can be made of silicon, are also feasible.
Reference could also be made to the publication
ΛStrain relaxation of pseudomorphic Sil-xGex/Si (100) heterostructures after hydrogen or helium ion implantation for virtual substrate fabrication', B.
Hollander et al, Nuclear Instrument and Methods in Physics Research B175-177 (2001) 357-367 which is incorporated by reference herein.
In such a process, the layer 110 is produced by making a strained layer, and by relaxation of this layer.
Thin layers of relaxed SiGe can also be obtained by techniques disclosed in the following documents, which are incorporated by reference as they disclose methods for obtaining such layers which can be carried out for the invention :
- "Development of a new type of SiGe thin strained relaxed buffer based on the incorporation of carbon containing layer", presented in the first SiGe Technology and Device Meeting (ISTDM, Nagoya, Japan, January 15-17, 2003,
- "Thin SiGe Buffers with High Ge content for n- Mosfets" (Lyutovich et al . Material Science & Engineering, B89 (2002), 341-345),
- "Relaxed SiGe buffers with thickness below 0.1 μm" (Bauer et al . - Thin Solid Films 369 (2000), 152-
156) .
Coming back to the process of the invention, in all cases a layer 110 which comprises the superficial thin layer of the structure to be produced has been created on the support substrate 100.
An intermediate wafer 10, comprising a layer 110 of SiGe (with the desired Si/Ge ratio) or of Ge on the support substrate 100, has thus been made.
The free surface of this layer 100 can be polished in order to allow the bonding of the intermediate wafer 10 which is to follow in the process. The surface roughness of the intermediate wafer 10 should indeed be no more than a few angstroms rms for such bonding.
An interface 105 is therefore defined between the layer 110 and the support 100.
It is specified that by using this type of deposit process, the defects of dislocation type have been confined to the region of the layer 110 which is adjacent to the interface 105. Confinement is understood to mean the majority of the defects of dislocation type located in said region. The rest of the layer 110 is not fully exempt from defects, but their concentration is compatible with microelectronic applications. Accordingly, this region of the layer 110 in which the defects of dislocation type are confined make up a lattice parameter adaptation layer, between the support substrate 100 made of silicon and the superficial region of the layer 110, which makes up in itself a layer of the wafer 10 made of Ge or relaxed SiGe.
And this layer of Ge or relaxed SiGe has a desired thickness following the deposit made at the beginning of the process. This desired thickness can be in particular of the order of 0.5 to 1 micron. With reference now to Figure lb, an embrittlement zone 120 is created in the thickness of the wafer 10.
This embrittlement zone can in particular be made by implantation of species through the layer 110.
The species implanted are one or several atomic or molecular species, e.g. hydrogen or helium ions or molecules . The implantation can also be a co-implantation of different species, e.g. hydrogen and helium. It is specified that in this text "implantation" covers as well such a co-implantation of at least two species. When the embrittlement zone is made by implantation, the implantation parameters can be defined so that the embrittlement zone is located in the support substrate 100, as illustrated in Figure lb.
It is also possible to define these parameters so that the embrittlement zone is located in the layer 110 itself (preferably in the region of this layer adjacent to the interface 105) .
It is specified that the embrittlement zone can also have been made by creating a porous region in the support substrate 100, before depositing the layer 110.
Next comes the wafer comprising its embrittlement zone, and this wafer is bonded to a target substrate 20.
The target substrate 20 can be made of silicon.
The face of the wafer 10 which is stuck onto the target substrate is that which corresponds to the relaxed surface of the layer 110.
To carry out this bonding, the surfaces have been cleaned prior to being placed in contact and an bonding layer has been optionally inserted in between these surfaces.
Also, an electrical insulating layer, for example an oxide, can have been inserted in between the wafer and the target substrate.
Such an oxide can originate from oxidation of the surface of the target substrate 20.
It can likewise originate from oxidation of the surface of the layer 110, if it is made of SiGe. If the layer 110 is made of Ge or SiGe, then it is also possible to associate an oxide layer to it prior to bonding, by oxide deposition.
The wafer and/or the target substrate can therefore be associated to an insulating layer, prior to bonding.
If required, the surface of one or both of the substrates to be bonded can be treated, in order to bring the surface roughness of these substrates down to values which favour bonding (i.e. not more than a few angstroms rms) .
Such surface treatment can be a polishing step.
After bonding, it is possible to proceed with classic thermal treatment for consolidation of the bonding interface. Next comes detachment at the level of the embrittlement interface, by thermal and/or mechanical power supply.
The result is a structure 30 comprising, as illustrated in Figure Id: • the target substrate 20,
• the layer 110,
• optionally residue of the support substrate 100.
In this structure, the layer 110 itself comprises: • a lattice parameter adaptation layer (part of the layer 110 which is adjacent to the residue of the support substrate 100) , and
• a relaxed layer of desired thickness.
In the event where the embrittlement zone has been constituted by implantation in the thickness of the
"lattice parameter adaptation layer" of layer 110, the resulting structure 30 does not comprise residue of the support substrate, and a part of the lattice parameter adaptation layer has been separated from this structure 30 during detachment.
In this case, the surface of the resulting structure is treated (Figure le) to improve the surface state of the layer 110.
This surface treatment can comprise polishing, as well as other types of treatment.
It is also possible to perform the implantation so as to obtain the embrittlement zone in the part of layer 110 which is relaxed.
In such case, the transferred layer does not comprise defaults such as dislocations (or only very few) , and the resulting structure after detachment can present a surface layer ( which comes from the relaxed part of layer 110) which does not need any additional treatment .
In the case where the embrittlement zone has been made up in the thickness of the support substrate 100 (by implantation or by a priori creation of a porous region) , the next step is selective attack of the residue of this support substrate.
This selective attack can be selective chemical etching, which attacks only the material of the support substrate.
Such etching can be done by a humid method (choice of an adapted etching solution) , or by a dry method (selective etching via energy plasma, or pulverisation) .
Such etching can be preceded by polishing. At the beginning of this selective attack, the free surface of the layer 110 is treated to remove the lattice parameter adaptation layer, corresponding to the part of this layer 110 in which the defects of dislocation type are confined.
Described hereinabove are two main variants for implementing the invention (creation of an embrittlement zone in the support substrate, and in the layer 110 respectively) .
In these two cases, the active layer of the final structure corresponds to the relaxed part of the layer 110. In accordance with a third main variant, the layer 110 is in reality constituted by different levels (or strata) , and this layer 110 has been created as follows :
• deposit of a first level, for example by a technique such as that disclosed by the document WO
00/15885 or by the reference B. Hollander et al mentioned above, or generally by any other known technique for producing a relaxed thin layer,
• deposit of a second level, constituting a stop layer for chemical attack,
• deposit of a third level corresponding to a relaxed layer to constitute the active layer of the final structure. Such deposition is done with a desired thickness for the active layer. The first level corresponds to the lattice parameter adaptation layer. It can be made of SiGe, or Ge.
The second level at the same time must:
• have good selectivity relative to the third level, vis-a-vis chemical attack (in this respect, different materials must be employed for levels 2 and 3) , and • not induce too significant a difference in terms of lattice parameter with the two levels surrounding it (in this respect, the materials of levels 1, 2 and 3 must not be too different) . For example, the following combinations could be created:
Material level 1 Material level 2 Materia 1 level 3
Ge SiGe (50/50) SiGe or Ge
SiGe strained SiGe or Si Ge
It is preferable for the layers of level 1 and 3 to be made from materials of the same nature, so that the layer of level 2, intercalated between these two layers, receives homogeneous constraints on its two faces .
In this case, the following materials will preferably be used:
Material level 1 Material level 2 Material level 3
Ge SiGe (50/50) Ge
SiGe strained SiGe Si
In this third variant, the same steps are followed for creating an embrittlement zone, bonding and detachment of the structure 30.
The embrittlement zone can therefore here again be located in the layer 110. In this case, it is preferably located in the thickness of the first level (in which it has been created by implantation) . To obtain the final structure two selective attacks are carried out: • a first selective attack for eliminating the residue of the first level. This attack can in particular be a chemical attack, thus justifying insertion of a level corresponding to a stop layer, • a second selective attack for eliminating the stop layer itself.
It is also possible to constitute the layer 110 with only two levels, whereof a first level such as described hereinabove and a second level resembling the levels 2 and 3 mentioned above.
In this case, the second level can for example be made of strained silicon, whereas the first level is made of SiGe or Ge .
And the second level thus makes up the active layer of the final structure, while the first level still constitutes a lattice parameter adaptation layer.
Still in this case, the following materials will be able to be used (this table, as with the preceding ones, is given by way of non-limiting example) :
Material level 1 Material level 2
Ge SiGe (50/50)
SiGe strained Si
In all cases, conventional surface treatment measures can be followed after the structure of Figure le has been produced.
The invention therefore enables multilayer structures to be produced which comprise for example a layer of Ge or SiGe on a silicon substrate.
It shall be noted that in the case of the invention, the adaptation layer of layer 110 does not present a concentration gradient in its thickness (e.g. a gradient of the concentration in Germanium if the adaptation layer is between a Si support substrate and a relaxed layer in Ge or SiGe with a given concentration of Ge) .
Conventional adaptation layers often present such a concentration gradient, which corresponds to a gradient of the lattice parameter in the adaptation layer.
But such adaptation layers with a concentration gradient are necessarily relatively thick (the more important the difference in lattice parameter on both sides of the adaptation layer, the thicker the adaptation layer) .
WO 02/15244 discloses an example of such traditional adaptation layer with a concentration gradient .
In the case of the invention, on the contrary, the adaptation layer can be very thin.
It is indeed reminded that the defects (e.g. dislocations) are confined to the region of the layer 110 which is adjacent to its interface 105 with the support substrate 100.
This specific aspect of the invention is advantageous (in comparison with known techniques, such as disclosed e.g. in WO 02/15244) .
An illustration of the advantages associated to this aspect is the fact that such thin adaptation layer makes it possible to create the embrittlement zone by implantation within the support substrate 100, by traversing the adaptation layer with the implanted species . This allows, after detachment and suppression of the remaining material (Si or other) of the support substrate 100, to obtain for the final structure a very good quality surface, without needing burdensome treatments for treating a splitted surface such as the one that would be obtained by detachment at an embrittlement zone located within the adaptation layer itself (which would be the case with the adaptation layers with gradient, which are too thick to be traversed by the implantation) .
It shall also be noted that the structures obtained by the present invention are examples of defects of dislocation type, even in an embedded region.
And the resulting structures can then be used to have supplementary layers, for example strained silicon, grow by epitaxy on the layer of SiGe or Ge .
In the case where the layer of level 2 is made of strained Si, it can be advantageous to make only a single selective attack in order to conserve a final structure consisting of a bi-layer of strained silicon -
SiGe on a silicon substrate.
In this case, the final structure preserves the stop layer.
Finally , it is also possible to deposit a layer of strained silicon on the layer of level 3 prior to the stage of bonding this structure onto the target substrate, so as to finally produce a structure comprising a layer of strained silicon on a silicon substrate.

Claims

1. A production process for a multilayer structure made of semiconductor materials, said structure comprising a substrate (20) made of a first semiconductor material and a superficial thin layer made of a second semiconductor material, the two semiconductor materials having substantially different lattice parameters, characterised in that the process comprises the following steps:
• producing a layer (110) comprising said superficial thin layer on a support substrate (100),
• creating an embrittlement zone in the ensemble (10) formed by said support substrate and said deposited layer,
• bonding said ensemble with a target substrate (20),
• detaching at the level of this embrittlement zone,
• treating the surface of the resulting structure .
2. The process as claimed in the preceding claim, characterised in that said step of producing a layer is made by epitaxy.
3. The process as claimed in the preceding claim, characterised in that said epitaxy is undertaken using the following steps:
• temperature stabilisation of the support substrate at a first preset stabilised temperature, • chemical deposition in the steam phase at said first preset temperature until a base layer is obtained on the support substrate of a preset thickness of less than a final desired thickness for said layer (110) comprising the superficial thin layer,
• increase of the temperature of the chemical deposition in the steam phase from the first preset temperature to a second preset temperature, and
• continuing chemical deposition in the steam phase at said second preset temperature until a final desired thickness is obtained for the layer.
4. The process as claimed in the preceding claim, characterised in that the first preset temperature is of the order of 400°C to 500°C, and the second preset temperature is of the order of 750°C to 850°C.
5. The process as claimed in the preceding claim, characterised in that the first preset temperature is of the order of 430°C to 460°C, and the second preset temperature is of the order of 800°C to 850°C.
6. The process as claimed in Claim 1, characterised in that said layer is produced by creating a strained layer and by relaxation of this layer.
7. The process as claimed in any one of the preceding claims, characterised in that said production of the embrittlement zone is carried out by implantation.
8. The process as claimed in the preceding claim, characterised in that the implantation is a co- implantation of at least two species.
9. The process as claimed in one of the two preceding claims, characterised in that said implantation is carried out between the production stage and the bonding stage.
10. The process as claimed in the preceding claim, characterised in that implantation is carried out so as to define the embrittlement zone in the thickness of the support substrate.
11. The process as claimed in Claim 9, characterised in that implantation is carried out so as to define the embrittlement zone in a region of the layer (110) created corresponding to a lattice parameter adaptation layer.
12. The process as claimed in Claim 9, characterised in that implantation is carried out so as to define the embrittlement zone in a region of the layer (110) created corresponding to a relaxed layer.
13. The process as claimed in any one of the preceding claims, characterised in that prior to bonding an electrically insulating layer was inserted between said ensemble (10) formed by the support substrate and the deposited layer, and the target substrate (20) .
14. The process as claimed in the preceding claim, characterised in that prior to bonding an electrically insulating layer was formed on the surface of said ensemble (10) formed by the support substrate and the deposited layer.
15. The process as claimed in any one of the two preceding claims, characterised in that prior to bonding an electrically insulating layer was formed on the target substrate.
16. The process as claimed in any one of the three preceding claims, characterised in that said electrically insulating layer is a layer of oxide.
17. The process as claimed in any one of the preceding claims, characterised in that the substrate
(20) of the multilayer structure is made of silicon.
18. The process as claimed in any one of the preceding claims, characterised in that the support substrate (100) is made of silicon.
19. The process as claimed in any one of the preceding claims, characterised in that the layer (110) created is made of SiGe or Ge .
20. The process as claimed in any one of the preceding claims, characterised in that when the layer is being formed a level is created corresponding to a stop layer for chemical attack during the surface treatment stage.
21. The process as claimed in the preceding claim, characterised in that when the layer is being formed three levels are formed corresponding to the following:
• Level 1: lattice parameter adaptation layer,
• Level 2: stop layer,
• Level 3: active layer of the structure to be obtained.
22. The process as claimed in the preceding claim, characterised in that the materials of the layers corresponding to said three levels constitute one of the following combinations:
Material level 1 Material level 2 Materia .1 level 3
Ge SiGe (50/50) SiGe or Ge
SiGe strained SiGe or Si Ge
23. The process as claimed in the preceding claim, characterised in that the materials of the layers corresponding to said three levels constitute one of the following combinations:
Material level 1 Material level 2 Material level 3
Ge SiGe (50/50) Ge
SiGe strained SiGe Si
24. The process as claimed in any one of the four preceding claims, characterised in that the stop layer is preserved in the final structure.
25. The process as claimed in Claim 19, characterised in that when the layer is being formed two levels are formed corresponding respectively to: • Level 1: lattice parameter adaptation layer,
• Level 2: active layer of the structure to be obtained.
26. The process as claimed in the preceding claim, characterised in that the materials of the layers corresponding to said three levels constitute one of the following combinations :
Material level 1 Material level 2
Ge SiGe (50/50)
SiGe strained Si
PCT/IB2003/006397 2002-07-09 2003-12-05 Manufacturing process for a multilayer structure WO2004053961A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP03789590A EP1568073A1 (en) 2002-12-06 2003-12-05 Manufacturing process for a multilayer structure
JP2004558309A JP4762547B2 (en) 2002-12-06 2003-12-05 Manufacturing method of multilayer structure
AU2003294170A AU2003294170A1 (en) 2002-12-06 2003-12-05 Manufacturing process for a multilayer structure
US11/106,135 US7510949B2 (en) 2002-07-09 2005-04-13 Methods for producing a multilayer semiconductor structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR02/15499 2002-12-06
FR0215499A FR2848334A1 (en) 2002-12-06 2002-12-06 Multi-layer structure production of semiconductor materials with different mesh parameters comprises epitaxy of thin film on support substrate and adhesion on target substrate

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/615,259 Continuation-In-Part US6953736B2 (en) 2002-07-09 2003-07-09 Process for transferring a layer of strained semiconductor material

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/106,135 Continuation US7510949B2 (en) 2002-07-09 2005-04-13 Methods for producing a multilayer semiconductor structure

Publications (1)

Publication Number Publication Date
WO2004053961A1 true WO2004053961A1 (en) 2004-06-24

Family

ID=32320086

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2003/006397 WO2004053961A1 (en) 2002-07-09 2003-12-05 Manufacturing process for a multilayer structure

Country Status (8)

Country Link
EP (1) EP1568073A1 (en)
JP (1) JP4762547B2 (en)
KR (1) KR100797210B1 (en)
CN (1) CN1720605A (en)
AU (1) AU2003294170A1 (en)
FR (1) FR2848334A1 (en)
TW (1) TWI289880B (en)
WO (1) WO2004053961A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006140453A (en) * 2004-11-10 2006-06-01 Sharp Corp Formation of low-defect germanium film by direct wafer bonding
US9097987B2 (en) 2002-11-12 2015-08-04 Asml Netherlands B.V. Lithographic apparatus and device manufacturing method

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101960604B (en) * 2008-03-13 2013-07-10 S.O.I.Tec绝缘体上硅技术公司 Substrate having a charged zone in an insulating buried layer
CN105023991B (en) * 2014-04-30 2018-02-23 环视先进数字显示无锡有限公司 A kind of manufacture method of the LED laminated circuit boards based on inorganic matter
CN108231695A (en) * 2016-12-15 2018-06-29 上海新微技术研发中心有限公司 Composite substrate and method for manufacturing the same
CN107195534B (en) * 2017-05-24 2021-04-13 中国科学院上海微系统与信息技术研究所 Ge composite substrate, substrate epitaxial structure and preparation method thereof

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
WO2000015885A1 (en) * 1998-09-10 2000-03-23 France Telecom Method for obtaining a monocrystalline germanium layer on a monocrystalline silicon substrate, and resulting products
EP1050901A2 (en) * 1999-04-30 2000-11-08 Canon Kabushiki Kaisha Method of separating composite member and process for producing thin film
US6323108B1 (en) * 1999-07-27 2001-11-27 The United States Of America As Represented By The Secretary Of The Navy Fabrication ultra-thin bonded semiconductor layers
WO2002015244A2 (en) * 2000-08-16 2002-02-21 Massachusetts Institute Of Technology Process for producing semiconductor article using graded expitaxial growth
WO2002071491A1 (en) * 2001-03-02 2002-09-12 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed cmos electronics and high speed analog circuits
US20020168864A1 (en) * 2001-04-04 2002-11-14 Zhiyuan Cheng Method for semiconductor device fabrication
WO2003017358A1 (en) * 2001-08-17 2003-02-27 Rosemount Aerospace, Inc. Method of manufacturing a semiconductor structure comprising sic on an oxide layer

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3607194B2 (en) * 1999-11-26 2005-01-05 株式会社東芝 Semiconductor device, semiconductor device manufacturing method, and semiconductor substrate
FR2809867B1 (en) * 2000-05-30 2003-10-24 Commissariat Energie Atomique FRAGILE SUBSTRATE AND METHOD FOR MANUFACTURING SUCH SUBSTRATE
JP2003249641A (en) * 2002-02-22 2003-09-05 Sharp Corp Semiconductor substrate, manufacturing method therefor and semiconductor device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
WO2000015885A1 (en) * 1998-09-10 2000-03-23 France Telecom Method for obtaining a monocrystalline germanium layer on a monocrystalline silicon substrate, and resulting products
EP1050901A2 (en) * 1999-04-30 2000-11-08 Canon Kabushiki Kaisha Method of separating composite member and process for producing thin film
US6323108B1 (en) * 1999-07-27 2001-11-27 The United States Of America As Represented By The Secretary Of The Navy Fabrication ultra-thin bonded semiconductor layers
WO2002015244A2 (en) * 2000-08-16 2002-02-21 Massachusetts Institute Of Technology Process for producing semiconductor article using graded expitaxial growth
WO2002071491A1 (en) * 2001-03-02 2002-09-12 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed cmos electronics and high speed analog circuits
US20020168864A1 (en) * 2001-04-04 2002-11-14 Zhiyuan Cheng Method for semiconductor device fabrication
WO2003017358A1 (en) * 2001-08-17 2003-02-27 Rosemount Aerospace, Inc. Method of manufacturing a semiconductor structure comprising sic on an oxide layer

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
TARASCHI GIANNI, LANGDO THOMAS A. ET AL.: "Relaxed SiGe-on-insulator fabricated via wafer bonding and etch back", JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY - B, vol. 20, no. 2, March 2002 (2002-03-01), pages 725 - 727, XP002259419 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9097987B2 (en) 2002-11-12 2015-08-04 Asml Netherlands B.V. Lithographic apparatus and device manufacturing method
JP2006140453A (en) * 2004-11-10 2006-06-01 Sharp Corp Formation of low-defect germanium film by direct wafer bonding
JP4651099B2 (en) * 2004-11-10 2011-03-16 シャープ株式会社 Fabrication of low defect germanium films by direct wafer bonding.

Also Published As

Publication number Publication date
AU2003294170A1 (en) 2004-06-30
EP1568073A1 (en) 2005-08-31
KR100797210B1 (en) 2008-01-22
TW200511393A (en) 2005-03-16
KR20050084146A (en) 2005-08-26
JP4762547B2 (en) 2011-08-31
CN1720605A (en) 2006-01-11
FR2848334A1 (en) 2004-06-11
JP2006509361A (en) 2006-03-16
TWI289880B (en) 2007-11-11

Similar Documents

Publication Publication Date Title
US5877070A (en) Method for the transfer of thin layers of monocrystalline material to a desirable substrate
US7338883B2 (en) Process for transferring a layer of strained semiconductor material
US7202124B2 (en) Strained gettering layers for semiconductor processes
KR100886620B1 (en) Method for manufacturing compound material wafers and method for recycling a used donor substrate
US7018910B2 (en) Transfer of a thin layer from a wafer comprising a buffer layer
TWI307935B (en) Treatment of a removed layer of si1-ygey
KR100749041B1 (en) Semiconductor substrate and process for producing it
WO2000019499A1 (en) Method for the transfer of thin layers of monocrystalline material onto a desirable substrate
US7001826B2 (en) Wafer with a relaxed useful layer and method of forming the wafer
KR101122859B1 (en) Method of detaching a thin film at moderate temperature after co-implantation
JP4817342B2 (en) Manufacturing method of SOI type wafer
JP2008530780A (en) Strain relaxation of strained layer using molten layer
KR20210144772A (en) Method for making thin layers of ferroelectric materials
JP2006505928A5 (en)
WO2005031852A1 (en) Indirect bonding with disappearance of the bonding layer
JP5113182B2 (en) Improved method for transfer of thin layers formed in substrates with defect clusters
JP3864495B2 (en) Manufacturing method of semiconductor substrate
WO2005067053A1 (en) Process for producing soi wafer
WO2004053961A1 (en) Manufacturing process for a multilayer structure
JP3707200B2 (en) Manufacturing method of semiconductor substrate
US7510949B2 (en) Methods for producing a multilayer semiconductor structure
KR20070090251A (en) Formation and treatment of a sige structure
US20050023610A1 (en) Semiconductor-on-insulator structure having high-temperature elastic constraints
JPH10335617A (en) Manufacture of semiconductor substrate
KR20070019697A (en) Thermal treatment of a semiconductor layer

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): BW GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 11106135

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 2003789590

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 1020057010109

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 2004558309

Country of ref document: JP

Ref document number: 20038A52499

Country of ref document: CN

WWP Wipo information: published in national office

Ref document number: 1020057010109

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 2003789590

Country of ref document: EP