WO2004057668A2 - Electronic device and method of manufacturing same - Google Patents
Electronic device and method of manufacturing same Download PDFInfo
- Publication number
- WO2004057668A2 WO2004057668A2 PCT/IB2003/005976 IB0305976W WO2004057668A2 WO 2004057668 A2 WO2004057668 A2 WO 2004057668A2 IB 0305976 W IB0305976 W IB 0305976W WO 2004057668 A2 WO2004057668 A2 WO 2004057668A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- chip
- substrate
- interconnections
- conductive interconnections
- conductive
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/19011—Structure including integrated passive components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
Definitions
- the second metal interconnection comprises a solder having a reflow temperature that is lower than the reflow temperature of the first metal interconnection.
- solder ball it is possible to place a solder ball on the substrate while the second conductive interconnection is covered by a layer of Au. It is alternatively possible to attach the solder ball to the second conductive interconnection of the first chip while an acid flux treatment is given during the application, or a flux layer is already present on the substrate. However, it is to be preferred to attach a solder ball to the second conductive interconnection while a solder dot having solder particles and acid in a 50-50 ratio is deposited on the substrate.
- Fig. 2 shows the final device 100 once the encapsulation 80 has been applied.
- the encapsulation comprises a passivating material known per se such as a glass-filled epoxy, a polyimide or another resin that has been chosen for the desired coefficient of expansion by the expert.
- the substrate 10 is embedded in the encapsulation 80 here while also the openings 18 are filled and the contact surfaces on the second side 12 can be reached for external contacting.
- Solder balls also of the lead-free type, may be applied to this after which the device as a whole is ready to be placed on a carrier such as a printed circuit board. From the outside the device 100 then does not differ from any other semiconductor device.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2003285638A AU2003285638A1 (en) | 2002-12-20 | 2003-12-10 | Electronic device and method of manufacturing same |
EP03778630A EP1579502A2 (en) | 2002-12-20 | 2003-12-10 | Electronic device and method of manufacturing same |
US10/539,367 US7196416B2 (en) | 2002-12-20 | 2003-12-10 | Electronic device and method of manufacturing same |
JP2004561851A JP2006511080A (en) | 2002-12-20 | 2003-12-10 | Electronic device and manufacturing method thereof |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP02080664.2 | 2002-12-20 | ||
EP02080664 | 2002-12-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2004057668A2 true WO2004057668A2 (en) | 2004-07-08 |
WO2004057668A3 WO2004057668A3 (en) | 2004-08-12 |
Family
ID=32668879
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2003/005976 WO2004057668A2 (en) | 2002-12-20 | 2003-12-10 | Electronic device and method of manufacturing same |
Country Status (7)
Country | Link |
---|---|
US (1) | US7196416B2 (en) |
EP (1) | EP1579502A2 (en) |
JP (1) | JP2006511080A (en) |
KR (1) | KR20050095586A (en) |
CN (1) | CN100382298C (en) |
AU (1) | AU2003285638A1 (en) |
WO (1) | WO2004057668A2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006080350A (en) * | 2004-09-10 | 2006-03-23 | Denso Corp | Semiconductor device, and mounting structure thereof |
EP1771880A1 (en) * | 2004-07-19 | 2007-04-11 | Koninklijke Philips Electronics N.V. | Electronic device comprising an integrated circuit and a capacitance element |
US8067830B2 (en) | 2007-02-14 | 2011-11-29 | Nxp B.V. | Dual or multiple row package |
CN102623441A (en) * | 2011-01-28 | 2012-08-01 | 三星电子株式会社 | Semiconductor device and method of fabricating the same |
EP3163609A4 (en) * | 2014-07-29 | 2017-06-28 | Huawei Technologies Co. Ltd. | Chip integration module, chip encapsulation structure and chip integration method |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040262368A1 (en) * | 2003-06-26 | 2004-12-30 | Haw Tan Tzyy | Ball grid array solder joint reliability |
US7160758B2 (en) * | 2004-03-31 | 2007-01-09 | Intel Corporation | Electronic packaging apparatus and method |
US7183622B2 (en) * | 2004-06-30 | 2007-02-27 | Intel Corporation | Module integrating MEMS and passive components |
US7560309B1 (en) * | 2005-07-26 | 2009-07-14 | Marvell International Ltd. | Drop-in heat sink and exposed die-back for molded flip die package |
TWI324378B (en) * | 2005-10-21 | 2010-05-01 | Freescale Semiconductor Inc | Method of making semiconductor package with reduced moisture sensitivity |
ES2904591T3 (en) | 2006-03-30 | 2022-04-05 | Esco Group Llc | wear set |
US7622811B2 (en) * | 2006-09-14 | 2009-11-24 | Stats Chippac, Inc. | Semiconductor assembly with component attached on die back side |
US7863738B2 (en) * | 2007-05-16 | 2011-01-04 | Texas Instruments Incorporated | Apparatus for connecting integrated circuit chip to power and ground circuits |
US20090230524A1 (en) * | 2008-03-14 | 2009-09-17 | Pao-Huei Chang Chien | Semiconductor chip package having ground and power regions and manufacturing methods thereof |
US7859120B2 (en) * | 2008-05-16 | 2010-12-28 | Stats Chippac Ltd. | Package system incorporating a flip-chip assembly |
US20100044850A1 (en) | 2008-08-21 | 2010-02-25 | Advanced Semiconductor Engineering, Inc. | Advanced quad flat non-leaded package structure and manufacturing method thereof |
US8124447B2 (en) | 2009-04-10 | 2012-02-28 | Advanced Semiconductor Engineering, Inc. | Manufacturing method of advanced quad flat non-leaded package |
US20110163430A1 (en) * | 2010-01-06 | 2011-07-07 | Advanced Semiconductor Engineering, Inc. | Leadframe Structure, Advanced Quad Flat No Lead Package Structure Using the Same, and Manufacturing Methods Thereof |
MY165522A (en) * | 2011-01-06 | 2018-04-02 | Carsem M Sdn Bhd | Leadframe packagewith die mounted on pedetal that isolates leads |
US9034692B2 (en) | 2011-03-21 | 2015-05-19 | Stats Chippac Ltd. | Integrated circuit packaging system with a flip chip and method of manufacture thereof |
JP2015046501A (en) * | 2013-08-28 | 2015-03-12 | 三菱電機株式会社 | Semiconductor device |
AU2018421974B2 (en) * | 2018-05-04 | 2022-03-31 | Telefonaktiebolaget Lm Ericsson (Publ) | A cavity-backed antenna element and array antenna arrangement |
CN109904139B (en) * | 2019-03-08 | 2020-12-25 | 中国科学院微电子研究所 | Large-size chip system packaging structure with flexible adapter plate and manufacturing method thereof |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0311747A (en) * | 1989-06-09 | 1991-01-21 | Toshiba Corp | Semiconductor device |
JPH08125112A (en) * | 1994-10-26 | 1996-05-17 | Hitachi Ltd | Semiconductor device and production thereof |
WO1997020347A1 (en) * | 1995-11-28 | 1997-06-05 | Hitachi, Ltd. | Semiconductor device, process for producing the same, and packaged substrate |
JP3545171B2 (en) * | 1997-07-31 | 2004-07-21 | 三洋電機株式会社 | Semiconductor device |
US6225699B1 (en) * | 1998-06-26 | 2001-05-01 | International Business Machines Corporation | Chip-on-chip interconnections of varied characteristics |
DE10041695A1 (en) * | 2000-08-24 | 2002-03-07 | Orient Semiconductor Elect Ltd | Capsule construction for flip-chip connected to chip and base has chip stuck onto base using surface adhesive flat encapsulation method, auxiliary chip stuck on to form housing |
US6337510B1 (en) * | 2000-11-17 | 2002-01-08 | Walsin Advanced Electronics Ltd | Stackable QFN semiconductor package |
KR100731007B1 (en) * | 2001-01-15 | 2007-06-22 | 앰코 테크놀로지 코리아 주식회사 | stack-type semiconductor package |
US20020105789A1 (en) * | 2001-02-02 | 2002-08-08 | Siliconware Precision Industries Co., Ltd. | Semiconductor package for multi-chip stacks |
SG95637A1 (en) * | 2001-03-15 | 2003-04-23 | Micron Technology Inc | Semiconductor/printed circuit board assembly, and computer system |
US6967395B1 (en) * | 2001-03-20 | 2005-11-22 | Amkor Technology, Inc. | Mounting for a package containing a chip |
US6441483B1 (en) * | 2001-03-30 | 2002-08-27 | Micron Technology, Inc. | Die stacking scheme |
US7064009B1 (en) * | 2001-04-04 | 2006-06-20 | Amkor Technology, Inc. | Thermally enhanced chip scale lead on chip semiconductor package and method of making same |
TW495943B (en) * | 2001-04-18 | 2002-07-21 | Siliconware Precision Industries Co Ltd | Semiconductor package article with heat sink structure and its manufacture method |
US6610560B2 (en) * | 2001-05-11 | 2003-08-26 | Siliconware Precision Industries Co., Ltd. | Chip-on-chip based multi-chip module with molded underfill and method of fabricating the same |
KR101009818B1 (en) * | 2002-04-11 | 2011-01-19 | 엔엑스피 비 브이 | Carrier, method of manufacturing a carrier and an electronic device |
US6987032B1 (en) * | 2002-07-19 | 2006-01-17 | Asat Ltd. | Ball grid array package and process for manufacturing same |
-
2003
- 2003-12-10 KR KR1020057011243A patent/KR20050095586A/en not_active Application Discontinuation
- 2003-12-10 EP EP03778630A patent/EP1579502A2/en not_active Withdrawn
- 2003-12-10 JP JP2004561851A patent/JP2006511080A/en active Pending
- 2003-12-10 CN CNB2003801064782A patent/CN100382298C/en not_active Expired - Fee Related
- 2003-12-10 WO PCT/IB2003/005976 patent/WO2004057668A2/en active Application Filing
- 2003-12-10 AU AU2003285638A patent/AU2003285638A1/en not_active Abandoned
- 2003-12-10 US US10/539,367 patent/US7196416B2/en not_active Expired - Fee Related
Non-Patent Citations (1)
Title |
---|
None |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1771880A1 (en) * | 2004-07-19 | 2007-04-11 | Koninklijke Philips Electronics N.V. | Electronic device comprising an integrated circuit and a capacitance element |
JP2006080350A (en) * | 2004-09-10 | 2006-03-23 | Denso Corp | Semiconductor device, and mounting structure thereof |
US8067830B2 (en) | 2007-02-14 | 2011-11-29 | Nxp B.V. | Dual or multiple row package |
CN102623441A (en) * | 2011-01-28 | 2012-08-01 | 三星电子株式会社 | Semiconductor device and method of fabricating the same |
CN102623441B (en) * | 2011-01-28 | 2016-06-15 | 三星电子株式会社 | Semiconductor device and manufacture method thereof |
EP3163609A4 (en) * | 2014-07-29 | 2017-06-28 | Huawei Technologies Co. Ltd. | Chip integration module, chip encapsulation structure and chip integration method |
US11462520B2 (en) | 2014-07-29 | 2022-10-04 | Huawei Technologies Co., Ltd. | Chip integration module, chip package structure, and chip integration method |
Also Published As
Publication number | Publication date |
---|---|
US7196416B2 (en) | 2007-03-27 |
JP2006511080A (en) | 2006-03-30 |
CN100382298C (en) | 2008-04-16 |
US20060099742A1 (en) | 2006-05-11 |
CN1726591A (en) | 2006-01-25 |
WO2004057668A3 (en) | 2004-08-12 |
KR20050095586A (en) | 2005-09-29 |
EP1579502A2 (en) | 2005-09-28 |
AU2003285638A1 (en) | 2004-07-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7196416B2 (en) | Electronic device and method of manufacturing same | |
JP3233535B2 (en) | Semiconductor device and manufacturing method thereof | |
US6555917B1 (en) | Semiconductor package having stacked semiconductor chips and method of making the same | |
KR100559664B1 (en) | Semiconductor package | |
US8748229B2 (en) | Manufacturing method including deformation of supporting board to accommodate semiconductor device | |
US6621172B2 (en) | Semiconductor device and method of fabricating the same, circuit board, and electronic equipment | |
JP4505983B2 (en) | Semiconductor device | |
US6518666B1 (en) | Circuit board reducing a warp and a method of mounting an integrated circuit chip | |
KR100543729B1 (en) | RF IC package for improving heat transfer rate and for reducing height and size of package and assembly method thereof | |
US5742100A (en) | Structure having flip-chip connected substrates | |
US20060035408A1 (en) | Methods for designing spacers for use in stacking semiconductor devices or semiconductor device components | |
KR100559652B1 (en) | Semiconductor device and method for manufacturing method thereof | |
US6548326B2 (en) | Semiconductor device and process of producing same | |
EP1662566A2 (en) | Semiconductor device and method of fabricating the same | |
EP1745510A2 (en) | A method of assembly and assembly thus made | |
CN111128763A (en) | Manufacturing method of chip packaging structure | |
US6383840B1 (en) | Semiconductor device, method of manufacture thereof, circuit board, and electronic device | |
US20110147905A1 (en) | Semiconductor device and method of manufacturing the same | |
US20050035465A1 (en) | Semiconductor device and method of manufacturing the same, circuit board and electronic instrument | |
JPH113969A (en) | Substrate component laminated with chip component | |
US6410364B1 (en) | Semiconductor device, method of connecting a semiconductor chip, circuit board, and electronic equipment | |
US10115673B1 (en) | Embedded substrate package structure | |
JP6495130B2 (en) | Semiconductor device and manufacturing method thereof | |
KR19990056739A (en) | Semiconductor chip mounting method | |
KR100403352B1 (en) | Solder paste wafer level package and fabrication method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): BW GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2003778630 Country of ref document: EP |
|
ENP | Entry into the national phase |
Ref document number: 2006099742 Country of ref document: US Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 10539367 Country of ref document: US |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1020057011243 Country of ref document: KR Ref document number: 20038A64782 Country of ref document: CN |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2004561851 Country of ref document: JP |
|
WWP | Wipo information: published in national office |
Ref document number: 2003778630 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 1020057011243 Country of ref document: KR |
|
WWP | Wipo information: published in national office |
Ref document number: 10539367 Country of ref document: US |