WO2004061859A3 - Stochastic assembly of sublithographic nanoscale interfaces - Google Patents

Stochastic assembly of sublithographic nanoscale interfaces Download PDF

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Publication number
WO2004061859A3
WO2004061859A3 PCT/US2003/023198 US0323198W WO2004061859A3 WO 2004061859 A3 WO2004061859 A3 WO 2004061859A3 US 0323198 W US0323198 W US 0323198W WO 2004061859 A3 WO2004061859 A3 WO 2004061859A3
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WO
WIPO (PCT)
Prior art keywords
nanoscale wires
controllable
wires
regions
sublithographic
Prior art date
Application number
PCT/US2003/023198
Other languages
French (fr)
Other versions
WO2004061859A2 (en
Inventor
Andre Dehon
Charles M Lieber
Patrick D Lincoln
John Savage
Original Assignee
California Inst Of Techn
Harvard College
Stanford Res Inst Int
Univ Brown
Andre Dehon
Charles M Lieber
Patrick D Lincoln
John Savage
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by California Inst Of Techn, Harvard College, Stanford Res Inst Int, Univ Brown, Andre Dehon, Charles M Lieber, Patrick D Lincoln, John Savage filed Critical California Inst Of Techn
Priority to AU2003298529A priority Critical patent/AU2003298529A1/en
Priority to JP2005508519A priority patent/JP2006512782A/en
Priority to EP03796281A priority patent/EP1525585A2/en
Publication of WO2004061859A2 publication Critical patent/WO2004061859A2/en
Publication of WO2004061859A3 publication Critical patent/WO2004061859A3/en

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/02—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/02—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
    • G11C13/025—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N99/00—Subject matter not provided for in other groups of this subclass
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/71—Three dimensional array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/81—Array wherein the array conductors, e.g. word lines, bit lines, are made of nanowires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/70—Nanostructure
    • Y10S977/762—Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/902—Specified use of nanostructure
    • Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
    • Y10S977/943—Information storage or retrieval using nanostructure

Abstract

A method for controlling electric conduction on nanoscale wires is disclosed.The nanoscale wires are provided with controllable regions axially and/or radially distributed. Controlling those regions by means of microscale wires or additional nanoscale wires allows or prevents electric conduction on the controlled nanoscale wires. The controllable regions are of two different types.For example, a first type of controllable region can exhibit a different dopingfrom a second type of controllable region. The method allows one or more of a set of nanoscale wires, packed at sublithographic pitch, to be independentlyselected.
PCT/US2003/023198 2002-07-25 2003-07-24 Stochastic assembly of sublithographic nanoscale interfaces WO2004061859A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU2003298529A AU2003298529A1 (en) 2002-07-25 2003-07-24 Stochastic assembly of sublithographic nanoscale interfaces
JP2005508519A JP2006512782A (en) 2002-07-25 2003-07-24 Stochastic assembly of sub-pattern transfer nanoscale interfaces
EP03796281A EP1525585A2 (en) 2002-07-25 2003-07-24 Stochastic assembly of sublithographic nanoscale interfaces

Applications Claiming Priority (14)

Application Number Priority Date Filing Date Title
US39894302P 2002-07-25 2002-07-25
US60/398,943 2002-07-25
US40039402P 2002-08-01 2002-08-01
US60/400,394 2002-08-01
US41517602P 2002-09-30 2002-09-30
US60/415,176 2002-09-30
US42901002P 2002-11-25 2002-11-25
US60/429,010 2002-11-25
US44199503P 2003-01-23 2003-01-23
US60/441,995 2003-01-23
US46535703P 2003-04-25 2003-04-25
US60/465,357 2003-04-25
US46738803P 2003-05-02 2003-05-02
US60/467,388 2003-05-02

Publications (2)

Publication Number Publication Date
WO2004061859A2 WO2004061859A2 (en) 2004-07-22
WO2004061859A3 true WO2004061859A3 (en) 2005-02-03

Family

ID=32097212

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/US2003/023199 WO2004034467A2 (en) 2002-07-25 2003-07-24 Sublithographic nanoscale memory architecture
PCT/US2003/023198 WO2004061859A2 (en) 2002-07-25 2003-07-24 Stochastic assembly of sublithographic nanoscale interfaces

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PCT/US2003/023199 WO2004034467A2 (en) 2002-07-25 2003-07-24 Sublithographic nanoscale memory architecture

Country Status (7)

Country Link
US (2) US6900479B2 (en)
EP (3) EP1525585A2 (en)
JP (2) JP2005539404A (en)
AT (2) ATE421147T1 (en)
AU (2) AU2003298529A1 (en)
DE (2) DE60325903D1 (en)
WO (2) WO2004034467A2 (en)

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AU2003298530A8 (en) 2004-05-04
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WO2004034467A3 (en) 2004-08-26
JP2005539404A (en) 2005-12-22
ATE421147T1 (en) 2009-01-15
AU2003298529A8 (en) 2004-07-29
US20040113138A1 (en) 2004-06-17
ATE360873T1 (en) 2007-05-15
AU2003298529A1 (en) 2004-07-29
EP1525586A2 (en) 2005-04-27
JP2006512782A (en) 2006-04-13
DE60313462T2 (en) 2008-01-03
US6963077B2 (en) 2005-11-08
EP1525586B1 (en) 2007-04-25
EP1758126A2 (en) 2007-02-28
DE60313462D1 (en) 2007-06-06
EP1525585A2 (en) 2005-04-27
US20040113139A1 (en) 2004-06-17
WO2004061859A2 (en) 2004-07-22
AU2003298530A1 (en) 2004-05-04
US6900479B2 (en) 2005-05-31
WO2004034467A2 (en) 2004-04-22

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