WO2004062062A1 - System and method for interleaving point-of-load regulators - Google Patents

System and method for interleaving point-of-load regulators Download PDF

Info

Publication number
WO2004062062A1
WO2004062062A1 PCT/US2003/035515 US0335515W WO2004062062A1 WO 2004062062 A1 WO2004062062 A1 WO 2004062062A1 US 0335515 W US0335515 W US 0335515W WO 2004062062 A1 WO2004062062 A1 WO 2004062062A1
Authority
WO
WIPO (PCT)
Prior art keywords
voltage
phase
supply system
power supply
voltage regulator
Prior art date
Application number
PCT/US2003/035515
Other languages
French (fr)
Inventor
Alain Chapuis
Original Assignee
Power-One Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Power-One Limited filed Critical Power-One Limited
Priority to AU2003291357A priority Critical patent/AU2003291357A1/en
Priority to KR1020047007979A priority patent/KR100785941B1/en
Priority to EP20030768750 priority patent/EP1576711B1/en
Publication of WO2004062062A1 publication Critical patent/WO2004062062A1/en

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/22Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/285Single converters with a plurality of output stages connected in parallel
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J1/00Circuit arrangements for dc mains or dc distribution networks
    • H02J1/08Three-wire systems; Systems having more than three wires
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J1/00Circuit arrangements for dc mains or dc distribution networks
    • H02J1/10Parallel operation of dc sources
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J1/00Circuit arrangements for dc mains or dc distribution networks
    • H02J1/10Parallel operation of dc sources
    • H02J1/102Parallel operation of dc sources being switching converters
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/02Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1584Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel

Definitions

  • the present invention relates generally to power supply circuits and more particularly, to voltage regulator systems for use in power supply systems.
  • Multi-phase regulators are commonly used in generating a single output voltage.
  • a common control circuit drives several out- phased power circuits.
  • the power stages typically consist of several chokes connected to a single section of output capacitors.
  • the benefits of the conventional multi-phase design is the reduction of bpth input reflected ripple currents and output ripple current in the output capacitor resulting from the displaced phasing of the choke currents.
  • the output voltage is normally fed back into the master pulse width modulation (PWM) controller.
  • PWM controller compensates the loop and distributes a pulse width modulated signal out-phased to each of the several output power stages over multiple lines.
  • multi-phase regulators have a low output capacitor ripple and low input reflected ripple current.
  • conventional multi-phase regulators also have a number of disadvantages.
  • Conventional multi-phase systems are limited to a single common input voltage and a single common output voltage.
  • conventional multi-phase systems include a multi-phase PWM controller that controls multiple slave power stages, these systems also require multiple control lines running from the controller to the slave power stages.
  • the phase location is fixed and is not adjustable from the master controller.
  • the present invention is directed toward a multi-phase regulator system that is configured to provide multiple independent output voltages or currents and programmable phase offsets via a single control line.
  • the present system and method provides an array of point-of-load (POL) regulators in which the switching cycle of each regulator is displaced with respect to those of other regulators in the array to reduce the aggregate reflected ripple and noise of the input, output, or both.
  • POL point-of-load
  • Each regulator in the array is provided with an address.
  • a serial data-line may write the phase spacing to each addressable POL in the array. In an alternative exemplary embodiment, the phase spacing is determined based on the address.
  • the system and method of the present invention provides phase displacement of the regulators without being limited by the input and output voltages of each of the regulators in the array.
  • the array may operate in a phase displaced mode with only a single control line and without the need for separate controllers or multiple control lines.
  • the present system and method further provides for the control of independent single phase regulators. Therefore, because the phase displacement is independent of the input voltage, the system and method may provide multiple independent input voltages within the array.
  • the array is capable of being configured as a single output multi-phase system. The array does not require a master controller because the control system is distributed in all regulators. Thus, the above functionality is independent of the regulator topology. Moreover, the array may utilize a single control line, instead of multiple control lines.
  • the present invention removes the restriction of a common output voltage. In addition, the common input voltage does not restrict the operation of the array.
  • the phasing determination is either made at a system controller or at each of the power stages. Furthermore, the control loops are closed locally at each power stage, rather than centrally.
  • the present invention reduces the system noise generated by the array of POL regulators and thereby reduces the filter requirements to manage such noise by out-phasing the switching of the regulators.
  • a further advantage is that the phase location of the start of each POL switching cycle is programmable and thereby provides flexibility and adjustability. For example, this flexibility in phase location of each regulator can be used to optimize the noise performance of the array.
  • the addressable nature of the regulators provides an additional degree of flexibility for the array.
  • Figure 1 is an exemplary block diagram of one embodiment of an array of point- of-load (POL) regulators in accordance with the present invention.
  • POL point- of-load
  • Figure 2 illustrates another exemplary embodiment of the POL regulator array.
  • Figure 3 is an exemplary embodiment of communication over a single-wire bus.
  • Figure 4 illustrates an exemplary embodiment of a data transmission scheme utilized by the POL regulators and controller.
  • Figure 5 illustrates an exemplary embodiment of a voltage regulator.
  • Figure 6 illustrates an exemplary embodiment of a clock recovery circuit.
  • Figure 7 illustrates an exemplary embodiment of a delay bus.
  • Figure 8 illustrates an exemplary embodiment of the timing diagram of the clock recovery circuit of Figure 6.
  • FIG. 9-11 illustrate exemplary embodiments of the timing diagrams and input ripple of the POL regulator array. It should be noted that the figures are not drawn to scale and that elements of similar structures or functions are generally represented by like reference numerals for illustrative purposes throughout the figures. It also should be noted that the figures are only intended to facilitate the description of the preferred embodiments of the present invention. The figures do not describe every aspect of the present invention and do not limit the scope of the invention.
  • the present invention is directed to a system and method for providing interleaving point-of-load (POL) regulators such that each regulator's switching cycle is phase displaced with respect to those of other regulators in the array. As a result, the aggregate reflected ripple and noise of the input, output or both is reduced.
  • POL point-of-load
  • Each regulator in the array is associated with an address.
  • a serial data-line may write the phase spacing programmed to each addressable POL regulator in the array. Alternatively, the phase spacing data may be provided from memory. Accordingly, the present invention permits phase displacement of the regulators without limiting the input and output voltages of each of the regulators in the array.
  • the array of regulators may also operate in a phase displaced mode with only a single control line.
  • FIG. 1 shows an exemplary embodiment of a point-of load (POL) regulator array system of the present invention, shown generally at 10.
  • the system 10 includes an array of POL regulators or converters 20 and a controller 5.
  • POL regulators 20 and controller 15 may be configured to form a board level distributed power architecture, for example.
  • Controller 15 and POL regulators 20 communicate via interface 25.
  • Interface 25, shown as SYNC/DATA line 25, may be a one line, bidirectional interface.
  • Each POL regulator 20 is associated with a selected address.
  • the address configuration for each POL regulator 20 specifies an ID for that POL regulator 20.
  • a selected POL regulator 20, shown as POL regulator 20A may be designated as the Master POL regulator 20. This designation may be based on a selected address, e.g., the least significant address or Address 0.
  • the Master POL regulator 20A generates the SYNC portion of the SYNC/DATA line signal 25. Controller 15 and all other POL regulators 20 synchronize to this SYNC signal. Any other device connected to the SYNC/DATA line 25 may provide the clock, e.g., POL regulator 20, controller 15 or an additional external clock generator (not shown).
  • each POL regulator 20 may operate at its optimal frequency depending on its input voltage and output voltage setting instead of operating at the same frequency as every other POL regulator in the system.
  • Each POL regulator 20 may receive input voltage Vin 45.
  • the output voltage Vo of each POL regulator 20 may be provided to devices connected to system 10 in any suitable manner. In the exemplary embodiment shown in Figure 1 , for example, the output of two or more POL regulators 20 may be connected in parallel. In this embodiment, an additional current share line 40 may be used to ensure an equal load share between the POL regulators 20.
  • controller 15 and POL regulators 20 communicate via interface 25, e.g., a one line, bi-directional SYNC/DATA line. Controller 15 may transmit data through SYNC/DATA line 25 to each of the POL regulators 25. Controller 15 may set the specific phase displacement for each of the POL regulators 25 through this interface. Controller 15 may set the phase displacements for each POL regulator 25 to minimize the switching noise on the intermediate bus voltage. Alternatively or additionally, controller 15 may set the phase displacements to minimize the noise on the output of the POL regulators 25 connected in parallel. Controller 15 may set the phase displacement statically, e.g., the phase displacement is programmed or set in a permanent or semi-permanent manner.
  • controller 15 may adapt the phase displacement dynamically to minimize the noise in the system when specific system parameters change.
  • system parameters may include, for example, load currents, output or input voltages or the number of POL regulators (e.g., the phase displacement may be dynamically adapted when POL regulators are added or removed physically or enabled or disabled electrically).
  • system 10 may be configured in a variety of modes.
  • system 10 may include a common input bus with several voltage outputs.
  • system 10 may include several input buses and several voltage outputs.
  • system 10 may include a common input bus and a single voltage output.
  • the single voltage output may be a multi-phase voltage output.
  • FIG. 2 illustrates another exemplary embodiment of the present invention.
  • the POL regulator array indicated generally at 200, includes POL regulators 220 and SYNC line 225.
  • the outputs of POL regulators 235A and 235B are connected in parallel to provide output voltage 230 (Vo1).
  • the outputs of POL regulators 235C and 235D provide output voltage 230B (Vo2).
  • Current share lines 240A and 240B are provided for these two pairs, respectively, to provide an equal load share.
  • the input voltage 245 (Vin) is provided to each POL regulator 220.
  • system 200 does not include a controller.
  • a selected POL regulator 235A acts as the Master POL regulator and generates the SYNC portion of the SYNC line signal. All other POL regulators 220 synchronize to this signal. Any internal or external device connected to SYNC line 225 may provide the clock.
  • each POL regulator 235 may be used to determine the phase displacement of the POL regulator 235.
  • the address of the POL regulators 235 may be used to determine the phase displacement of the pulse width modulated (PWM) signals of each POL regulator 235 as compared to the SYNC line 225.
  • PWM pulse width modulated
  • the address of each POL regulator 20 may set the initial phase displacement and this phase displacement can be overwritten or changed by the controller 15.
  • the addresses for the POL regulators 235 do not need to be unique. For instance, POL regulators 235 with the same address will be phase synchronized.
  • each POL regulator 235 may be chosen to minimize a specific design parameter by wiring or programming the address via input 235 accordingly.
  • POL regulator 220A (“POL 0”) may have a phase displacement of 0°
  • POL regulator 220B (“POL 1”) may have a phase displacement of 180°
  • POL regulator 220C (“POL 2”) may have a phase displacement of 90°
  • POL regulator 220D (“POL 3”) may have a phase displacement of 270°.
  • the POL regulators connected in parallel, as shown in Figure 2 will have a 180° phase shift, which is optimal for the outputs of system 200.
  • the pairs are 90° phase shifted with respect to each other, which therefore provides an optimal current distribution for the input of system 200.
  • Figure 3 illustrates one exemplary method of communicating over a single-wire serial bus, e.g., the SYNC/DATA line.
  • a transmission line 340 is created by propagating a clock signal 300 over the serial bus.
  • the clock signal 300 synchronizes the various ' communicating devices (e.g., the POL regulators and the controller) and creates a series of clock cycles 310, each one including a data bit 320. This data bit 320 allows the various communicating devices to transmit a single bit of data for every clock cycle 310.
  • each communicating device transmits data by leaving/pulling the data bit 320 high or low (i.e., binary one or zero).
  • Figure 3 is not intended to limit the present invention, but to provide an example as to how communication can occur over a single- wire serial bus.
  • Figure 4 illustrates one exemplary method of transmitting information between the controller and at least one POL regulator.
  • a forty-two bit communication cycle 450 can be used to transmit initial-configuration data, fault- monitoring data, unique ID data or any combination thereof.
  • the forty-two bit transmission cycle 450 includes a four bit start sequence 410, a sixteen bit (with parity) address set 420, an eight bit (with parity) command set 430, a first acknowledgement bit 440, an eight bit (with parity) data set 460, and a second acknowledge bit 470.
  • An additional bit 450 has been added to ensure that the command set 430 is executed before the data set 460 is provided.
  • the communication cycle 450 depicted in Figure 4 is not intended to limit the present invention, but to illustrate how information can be transmitted over a serial bus. Therefore, communication cycles containing more or less information or bits are within the spirit and scope of the present invention.
  • the first and second acknowledgement bits 440 and 470 are used to acknowledge the reception of the command set 430 and the data set 460, respectively. It should be appreciated that the device responsible for the providing the first and second acknowledgement bits 440 and 470 varies depending upon whether the information is being sent to or from the POL regulator (e.g., whether the information is being written, read, or provided).
  • the command set 430, data set 460 and address set 420 enable the controller and the POL regulators to write, read and provide data.
  • the command set 430 is used to identify whether and what the controller is writing (e.g., writing to the status register), the controller is reading (e.g., reading the status register), or the POL regulator is providing (e.g., providing status register information).
  • the address set 420 is used to identify the POL regulator(s) that is being written to or read or the POL regulator that is providing information.
  • the data set 460 is used to identify the actual data that is being written, read, or provided.
  • the start sequence 410 and address set 420 are used, in part, to identify the sender of the information.
  • the controller uses a different start sequence 410 than the POL regulators.
  • the controller can determine, by reading the start sequence 410 of the communication cycle 450 being transmitted, whether a POL regulator is also attempting to send a communication cycle 450 at the same time.
  • each POL regulator has a different address set 420.
  • a POL regulator can determine, by reading the start sequence 410 and address set 420 of the communication cycle 450 being transmitted, whether another POL regulator or the controller is also attempting to send a communication cycle 450 at the same time.
  • sequencing data is used to allocate or arbitrate bus use. It should be appreciated that the sequence data can either be stored (or hard wired) as a default value or provided as initial-configuration data and stored in the storage device (e.g., a sequencing configuration register).
  • FIG. 5 shows an exemplary embodiment of a voltage regulation module, indicated generally at 500, according to the present invention.
  • the voltage regulation module 500 has an input stage and an output stage accessible via an input terminal 510 and an output terminal 520 with a return terminal 530.
  • voltage regulation module 500 is designed to convert the input voltage Vin between the terminals 510 and 530 into an output voltage Vo between the terminals 520 and 530.
  • the voltage regulation module 500 includes a L/C low pass filter, indicated generally at 560, driven by switching elements Q1 and Q2.
  • a non-inverting driver 540 and an inverting driver 545 are provided for power switches Q1 and Q2, respectively, and these drivers are both controlled or activated by a pulse width modulated control signal generated by the PWM signal generator or pulse width modulator 570, discussed below.
  • the voltage regulation module also includes an output voltage or power train controller 550.
  • the output voltage controller 550 includes a feedback controller 565 and pulse width modulator 570 that is synchronized to the TRIGGER signal 575.
  • the module 500 further includes a clock recovery circuit 580, a serial interface handler 585 and a memory block 590.
  • the clock recovery circuit 580 generates the phase shifted, synchronized TRIGGER signal 575.
  • the serial interface handler 585 decodes any messages that are sent over the SYNC/DATA line 595 and stores the data in the memory block 590, e.g. the required phase displacement.
  • the clock recovery circuit 580 and serial interface handler 585 receive address data via input 555.
  • the memory 590 may be initialized with predefined data. This data can either be hardwired or programmed by an OTP (one time programmable) method or any other method.
  • OTP one time programmable
  • the TRIGGER signal 575 is sent to the voltage regulator's pulse width modulator 570 to start a new PWM control signal used to control the drivers 540 and 545 associated with the power switches Q1 and Q2.
  • FIG. 6 shows an exemplary embodiment of the clock recovery circuit, indicated generally at 600, of the present invention.
  • clock recovery circuit 600 receives a SYNC/DATA signal 605 and generates a phase-shifted synchronized TRIGGER signal 630.
  • Clock recovery circuit 600 includes an inverter 610, a phase detector (PD) 615, a filter 620, a ring oscillator 625, a delay bus 635, a multiplexer 640 and a frequency divider 680.
  • Clock recovery circuit 600 may access a memory location 645.
  • this memory location may be a memory location in the voltage regulator (e.g., memory 590 as shown in Figure 5).
  • Inverter 610 inverts SYNC/DATA line signal 605.
  • Phase detector 615 generates a signal which is proportional to the frequency and phase difference of the positive slopes of signals S1 (generated by the inverter 610) and S2 (generated by the frequency divider 680).
  • Filter 620 filters the phase difference and controls the ring- oscillator frequency and phase.
  • Ring oscillator 625 is an oscillator that may generate a delay bus 635. The signals of delay bus 635 are equally spaced to each other (see Figure 7, described below).
  • the DO signal is used as the TRIGGER signal 630 to synchronize the PWM generator of the power train feedback loop (see, for example, Figure 5).
  • Multiplexer 640 selects, based on the settings in memory block 645, at least one output of delay bus 635.
  • Frequency divider 680 divides the frequency of the output of multiplexer 640 according the settings in memory block 645 and feeds the signal (shown in Figure 6 as S2) back to phase detector 615.
  • the components of clock recovery circuit 600 form a phase locked loop.
  • the phases of the signals S1 and S2 are aligned in steady state.
  • the DO positive transition can be shifted relative to the negative transition of the SYNC/DATA line 605.
  • the DO positive transition defines the starting point of the PWM signal in the power train, e.g., power train 550 shown in Figure 5.
  • a selected voltage regulator 500 may serve as the master voltage regulator.
  • the master voltage regulator includes the master clock generator to generate the synchronization signal, as discussed above.
  • the clock recovery circuit 600 of the master voltage regulator may be configured to act as the master clock generator.
  • this clock recovery circuit 600 may be configured to serve as the master clock generator by opening the phase locked loop of the clock recovery circuit and using the ring oscillator 625 as a free-running oscillator.
  • Figure 7 shows an exemplary embodiment of the signals generated by the delay bus 635 as shown in Figure 6.
  • the ring oscillator 625 generates a delay bus consisting of 2 m signals, wherein each signal is equally delayed by trj. Note that the delay bus need not generate 2 X number of signals.
  • the phase lead or phase displacement may accordingly be expressed as:
  • Phi ⁇ [value (address)]/(maximum number of POL regulators) ⁇ x 360°
  • the value (address) corresponds to the address of the selected POL regulator or delay bus signal.
  • the denominator corresponds to the maximum number of POL regulators in the system that may be addressed, e.g., 32.
  • Figure 8 shows an exemplary embodiment of the various timing signals of the voltage regulation module and clock recovery circuit of the present invention.
  • m 4.
  • the multiplexer 640 (shown in figure 6) selects signal D3 from delay bus 635.
  • the clock recovery circuit 600 aligns the selected delay bus signal D3 to the SYNC/DATA line.
  • the delay bus signal DO e.g., the SYNC signal
  • the positive slope of the DO signal e.g., the TRIGGER signal
  • the PWM signal has the same phase lead as the DO signal.
  • the phase lead of the PWM signal is therefore selectable by the value stored in memory.
  • Figures 9-11 illustrate exemplary embodiments of timing diagrams and simplified input ripple waveforms.
  • Figure 9 shows an in-phase set of waveforms.
  • four downstream buck converter signals i(i1), i(i2), i(i3) and i(i4) which correspond to the input current of regulators with 3.3 V at 20 A, 2.5 V at 30 A, 1.8 V at 20 A and 1.2 V at 20 A, respectively, are shown.
  • Signal i(co) is the ripple current in an input capacitor.
  • the resulting capacitor ripple voltage is 1.198 V.
  • Figure 10 illustrates the effects of out-phasing. In this case, the regulators are equally out-phased. It may be noted that the first two waveforms overlap.
  • the resulting capacitor ripple voltage in this case is 406 mV.
  • Figure 11 shows an even more advantageous phasing distribution that results from choosing voltage and current dependant phase displacements. Accordingly, the capacitor ripple voltage is lower. In this case, the capacitor ripple is 263 mV. This shows clearly the advantage of being able to choose the phase displacement according the operating point of the system to reduce system noise. It may be understood that further optimization is possible. Thus, phase displacing these pulses may result in lowered capacitor ripple or, alternatively, lower amounts of bus capacitance may be required to support a given ripple voltage.

Abstract

A system and method for providing interleaving point-of-load (POL) regulators (20A-20D) such that each regulator's switching cycle is phase displaced with respect to those of other POL regulators in the array is disclosed. As a result, the aggregate input and/or output reflected ripple and noise of the input, output, or both is reduced. Each regulator in the array is associated with an unique address (ADDR). A serial data-line (25) writes the phase spacing programmed to each addressable POL regulator in the array. The present invention permits phase displacement of POL regulators without limitation to the input and output voltages of each of the regulators in the array. The array of POL regulators may also operate in a phase displaced mode with only a single control line. The need for separate controllers and multiple control lines is thereby eliminated.

Description

SYSTEM AND METHOD FOR INTERLEAVING POINT-OF-LOAD REGULATORS
BACKGROUND OF THE INVENTION
1. Field Of The Invention
The present invention relates generally to power supply circuits and more particularly, to voltage regulator systems for use in power supply systems.
2. Background Of The Invention
Multi-phase regulators are commonly used in generating a single output voltage. For conventional multi-phase systems, a common control circuit drives several out- phased power circuits. The power stages typically consist of several chokes connected to a single section of output capacitors. The benefits of the conventional multi-phase design is the reduction of bpth input reflected ripple currents and output ripple current in the output capacitor resulting from the displaced phasing of the choke currents. In this type of arrangement, the output voltage is normally fed back into the master pulse width modulation (PWM) controller. In turn, the PWM controller compensates the loop and distributes a pulse width modulated signal out-phased to each of the several output power stages over multiple lines.
As discussed above, in comparison to single-phase systems, multi-phase regulators have a low output capacitor ripple and low input reflected ripple current. Unfortunately, conventional multi-phase regulators also have a number of disadvantages. Conventional multi-phase systems are limited to a single common input voltage and a single common output voltage. Because conventional multi-phase systems include a multi-phase PWM controller that controls multiple slave power stages, these systems also require multiple control lines running from the controller to the slave power stages. Moreover, the phase location is fixed and is not adjustable from the master controller. In view of the foregoing, it is believed that a need exists for an improved multiphase regulator system that overcomes the aforementioned obstacles and deficiencies of currently-available multi-phase regulator systems. More particularly, a need exists for a flexible multi-phase regulator system for use in power supply circuits.
SUMMARY OF THE INVENTION The present invention is directed toward a multi-phase regulator system that is configured to provide multiple independent output voltages or currents and programmable phase offsets via a single control line. The present system and method provides an array of point-of-load (POL) regulators in which the switching cycle of each regulator is displaced with respect to those of other regulators in the array to reduce the aggregate reflected ripple and noise of the input, output, or both. Each regulator in the array is provided with an address. A serial data-line may write the phase spacing to each addressable POL in the array. In an alternative exemplary embodiment, the phase spacing is determined based on the address. Accordingly, the system and method of the present invention provides phase displacement of the regulators without being limited by the input and output voltages of each of the regulators in the array. Moreover, the array may operate in a phase displaced mode with only a single control line and without the need for separate controllers or multiple control lines.
The present system and method further provides for the control of independent single phase regulators. Therefore, because the phase displacement is independent of the input voltage, the system and method may provide multiple independent input voltages within the array. In an alternative exemplary embodiment, the array is capable of being configured as a single output multi-phase system. The array does not require a master controller because the control system is distributed in all regulators. Thus, the above functionality is independent of the regulator topology. Moreover, the array may utilize a single control line, instead of multiple control lines. The present invention removes the restriction of a common output voltage. In addition, the common input voltage does not restrict the operation of the array. The phasing determination is either made at a system controller or at each of the power stages. Furthermore, the control loops are closed locally at each power stage, rather than centrally. The present invention reduces the system noise generated by the array of POL regulators and thereby reduces the filter requirements to manage such noise by out-phasing the switching of the regulators. A further advantage is that the phase location of the start of each POL switching cycle is programmable and thereby provides flexibility and adjustability. For example, this flexibility in phase location of each regulator can be used to optimize the noise performance of the array. The addressable nature of the regulators provides an additional degree of flexibility for the array.
Other aspects and features of the present invention will become apparent from consideration of the following description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is an exemplary block diagram of one embodiment of an array of point- of-load (POL) regulators in accordance with the present invention.
Figure 2 illustrates another exemplary embodiment of the POL regulator array.
Figure 3 is an exemplary embodiment of communication over a single-wire bus. Figure 4 illustrates an exemplary embodiment of a data transmission scheme utilized by the POL regulators and controller.
Figure 5 illustrates an exemplary embodiment of a voltage regulator.
Figure 6 illustrates an exemplary embodiment of a clock recovery circuit.
Figure 7 illustrates an exemplary embodiment of a delay bus. Figure 8 illustrates an exemplary embodiment of the timing diagram of the clock recovery circuit of Figure 6.
Figures 9-11 illustrate exemplary embodiments of the timing diagrams and input ripple of the POL regulator array. It should be noted that the figures are not drawn to scale and that elements of similar structures or functions are generally represented by like reference numerals for illustrative purposes throughout the figures. It also should be noted that the figures are only intended to facilitate the description of the preferred embodiments of the present invention. The figures do not describe every aspect of the present invention and do not limit the scope of the invention.
DETAILED DESCRIPTION The present invention is directed to a system and method for providing interleaving point-of-load (POL) regulators such that each regulator's switching cycle is phase displaced with respect to those of other regulators in the array. As a result, the aggregate reflected ripple and noise of the input, output or both is reduced. Each regulator in the array is associated with an address. A serial data-line may write the phase spacing programmed to each addressable POL regulator in the array. Alternatively, the phase spacing data may be provided from memory. Accordingly, the present invention permits phase displacement of the regulators without limiting the input and output voltages of each of the regulators in the array. The array of regulators may also operate in a phase displaced mode with only a single control line. The need for separate controllers and multiple control lines is thereby eliminated. Figure 1 shows an exemplary embodiment of a point-of load (POL) regulator array system of the present invention, shown generally at 10. The system 10 includes an array of POL regulators or converters 20 and a controller 5. POL regulators 20 and controller 15 may be configured to form a board level distributed power architecture, for example. Although the exemplary embodiment depicted in Figure 1 shows a controller 15, the present invention does not require controller 15, as will be shown and described below with reference to Figure 2. Controller 15 and POL regulators 20 communicate via interface 25. Interface 25, shown as SYNC/DATA line 25, may be a one line, bidirectional interface.
Each POL regulator 20 is associated with a selected address. The address configuration for each POL regulator 20 specifies an ID for that POL regulator 20. A selected POL regulator 20, shown as POL regulator 20A, may be designated as the Master POL regulator 20. This designation may be based on a selected address, e.g., the least significant address or Address 0. The Master POL regulator 20A generates the SYNC portion of the SYNC/DATA line signal 25. Controller 15 and all other POL regulators 20 synchronize to this SYNC signal. Any other device connected to the SYNC/DATA line 25 may provide the clock, e.g., POL regulator 20, controller 15 or an additional external clock generator (not shown).
The power conversion switching frequency of each POL regulator 20 is synchronized to a (integer or fractional) multiple of the SYNC/DATA line frequency. Therefore, the POL regulators 20 do not have to operate at the same frequency. As a result, this provides greater system flexibility and optimized efficiency because each POL regulator 20 may operate at its optimal frequency depending on its input voltage and output voltage setting instead of operating at the same frequency as every other POL regulator in the system. Each POL regulator 20 may receive input voltage Vin 45. The output voltage Vo of each POL regulator 20 may be provided to devices connected to system 10 in any suitable manner. In the exemplary embodiment shown in Figure 1 , for example, the output of two or more POL regulators 20 may be connected in parallel. In this embodiment, an additional current share line 40 may be used to ensure an equal load share between the POL regulators 20.
As discussed above, controller 15 and POL regulators 20 communicate via interface 25, e.g., a one line, bi-directional SYNC/DATA line. Controller 15 may transmit data through SYNC/DATA line 25 to each of the POL regulators 25. Controller 15 may set the specific phase displacement for each of the POL regulators 25 through this interface. Controller 15 may set the phase displacements for each POL regulator 25 to minimize the switching noise on the intermediate bus voltage. Alternatively or additionally, controller 15 may set the phase displacements to minimize the noise on the output of the POL regulators 25 connected in parallel. Controller 15 may set the phase displacement statically, e.g., the phase displacement is programmed or set in a permanent or semi-permanent manner. Alternatively, controller 15 may adapt the phase displacement dynamically to minimize the noise in the system when specific system parameters change. These system parameters may include, for example, load currents, output or input voltages or the number of POL regulators (e.g., the phase displacement may be dynamically adapted when POL regulators are added or removed physically or enabled or disabled electrically).
Because of the flexible nature of the present invention, system 10 may be configured in a variety of modes. For example, in one exemplary embodiment, system 10 may include a common input bus with several voltage outputs. In another exemplary embodiment, system 10 may include several input buses and several voltage outputs. In another exemplary embodiment, system 10 may include a common input bus and a single voltage output. In this particular embodiment, the single voltage output may be a multi-phase voltage output.
Figure 2 illustrates another exemplary embodiment of the present invention. The POL regulator array, indicated generally at 200, includes POL regulators 220 and SYNC line 225. The outputs of POL regulators 235A and 235B are connected in parallel to provide output voltage 230 (Vo1). Similarly, the outputs of POL regulators 235C and 235D provide output voltage 230B (Vo2). Current share lines 240A and 240B are provided for these two pairs, respectively, to provide an equal load share. The input voltage 245 (Vin) is provided to each POL regulator 220. In this particular exemplary embodiment, system 200 does not include a controller. A selected POL regulator 235A, e.g., the POL regulator with Address=0, acts as the Master POL regulator and generates the SYNC portion of the SYNC line signal. All other POL regulators 220 synchronize to this signal. Any internal or external device connected to SYNC line 225 may provide the clock.
Data transmission over SYNC line 225 is not necessary to set the phase displacement of POL regulators 235. In this exemplary embodiment, the address of each POL regulator 235 may be used to determine the phase displacement of the POL regulator 235. For example, as discussed below in reference to Figure 5, the address of the POL regulators 235 may be used to determine the phase displacement of the pulse width modulated (PWM) signals of each POL regulator 235 as compared to the SYNC line 225. For instance, the address of each POL regulator 20 may set the initial phase displacement and this phase displacement can be overwritten or changed by the controller 15. The addresses for the POL regulators 235 do not need to be unique. For instance, POL regulators 235 with the same address will be phase synchronized. Thus, the optimal phase position of each POL regulator 235 may be chosen to minimize a specific design parameter by wiring or programming the address via input 235 accordingly. For example, POL regulator 220A ("POL 0") may have a phase displacement of 0°, POL regulator 220B ("POL 1") may have a phase displacement of 180°, POL regulator 220C ("POL 2") may have a phase displacement of 90° and POL regulator 220D ("POL 3") may have a phase displacement of 270°. In this particular example, the POL regulators connected in parallel, as shown in Figure 2, will have a 180° phase shift, which is optimal for the outputs of system 200. Similarly, the pairs are 90° phase shifted with respect to each other, which therefore provides an optimal current distribution for the input of system 200.
Figure 3 illustrates one exemplary method of communicating over a single-wire serial bus, e.g., the SYNC/DATA line. Specifically, a transmission line 340 is created by propagating a clock signal 300 over the serial bus. The clock signal 300 can be generated by the controller, a particular POL regulator (e.g., the POL regulator with the least significant address or Address=0), or an external device. The clock signal 300 synchronizes the various ' communicating devices (e.g., the POL regulators and the controller) and creates a series of clock cycles 310, each one including a data bit 320. This data bit 320 allows the various communicating devices to transmit a single bit of data for every clock cycle 310. Accordingly, each communicating device transmits data by leaving/pulling the data bit 320 high or low (i.e., binary one or zero). It should be appreciated that Figure 3, as discussed herein, is not intended to limit the present invention, but to provide an example as to how communication can occur over a single- wire serial bus. Figure 4 illustrates one exemplary method of transmitting information between the controller and at least one POL regulator. In this particular example, a forty-two bit communication cycle 450 can be used to transmit initial-configuration data, fault- monitoring data, unique ID data or any combination thereof. As shown in Figure 4, the forty-two bit transmission cycle 450 includes a four bit start sequence 410, a sixteen bit (with parity) address set 420, an eight bit (with parity) command set 430, a first acknowledgement bit 440, an eight bit (with parity) data set 460, and a second acknowledge bit 470. An additional bit 450 has been added to ensure that the command set 430 is executed before the data set 460 is provided. It should be appreciated that the communication cycle 450 depicted in Figure 4 is not intended to limit the present invention, but to illustrate how information can be transmitted over a serial bus. Therefore, communication cycles containing more or less information or bits are within the spirit and scope of the present invention.
The first and second acknowledgement bits 440 and 470, respectively, are used to acknowledge the reception of the command set 430 and the data set 460, respectively. It should be appreciated that the device responsible for the providing the first and second acknowledgement bits 440 and 470 varies depending upon whether the information is being sent to or from the POL regulator (e.g., whether the information is being written, read, or provided). The command set 430, data set 460 and address set 420 enable the controller and the POL regulators to write, read and provide data. For example, the command set 430 is used to identify whether and what the controller is writing (e.g., writing to the status register), the controller is reading (e.g., reading the status register), or the POL regulator is providing (e.g., providing status register information). The address set 420 is used to identify the POL regulator(s) that is being written to or read or the POL regulator that is providing information. The data set 460 is used to identify the actual data that is being written, read, or provided.
The start sequence 410 and address set 420 are used, in part, to identify the sender of the information. For example, the controller uses a different start sequence 410 than the POL regulators. Thus, the controller can determine, by reading the start sequence 410 of the communication cycle 450 being transmitted, whether a POL regulator is also attempting to send a communication cycle 450 at the same time. Similarly, each POL regulator has a different address set 420. Thus, a POL regulator can determine, by reading the start sequence 410 and address set 420 of the communication cycle 450 being transmitted, whether another POL regulator or the controller is also attempting to send a communication cycle 450 at the same time. If multiple devices are attempting to send a communication cycle 450, sequencing data is used to allocate or arbitrate bus use. It should be appreciated that the sequence data can either be stored (or hard wired) as a default value or provided as initial-configuration data and stored in the storage device (e.g., a sequencing configuration register).
Figure 5 shows an exemplary embodiment of a voltage regulation module, indicated generally at 500, according to the present invention. The voltage regulation module 500 has an input stage and an output stage accessible via an input terminal 510 and an output terminal 520 with a return terminal 530. Generally, voltage regulation module 500 is designed to convert the input voltage Vin between the terminals 510 and 530 into an output voltage Vo between the terminals 520 and 530. The voltage regulation module 500 includes a L/C low pass filter, indicated generally at 560, driven by switching elements Q1 and Q2. A non-inverting driver 540 and an inverting driver 545 are provided for power switches Q1 and Q2, respectively, and these drivers are both controlled or activated by a pulse width modulated control signal generated by the PWM signal generator or pulse width modulator 570, discussed below.
The voltage regulation module also includes an output voltage or power train controller 550. The output voltage controller 550 includes a feedback controller 565 and pulse width modulator 570 that is synchronized to the TRIGGER signal 575. The module 500 further includes a clock recovery circuit 580, a serial interface handler 585 and a memory block 590. The clock recovery circuit 580 generates the phase shifted, synchronized TRIGGER signal 575. The serial interface handler 585 decodes any messages that are sent over the SYNC/DATA line 595 and stores the data in the memory block 590, e.g. the required phase displacement. The clock recovery circuit 580 and serial interface handler 585 receive address data via input 555. If there is no communication over the SYNC/DATA line 595, for instance, in the case of the exemplary embodiment of the POL regulator array shown in Figure 2 or before any communication over the SYNC/DATA line 595 has taken place, in the case of the exemplary embodiment shown in Figure 1 , the memory 590 may be initialized with predefined data. This data can either be hardwired or programmed by an OTP (one time programmable) method or any other method. As discussed above, the TRIGGER signal 575 is sent to the voltage regulator's pulse width modulator 570 to start a new PWM control signal used to control the drivers 540 and 545 associated with the power switches Q1 and Q2.
Figure 6 shows an exemplary embodiment of the clock recovery circuit, indicated generally at 600, of the present invention. Generally, clock recovery circuit 600 receives a SYNC/DATA signal 605 and generates a phase-shifted synchronized TRIGGER signal 630. Clock recovery circuit 600 includes an inverter 610, a phase detector (PD) 615, a filter 620, a ring oscillator 625, a delay bus 635, a multiplexer 640 and a frequency divider 680. Clock recovery circuit 600 may access a memory location 645. For example, this memory location may be a memory location in the voltage regulator (e.g., memory 590 as shown in Figure 5). Inverter 610 inverts SYNC/DATA line signal 605. Phase detector 615 generates a signal which is proportional to the frequency and phase difference of the positive slopes of signals S1 (generated by the inverter 610) and S2 (generated by the frequency divider 680). Filter 620 filters the phase difference and controls the ring- oscillator frequency and phase. Ring oscillator 625 is an oscillator that may generate a delay bus 635. The signals of delay bus 635 are equally spaced to each other (see Figure 7, described below). As discussed above, the DO signal is used as the TRIGGER signal 630 to synchronize the PWM generator of the power train feedback loop (see, for example, Figure 5). Multiplexer 640 selects, based on the settings in memory block 645, at least one output of delay bus 635. Frequency divider 680 divides the frequency of the output of multiplexer 640 according the settings in memory block 645 and feeds the signal (shown in Figure 6 as S2) back to phase detector 615.
Generally, the components of clock recovery circuit 600 form a phase locked loop. The phases of the signals S1 and S2 are aligned in steady state. Depending on which signal is chosen by multiplexer 640 from delay bus 635, the DO positive transition can be shifted relative to the negative transition of the SYNC/DATA line 605. The DO positive transition defines the starting point of the PWM signal in the power train, e.g., power train 550 shown in Figure 5. In another exemplary embodiment, a selected voltage regulator 500 may serve as the master voltage regulator. The master voltage regulator includes the master clock generator to generate the synchronization signal, as discussed above. In this case, the clock recovery circuit 600 of the master voltage regulator may be configured to act as the master clock generator. For example, this clock recovery circuit 600 may be configured to serve as the master clock generator by opening the phase locked loop of the clock recovery circuit and using the ring oscillator 625 as a free-running oscillator.
Figure 7 shows an exemplary embodiment of the signals generated by the delay bus 635 as shown in Figure 6. In the exemplary embodiment of Figure 7, the ring oscillator 625 generates a delay bus consisting of 2m signals, wherein each signal is equally delayed by trj. Note that the delay bus need not generate 2X number of signals. In a system without a controller (e.g., as depicted in the exemplary embodiment of Figure 2), the phase lead or phase displacement may accordingly be expressed as:
Phi = {[value (address)]/(maximum number of POL regulators)} x 360° The value (address) corresponds to the address of the selected POL regulator or delay bus signal. The denominator corresponds to the maximum number of POL regulators in the system that may be addressed, e.g., 32.
Figure 8 shows an exemplary embodiment of the various timing signals of the voltage regulation module and clock recovery circuit of the present invention. In this example, m=4. The multiplexer 640 (shown in figure 6) selects signal D3 from delay bus 635. The frequency divider 680 is set to K=1. Accordingly, the clock recovery circuit 600 aligns the selected delay bus signal D3 to the SYNC/DATA line. As a result, using the formula discussed above, the delay bus signal DO (e.g., the SYNC signal) has a predictable phase lead of Phi= 3/2m x 360° = 67.5° compared to the SYNC/DATA line. The positive slope of the DO signal (e.g., the TRIGGER signal) triggers the starting of the PWM signal. Therefore, the PWM signal has the same phase lead as the DO signal. By changing the multiplexer selection, the phase lead of the PWM signal is therefore selectable by the value stored in memory.
Figures 9-11 illustrate exemplary embodiments of timing diagrams and simplified input ripple waveforms. Figure 9 shows an in-phase set of waveforms. In this exemplary embodiment, four downstream buck converter signals i(i1), i(i2), i(i3) and i(i4), which correspond to the input current of regulators with 3.3 V at 20 A, 2.5 V at 30 A, 1.8 V at 20 A and 1.2 V at 20 A, respectively, are shown. Signal i(co) is the ripple current in an input capacitor. As shown in Figure 9, the resulting capacitor ripple voltage is 1.198 V. Figure 10 illustrates the effects of out-phasing. In this case, the regulators are equally out-phased. It may be noted that the first two waveforms overlap. The resulting capacitor ripple voltage in this case is 406 mV. Figure 11 shows an even more advantageous phasing distribution that results from choosing voltage and current dependant phase displacements. Accordingly, the capacitor ripple voltage is lower. In this case, the capacitor ripple is 263 mV. This shows clearly the advantage of being able to choose the phase displacement according the operating point of the system to reduce system noise. It may be understood that further optimization is possible. Thus, phase displacing these pulses may result in lowered capacitor ripple or, alternatively, lower amounts of bus capacitance may be required to support a given ripple voltage.
The invention is susceptible to various modifications and alternative forms, and specific examples thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the invention is not to be limited to the particular forms or methods disclosed, but to the contrary, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the claims.

Claims

CLAIMS What is claimed is:
1. A power supply system comprising: a plurality of voltage regulators, wherein each voltage regulator is operable to provide a voltage output and is associated with an address; a master clock generator operable to generate a synchronization signal; an interface line operable to communicatively couple the voltage regulators and carry the synchronization signal to allow the voltage regulators to receive the synchronization signal; and a plurality of clock recovery circuits, wherein each clock recovery circuit is associated with a voltage regulator and wherein each clock recovery circuit is operable to generate a phase shifted trigger signal, wherein the phase shifted trigger signal is phase shifted with respect to the synchronization signal by a selected phase difference and synchronized to a selected frequency multiple of the synchronization signal based on the address of the associated voltage regulator such that a first switching cycle associated with a first voltage regulator may be phase displaced with respect to a second switching cycle associated with a second voltage regulator and a different frequency from the second switching cycle.
2. The supply system of Claim 1 , wherein a selected one of the plurality of voltage regulators further comprises the master clock generator.
3. The supply system of Claim 1 , wherein a selected one of the plurality of clock recovery circuits further comprises the master clock generator.
4. The power supply system of Claim 1 , further comprising a controller communicatively coupled to the interface line and operable to transmit data to the voltage regulators and set the selected phase difference for each voltage regulator via the interface line.
5. The power supply system of Claim 4 wherein the controller is operable to set the selected phase difference to minimize system noise.
6. The power supply system of Claim 5, wherein the controller is operable to dynamically set the selected phase difference to minimize system noise in response to a change in a selected system parameter.
7. The power supply system of Claim 6, wherein the selected system parameter is the number of enabled voltage regulators.
8. The power supply system of Claim 1 , wherein the phase displacement and selected frequency multiple of each voltage regulator is selected based on the input voltage of the respective voltage regulator.
9. The power supply system of Claim 1 , wherein the phase displacement and selected frequency multiple of each voltage regulator is selected based on the output voltage of the respective voltage regulator.
10. The power supply system of Claim 1 , wherein each voltage regulator further comprises: an input terminal, an output terminal and a return terminal, wherein the voltage regulator is operable to convert an input voltage between the input terminal and the return terminal into an output voltage between the return terminal and the output terminal; a power device; a memory operable to store the selected phase displacement; and an output voltage controller operable to receive the phase shifted trigger signal and transmit a pulse width modulated signal based on the phase shifted trigger signal to control the operation of the power device, wherein an associated one of the plurality of clock recovery circuits is operable to access the memory, receive the synchronization signal and transmit the phase shifted trigger signal to the pulse width modulator based on the selected phase displacement.
11. The power supply system of Claim 10, wherein the voltage regulator further comprises a serial interface handler operable to decode data transmitted via the interface line and store the selected phase displacement in the memory.
12. The power supply system of Claim 10, wherein the output voltage controller further comprises a pulse width modulator operable to generate the pulse width modulated signal.
13. The power supply system of Claim 10, wherein the clock recovery circuit comprises a ring oscillator operable to generate a delay bus associated with a plurality of delay bus signals, wherein the phase shifted trigger signal is based on the selected delay bus signal.
14. The power supply system of Claim 13, wherein the clock recovery circuit further comprises a multiplexer operable to select the delay bus signal based on the selected phase displacement stored in the memory.
15. The power supply system of Claim 14, wherein the memory is initialized with the address of the voltage regulator.
16. The power supply system of Claim 1 , wherein the voltage regulator is a point-of-load (POL) regulator.
17. The power supply system of Claim 1 , wherein the power supply system is operable to receive multiple independent voltage inputs.
18. The power supply system of Claim 1 , wherein the power supply system further comprises a single multiple-phase voltage output.
19. The power supply system of Claim 1 , wherein the voltage outputs of at least two voltage regulators are connected in parallel.
20. The power supply system of Claim 19, wherein the power supply system further comprises a current share line communicatively coupled between at least two voltage regulators that are connected in parallel to thereby provide an equal load share between the voltage regulators that are connected in parallel.
21. A method for providing the interleaving of a plurality of voltage regulators, comprising the steps of: selecting a phase displacement for each voltage regulator; assigning an address for each voltage regulator; generating a synchronization signal; generating a trigger signal that is phase displaced from the synchronization signal by the selected phase displacement and synchronized to a selected frequency multiple of the synchronization signal; and providing a phase displaced switching frequency based on the trigger signal.
22. The method of Claim 21 , wherein the phase displacement for a selected voltage regulator is based on the address of the selected voltage regulator.
23. The method of Claim 22, further comprising the step of transmitting the phase displacement for the selected voltage regulator to the selected voltage regulator.
24. The method of Claim 21 , further comprising the steps of: receiving an input voltage via a common input bus; and providing a single multi-phase voltage output.
25. The method of Claim 21 , further comprising the steps of: receiving a plurality of input voltages; and providing a plurality of output voltages, wherein each output voltage is phase displaced with respect to each other.
26. The method of Claim 21 , further comprising the steps of receiving a plurality of input voltages; and providing a single multi-phase voltage output.
PCT/US2003/035515 2002-12-23 2003-11-06 System and method for interleaving point-of-load regulators WO2004062062A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU2003291357A AU2003291357A1 (en) 2002-12-23 2003-11-06 System and method for interleaving point-of-load regulators
KR1020047007979A KR100785941B1 (en) 2002-12-23 2003-11-06 Method of interleaving a plurality of voltage regulators and power supply system using the same
EP20030768750 EP1576711B1 (en) 2002-12-23 2003-11-06 System and method for interleaving point-of-load regulators

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/328,154 2002-12-23
US10/328,154 US7373527B2 (en) 2002-12-23 2002-12-23 System and method for interleaving point-of-load regulators

Publications (1)

Publication Number Publication Date
WO2004062062A1 true WO2004062062A1 (en) 2004-07-22

Family

ID=32594389

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/035515 WO2004062062A1 (en) 2002-12-23 2003-11-06 System and method for interleaving point-of-load regulators

Country Status (6)

Country Link
US (2) US7373527B2 (en)
EP (1) EP1576711B1 (en)
KR (1) KR100785941B1 (en)
CN (1) CN100459360C (en)
AU (1) AU2003291357A1 (en)
WO (1) WO2004062062A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008053670A1 (en) * 2008-10-29 2010-05-12 Texas Instruments Deutschland Gmbh Apparatus and method for generating clock signals for DC-DC converters

Families Citing this family (97)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7049798B2 (en) * 2002-11-13 2006-05-23 Power-One, Inc. System and method for communicating with a voltage regulator
US7394445B2 (en) * 2002-11-12 2008-07-01 Power-One, Inc. Digital power manager for controlling and monitoring an array of point-of-load regulators
US6949916B2 (en) * 2002-11-12 2005-09-27 Power-One Limited System and method for controlling a point-of-load regulator
US7456617B2 (en) 2002-11-13 2008-11-25 Power-One, Inc. System for controlling and monitoring an array of point-of-load regulators by a host
US6833691B2 (en) 2002-11-19 2004-12-21 Power-One Limited System and method for providing digital pulse width modulation
US7249267B2 (en) * 2002-12-21 2007-07-24 Power-One, Inc. Method and system for communicating filter compensation coefficients for a digital power control system
US7836322B2 (en) 2002-12-21 2010-11-16 Power-One, Inc. System for controlling an array of point-of-load regulators and auxiliary devices
US7266709B2 (en) 2002-12-21 2007-09-04 Power-One, Inc. Method and system for controlling an array of point-of-load regulators and auxiliary devices
US7673157B2 (en) 2002-12-21 2010-03-02 Power-One, Inc. Method and system for controlling a mixed array of point-of-load regulators through a bus translator
US7737961B2 (en) 2002-12-21 2010-06-15 Power-One, Inc. Method and system for controlling and monitoring an array of point-of-load regulators
US7882372B2 (en) 2002-12-21 2011-02-01 Power-One, Inc. Method and system for controlling and monitoring an array of point-of-load regulators
US7743266B2 (en) 2002-12-21 2010-06-22 Power-One, Inc. Method and system for optimizing filter compensation coefficients for a digital power control system
US7373527B2 (en) * 2002-12-23 2008-05-13 Power-One, Inc. System and method for interleaving point-of-load regulators
US7710092B2 (en) * 2003-02-10 2010-05-04 Power-One, Inc. Self tracking ADC for digital power supply control systems
US7023190B2 (en) * 2003-02-10 2006-04-04 Power-One, Inc. ADC transfer function providing improved dynamic regulation in a switched mode power supply
US7080265B2 (en) * 2003-03-14 2006-07-18 Power-One, Inc. Voltage set point control scheme
US6936999B2 (en) * 2003-03-14 2005-08-30 Power-One Limited System and method for controlling output-timing parameters of power converters
US7506179B2 (en) 2003-04-11 2009-03-17 Zilker Labs, Inc. Method and apparatus for improved DC power delivery management and configuration
US7793005B1 (en) * 2003-04-11 2010-09-07 Zilker Labs, Inc. Power management system using a multi-master multi-slave bus and multi-function point-of-load regulators
US7653757B1 (en) * 2004-08-06 2010-01-26 Zilker Labs, Inc. Method for using a multi-master multi-slave bus for power management
US7685320B1 (en) * 2003-04-11 2010-03-23 Zilker Labs, Inc. Autonomous sequencing and fault spreading
US7372682B2 (en) * 2004-02-12 2008-05-13 Power-One, Inc. System and method for managing fault in a power system
US20050286709A1 (en) * 2004-06-28 2005-12-29 Steve Horton Customer service marketing
US7554310B2 (en) * 2005-03-18 2009-06-30 Power-One, Inc. Digital double-loop output voltage regulation
US7141956B2 (en) * 2005-03-18 2006-11-28 Power-One, Inc. Digital output voltage regulation circuit having first control loop for high speed and second control loop for high accuracy
US7239115B2 (en) * 2005-04-04 2007-07-03 Power-One, Inc. Digital pulse width modulation controller with preset filter coefficients
US20080207237A1 (en) 2005-04-14 2008-08-28 Koninklijke Philips Electronics N.V. Communication in Phase Shifted Driven Power Converters
US7327149B2 (en) * 2005-05-10 2008-02-05 Power-One, Inc. Bi-directional MOS current sense circuit
US8589704B2 (en) * 2005-06-16 2013-11-19 Active-Semi, Inc. System for a scalable and programmable power management integrated circuit
US7688046B2 (en) * 2005-07-25 2010-03-30 Apple Inc. Power converters having varied switching frequencies
US8515342B2 (en) * 2005-10-12 2013-08-20 The Directv Group, Inc. Dynamic current sharing in KA/KU LNB design
US20080018313A1 (en) * 2006-07-20 2008-01-24 International Business Machines Corporation Power supply system using delay lines in regulator topology to reduce input ripple voltage
US20080246453A1 (en) * 2006-07-20 2008-10-09 International Business Machines Corporation Power supply system using delay lines in regulator topology to reduce input ripple voltage
KR100817031B1 (en) * 2006-08-25 2008-03-26 주식회사 케이이씨 Single wire Serial Interface Module
US8004111B2 (en) * 2007-01-19 2011-08-23 Astec International Limited DC-DC switching cell modules for on-board power systems
JP4687656B2 (en) * 2007-01-24 2011-05-25 トヨタ自動車株式会社 Multiphase voltage conversion device, vehicle, and control method for multiphase voltage conversion device
US7673084B2 (en) * 2007-02-20 2010-03-02 Infineon Technologies Ag Bus system and methods of operation using a combined data and synchronization line to communicate between bus master and slaves
US7755341B2 (en) * 2007-07-05 2010-07-13 Intersil Americas Inc. Steady state frequency control of variable frequency switching regulators
US7592791B2 (en) * 2007-08-07 2009-09-22 Newport Media, Inc. High efficiency DC-DC converter using pulse skipping modulation with programmable burst duration
US7834613B2 (en) * 2007-10-30 2010-11-16 Power-One, Inc. Isolated current to voltage, voltage to voltage converter
DE102007059380B3 (en) * 2007-12-07 2009-05-07 Deutsches Zentrum für Luft- und Raumfahrt e.V. Ripple currents minimizing method for common buffer capacitor of e.g. step-up converter, involves adjusting determined phase difference of signal during pulse width modulation period after processing pulses in another period
US8120205B2 (en) * 2008-07-18 2012-02-21 Zilker Labs, Inc. Adding and dropping phases in current sharing
US8239597B2 (en) * 2008-07-18 2012-08-07 Intersil Americas Inc. Device-to-device communication bus for distributed power management
US8120203B2 (en) * 2008-07-18 2012-02-21 Intersil Americas Inc. Intelligent management of current sharing group
US8237423B2 (en) * 2008-07-18 2012-08-07 Intersil Americas Inc. Active droop current sharing
DE102008002971A1 (en) 2008-07-25 2009-01-15 Robust Electronics Gmbh Method for minimizing harmonic source current during supply from multiple converter stages, involves determining amplitude and phase of fundamental vibrations of each converter
DE102008048017B4 (en) * 2008-09-19 2023-03-16 Bayerische Motoren Werke Aktiengesellschaft Control device for a polyphase voltage converter
GB2471078A (en) * 2009-06-15 2010-12-22 Powervation Ltd Digitally sharing of power converter stress
US9014825B2 (en) * 2009-06-16 2015-04-21 Maxim Integrated Products, Inc. System and method for sequentially distributing power among one or more modules
WO2011046645A1 (en) * 2009-07-10 2011-04-21 Protonex Technology Corporation Power managers, methods for operating a power manager, and methods for operating a power network
TWI412216B (en) * 2009-09-02 2013-10-11 Delta Electronics Inc Interleaved-pwm power system and method for operating the same
CN102025284B (en) * 2009-09-10 2013-08-21 台达电子工业股份有限公司 Staggered pulse wave width modulation control power module system and operating method thereof
US8014181B2 (en) * 2009-09-29 2011-09-06 General Electric Company Power conversion control system
TWI381622B (en) * 2009-10-05 2013-01-01 Anpec Electronics Corp Power supply with synchronized clocks and related dc-dc converter
US8502420B1 (en) 2009-10-15 2013-08-06 Power-One, Inc. Power supply architecture for controlling and monitoring isolated output modules
US8261103B2 (en) * 2009-10-28 2012-09-04 Dell Products L.P. Systems and methods for controlling power delivery to system components
US8080981B2 (en) * 2009-11-06 2011-12-20 Delta Electronics, Inc. Interleaved-PWM power module system and method with phase-locking operation
US8417986B2 (en) * 2009-12-23 2013-04-09 Intel Corporation Time negotiation using serial voltage identification communication
EP2394908B1 (en) * 2010-06-08 2013-03-06 GE Energy Power Conversion Technology Limited Power distribution system and method for controlling it.
CN102792573B (en) * 2010-06-15 2018-03-23 罗姆电力华纯有限公司 Digital pressure sharing method
US8575909B2 (en) * 2010-09-17 2013-11-05 Qualcomm Incorporated Synchronously sampled single bit switch mode power supply
FR2969849B1 (en) * 2010-12-23 2012-12-28 Valeo Sys Controle Moteur Sas DEVICE AND METHOD FOR CONVERTING IN THE INBOARD NETWORK OF A VEHICLE
US8723492B2 (en) * 2011-03-22 2014-05-13 Integrated Device Technology, Inc. Autonomous controlled headroom low dropout regulator for single inductor multiple output power supply
TWI481169B (en) * 2011-05-27 2015-04-11 Leadtrend Tech Corp Method for controlling voltage crossing power switch of switched-mode power converter and the circuit using the same
US8941409B2 (en) 2011-07-01 2015-01-27 Tabula, Inc. Configurable storage elements
US9148151B2 (en) 2011-07-13 2015-09-29 Altera Corporation Configurable storage elements
JP5849502B2 (en) * 2011-08-01 2016-01-27 ソニー株式会社 Information processing apparatus, information processing method, and program
JP5878742B2 (en) * 2011-11-30 2016-03-08 ルネサスエレクトロニクス株式会社 controller
US8935010B1 (en) * 2011-12-13 2015-01-13 Juniper Networks, Inc. Power distribution within high-power networking equipment
US8624567B2 (en) * 2011-12-30 2014-01-07 O2Micro, Inc. Controllers for DC/DC converters
US9419526B2 (en) * 2012-03-16 2016-08-16 Apple Inc. Phase-shifting a synchronization signal to reduce electromagnetic interference
KR101319989B1 (en) * 2012-04-25 2013-10-18 한국에너지기술연구원 Apparatus and method for controlling plural power converting modules, and apparatus and method for analizing electric energy imbalance
US9030047B2 (en) 2012-06-08 2015-05-12 International Business Machines Corporation Controlling a fault-tolerant array of converters
US9325242B2 (en) * 2012-06-29 2016-04-26 Infineon Technologies Austria Ag Switching regulator output capacitor current estimation
WO2014007845A1 (en) * 2012-07-02 2014-01-09 Tabula, Inc. Configurable storage elements
KR102008810B1 (en) * 2012-11-12 2019-08-08 엘지이노텍 주식회사 Wireless power transmitting apparatus and method
US9368073B2 (en) * 2013-08-12 2016-06-14 Shenzhen China Star Optoelectronics Technology Co., Ltd. LED backlight driving circuit and LCD
US9665147B1 (en) * 2013-12-12 2017-05-30 Google Inc. Devices and methods for minimizing input capacitance in computer design
US9748839B2 (en) 2014-03-31 2017-08-29 Infineon Technologies Austria Ag Digital voltage regulator controller with multiple configurations
US9570983B2 (en) * 2014-04-22 2017-02-14 International Business Machines Corporation Point of load regulator synchronization and phase offset
US9946677B2 (en) * 2015-02-12 2018-04-17 Atmel Corporation Managing single-wire communications
US9806620B2 (en) * 2015-03-12 2017-10-31 Avago Technologies General Ip (Singapore) Pte. Ltd. Multi-phase hysteretic buck switching regulator
US9645604B1 (en) 2016-01-05 2017-05-09 Bitfury Group Limited Circuits and techniques for mesochronous processing
US9514264B1 (en) 2016-01-05 2016-12-06 Bitfury Group Limited Layouts of transmission gates and related systems and techniques
US9660627B1 (en) 2016-01-05 2017-05-23 Bitfury Group Limited System and techniques for repeating differential signals
US10008918B2 (en) * 2016-10-25 2018-06-26 Dialog Semiconductor (Uk) Limited Phase-shifting optimization for asymmetric inductors in multi-phase DC-DC converters
US10230236B2 (en) * 2017-05-04 2019-03-12 Thermo King Corporation Method and system for feedback-based load control of a climate control system in transport
KR102395035B1 (en) 2017-08-29 2022-05-13 삼성전자 주식회사 Power supply for compensating for current deviation and operating method thereof
CN107908269A (en) * 2017-11-30 2018-04-13 郑州云海信息技术有限公司 A kind of more POL parallel combinations electric power systems and method of supplying power to
US10802519B2 (en) * 2018-05-25 2020-10-13 Renesas Electronics America Inc. Automatic configuration of multiple-phase digital voltage regulator
CN109683694A (en) * 2018-12-26 2019-04-26 联想(北京)有限公司 A kind of control method, device and electronic equipment
CN109491490B (en) * 2018-12-26 2021-05-18 联想(北京)有限公司 Control method and device and electronic equipment
EP3709492B1 (en) 2019-03-14 2021-08-11 Nxp B.V. Distributed control of a multiphase power converter
CN109933180B (en) * 2019-03-22 2021-06-15 联想(北京)有限公司 Control method and device and electronic equipment
EP3832871B1 (en) 2019-12-03 2022-10-26 NXP USA, Inc. Distributed interleaving control of multiphase smpcs
EP3902132A1 (en) 2020-04-22 2021-10-27 NXP USA, Inc. Modular interleaving techniques for scalable power electronics converter
US20230106703A1 (en) * 2021-09-28 2023-04-06 Infineon Technologies Ag Calibration with feedback sensing

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0660487A2 (en) * 1993-12-27 1995-06-28 Hitachi, Ltd. Power supply system
US5929618A (en) * 1998-06-04 1999-07-27 Lucent Technologies Inc. System and method for synchronizing and interleaving power modules
WO2002031951A2 (en) * 2000-10-13 2002-04-18 Primarion, Inc. System and method for highly phased power regulation using adaptive compensation control

Family Cites Families (155)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US122429A (en) * 1872-01-02 Improvement in propelling canal-boats
US201761A (en) * 1878-03-26 Improvement in motors
US27101A (en) * 1860-02-14 Twine-holdek
US142513A (en) * 1873-09-02 Improvement m draft-tubes for soda-fountains
US73347A (en) * 1868-01-14 of same place
US33152A (en) * 1861-08-27 Improvement in combination cement and metal pipes
US429581A (en) * 1890-06-03 parmelee
US3660672A (en) * 1971-02-25 1972-05-02 Pioneer Magnetics Inc Power supply dual output
GB1536046A (en) 1976-06-30 1978-12-20 Ibm Data processing system power control
US4194147A (en) * 1977-12-05 1980-03-18 Burr-Brown Research Corporation Parallel connected switching regulator system
DE2904786C2 (en) * 1979-02-08 1981-02-19 Siemens Ag, 1000 Berlin Und 8000 Muenchen Process for regulating inverters in parallel operation and circuit arrangements for carrying out the process
US4335445A (en) 1979-02-26 1982-06-15 Kepco, Inc. System for interfacing computers with programmable power supplies
US4350943A (en) * 1980-04-04 1982-09-21 Pritchard Eric K Amplifier for inductive loads with corrective current sensing
US4451773A (en) 1982-04-02 1984-05-29 Bell Telephone Laboratories, Incorporated Rectifier control system for a DC power plant system
EP0096370B1 (en) * 1982-06-04 1987-02-04 Nippon Chemi-Con Corporation Power supply device
US4538073A (en) 1983-05-09 1985-08-27 Convergent Technologies, Inc. Modular power supply system
US4607330A (en) 1983-11-29 1986-08-19 Parallel Computers, Inc. Fault-tolerant power supply system
US4622627A (en) * 1984-02-16 1986-11-11 Theta-J Corporation Switching electrical power supply utilizing miniature inductors integrally in a PCB
US4677566A (en) 1984-10-18 1987-06-30 Burroughs Corporation Power control network for multiple digital modules
US4654769A (en) * 1984-11-02 1987-03-31 California Institute Of Technology Transformerless dc-to-dc converters with large conversion ratios
US4616142A (en) * 1984-12-31 1986-10-07 Sundstrand Corporation Method of operating parallel-connected semiconductor switch elements
US4630187A (en) * 1985-09-09 1986-12-16 Sperry Corporation Power converter with duty ratio quantization
US4761725A (en) * 1986-08-01 1988-08-02 Unisys Corporation Digitally controlled A.C. to D.C. power conditioner
US4766364A (en) * 1987-11-04 1988-08-23 International Business Machines Corporation Parallel power systems
US5168208A (en) * 1988-05-09 1992-12-01 Onan Corporation Microprocessor based integrated generator set controller apparatus and method
US4988942A (en) * 1988-11-08 1991-01-29 Spectra-Physics, Inc. Switched resistor regulator control when transfer function includes discontinuity
US5053920A (en) * 1989-06-09 1991-10-01 Digital Equipment Corporation Integrated power conversion
US4940930A (en) 1989-09-07 1990-07-10 Honeywell Incorporated Digitally controlled current source
US5004972A (en) 1989-12-26 1991-04-02 Honeywell Inc. Integrated power level control and on/off function circuit
FR2656932B1 (en) * 1990-01-09 1992-05-07 Sgs Thomson Microelectronics CURRENT MEASUREMENT CIRCUIT IN A POWER MOS TRANSISTOR.
US5270904A (en) * 1990-05-02 1993-12-14 Zdzislaw Gulczynski Switching power apparatus with 3-state driver
US5073848A (en) * 1990-11-21 1991-12-17 General Electric Company Power distribution system
US5117430A (en) 1991-02-08 1992-05-26 International Business Machines Corporation Apparatus and method for communicating between nodes in a network
US5079498A (en) * 1991-03-26 1992-01-07 Vickers Systems Limited Digital pulse-width-modulation generator for current control
US6115441A (en) * 1991-07-09 2000-09-05 Dallas Semiconductor Corporation Temperature detector systems and methods
DE4122945A1 (en) 1991-07-11 1993-01-14 Philips Patentverwaltung MICROPROCESSOR CONTROLLED DC CONVERTER
US5229699A (en) * 1991-10-15 1993-07-20 Industrial Technology Research Institute Method and an apparatus for PID controller tuning
US5481140A (en) * 1992-03-10 1996-01-02 Mitsubishi Denki Kabushiki Kaisha Demand control apparatus and power distribution control system
US5426425A (en) 1992-10-07 1995-06-20 Wescom, Inc. Intelligent locator system with multiple bits represented in each pulse
JP2508616B2 (en) 1992-12-21 1996-06-19 日本プレシジョン・サーキッツ株式会社 Sampling rate converter
US5377090A (en) * 1993-01-19 1994-12-27 Martin Marietta Corporation Pulsed power converter with multiple output voltages
JP3191275B2 (en) * 1993-02-22 2001-07-23 横河電機株式会社 Switching power supply
US5481178A (en) 1993-03-23 1996-01-02 Linear Technology Corporation Control circuit and method for maintaining high efficiency over broad current ranges in a switching regulator circuit
US5489904A (en) * 1993-09-28 1996-02-06 The Regents Of The University Of California Analog current mode analog/digital converter
US6121760A (en) 1994-03-17 2000-09-19 Texas Instruments Incorporated Turn-on controller for switch-mode regulator
US5532577A (en) * 1994-04-01 1996-07-02 Maxim Integrated Products, Inc. Method and apparatus for multiple output regulation in a step-down switching regulator
US5627460A (en) * 1994-12-28 1997-05-06 Unitrode Corporation DC/DC converter having a bootstrapped high side driver
US5949226A (en) * 1995-04-10 1999-09-07 Kabushiki Kaisha Toyoda Jidoshokki Seisakush DC/DC converter with reduced power consumpton and improved efficiency
US5727208A (en) * 1995-07-03 1998-03-10 Dell U.S.A. L.P. Method and apparatus for configuration of processor operating parameters
US5752047A (en) * 1995-08-11 1998-05-12 Mcdonnell Douglas Corporation Modular solid state power controller with microcontroller
US5646509A (en) 1995-12-01 1997-07-08 International Business Machines Corporation Battery capacity test and electronic system utilizing same
US5631550A (en) 1996-04-25 1997-05-20 Lockheed Martin Tactical Defense Systems Digital control for active power factor correction
US5675480A (en) 1996-05-29 1997-10-07 Compaq Computer Corporation Microprocessor control of parallel power supply systems
US5943227A (en) * 1996-06-26 1999-08-24 Fairchild Semiconductor Corporation Programmable synchronous step down DC-DC converter controller
US5815018A (en) * 1996-07-16 1998-09-29 Systech Solutions, Inc. Pulse modulator circuit for an illuminator system
JP3042423B2 (en) 1996-09-30 2000-05-15 日本電気株式会社 Series-parallel A / D converter
US5929620A (en) 1996-11-07 1999-07-27 Linear Technology Corporation Switching regulators having a synchronizable oscillator frequency with constant ramp amplitude
US5847950A (en) 1997-02-19 1998-12-08 Electronic Measurements, Inc. Control system for a power supply
US5889392A (en) 1997-03-06 1999-03-30 Maxim Integrated Products, Inc. Switch-mode regulators and methods providing transient response speed-up
US5892933A (en) * 1997-03-31 1999-04-06 Compaq Computer Corp. Digital bus
US5872984A (en) 1997-04-01 1999-02-16 International Business Machines Corporation Uninterruptible power supply providing continuous power mainstore function for a computer system
US5946495A (en) * 1997-04-08 1999-08-31 Compaq Computer Corp. Data communication circuit for controlling data communication between redundant power supplies and peripheral devices
US5905370A (en) * 1997-05-06 1999-05-18 Fairchild Semiconductor Corporation Programmable step down DC-DC converter controller
US5883797A (en) * 1997-06-30 1999-03-16 Power Trends, Inc. Parallel path power supply
US5917719A (en) * 1997-08-11 1999-06-29 Power Ten, Inc. Internally programmable modular power supply and method
US5935252A (en) 1997-08-18 1999-08-10 International Business Machines Corporation Apparatus and method for determining and setting system device configuration relating to power and cooling using VPD circuits associated with system devices
US6000042A (en) * 1997-08-25 1999-12-07 3Com Corporation Fault detection on a dual supply system for a universal serial bus system
US6005377A (en) 1997-09-17 1999-12-21 Lucent Technologies Inc. Programmable digital controller for switch mode power conversion and power supply employing the same
US5870296A (en) 1997-10-14 1999-02-09 Maxim Integrated Products, Inc. Dual interleaved DC to DC switching circuits realized in an integrated circuit
US6079026A (en) 1997-12-11 2000-06-20 International Business Machines Corporation Uninterruptible memory backup power supply system using threshold value of energy in the backup batteries for control of switching from AC to DC output
US5990669A (en) * 1997-12-15 1999-11-23 Dell Usa, L.P. Voltage supply regulation using master/slave timer circuit modulation
US6136143A (en) 1998-02-23 2000-10-24 3M Innovative Properties Company Surface treating article including a hub
JP3744680B2 (en) * 1998-03-31 2006-02-15 富士通株式会社 Power supply device and method for controlling power supply circuit
JP3702091B2 (en) * 1998-03-31 2005-10-05 富士通株式会社 Power supply device and method for controlling power supply circuit
FI107418B (en) * 1998-05-22 2001-07-31 Muuntolaite Oy Method and plant for controlling a power source system
US6199130B1 (en) 1998-06-04 2001-03-06 International Business Machines Corporation Concurrent maintenance for PCI based DASD subsystem with concurrent maintenance message being communicated between SPCN (system power control network) and I/O adapter using PCI bridge
US6055163A (en) 1998-08-26 2000-04-25 Northrop Grumman Corporation Communications processor remote host and multiple unit control devices and methods for micropower generation systems
US6177787B1 (en) 1998-09-11 2001-01-23 Linear Technology Corporation Circuits and methods for controlling timing and slope compensation in switching regulators
US6304823B1 (en) 1998-09-16 2001-10-16 Microchip Technology Incorporated Microprocessor power supply system including a programmable power supply and a programmable brownout detector
US6268716B1 (en) * 1998-10-30 2001-07-31 Volterra Semiconductor Corporation Digital voltage regulator using current control
US6100676A (en) 1998-10-30 2000-08-08 Volterra Semiconductor Corporation Method and apparatus for digital voltage regulation
US6198261B1 (en) 1998-10-30 2001-03-06 Volterra Semiconductor Corporation Method and apparatus for control of a power transistor in a digital voltage regulator
US6181029B1 (en) 1998-11-06 2001-01-30 International Business Machines Corporation Method of controlling battery back-up for multiple power supplies
US6163178A (en) * 1998-12-28 2000-12-19 Rambus Incorporated Impedance controlled output driver
US6021059A (en) 1998-12-31 2000-02-01 Honeywell Inc. Integrated synchronous rectifier for power supplies
WO2000044098A1 (en) * 1999-01-19 2000-07-27 Steensgaard Madsen Jesper Residue-compensating a / d converter
US6137280A (en) * 1999-01-22 2000-10-24 Science Applications International Corporation Universal power manager with variable buck/boost converter
US6355990B1 (en) 1999-03-24 2002-03-12 Rockwell Collins, Inc. Power distribution system and method
US6111396A (en) * 1999-04-15 2000-08-29 Vanguard International Semiconductor Corporation Any value, temperature independent, voltage reference utilizing band gap voltage reference and cascode current mirror circuits
JP3644531B2 (en) * 1999-07-06 2005-04-27 富士電機機器制御株式会社 Arm-on detection circuit for on-delay compensation
US6057607A (en) * 1999-07-16 2000-05-02 Semtech Corporation Method and apparatus for voltage regulation in multi-output switched mode power supplies
US6191566B1 (en) * 1999-08-26 2001-02-20 Lucent Technologies Inc. Board mountable power supply module with multi-function control pin
US6294954B1 (en) 1999-09-23 2001-09-25 Audiologic, Incorporated Adaptive dead time control for switching circuits
US6157093A (en) * 1999-09-27 2000-12-05 Philips Electronics North America Corporation Modular master-slave power supply controller
US6211579B1 (en) * 1999-09-29 2001-04-03 Lucent Technologies, Inc. Multiple output converter having a low power dissipation cross regulation compensation circuit
US6392577B1 (en) * 1999-10-05 2002-05-21 Stmicroelectronics, Inc. System and method for regulating an alternator
US6208127B1 (en) * 1999-11-02 2001-03-27 Maxim Integrated Products, Inc. Methods and apparatus to predictably change the output voltage of regulators
WO2001055823A2 (en) * 2000-01-27 2001-08-02 Primarion, Inc. Apparatus for providing regulated power to an integrated circuit
US6396169B1 (en) * 2000-02-29 2002-05-28 3Com Corporation Intelligent power supply control for electronic systems requiring multiple voltages
US6385024B1 (en) * 2000-03-07 2002-05-07 Ss8 Networks, Inc. System and method for monitoring current consumption from current share components
US6246219B1 (en) * 2000-03-24 2001-06-12 The Boeing Company String switching apparatus and associated method for controllably connecting the output of a solar array string to a respective power bus
US6291975B1 (en) 2000-03-27 2001-09-18 Rockwell Collins Method and system for efficiently regulating power supply voltages with reduced propagation of power transients capable of communicating information
US6150803A (en) 2000-03-28 2000-11-21 Linear Technology Corporation Dual input, single output power supply
US6373334B1 (en) * 2000-06-12 2002-04-16 Cirrus Logic, Inc. Real time correction of a digital PWM amplifier
US6249111B1 (en) * 2000-06-22 2001-06-19 Intel Corporation Dual drive buck regulator
US6448746B1 (en) * 2000-06-30 2002-09-10 Intel Corporation Multiple phase voltage regulator system
US6396250B1 (en) * 2000-08-31 2002-05-28 Texas Instruments Incorporated Control method to reduce body diode conduction and reverse recovery losses
IT1318879B1 (en) * 2000-09-19 2003-09-10 St Microelectronics Srl VOLTAGE / CURRENT CONTROLLER DEVICE, IN PARTICULAR SWITCHING INTERLEAVING REGULATORS.
US6320768B1 (en) 2000-10-06 2001-11-20 Texas Instruments Incorporated Power supply pulse width modulation (PWM) control system
WO2002031943A2 (en) * 2000-10-10 2002-04-18 Primarion, Inc. System and method for highly phased power regulation
US7007176B2 (en) * 2000-10-10 2006-02-28 Primarion, Inc. System and method for highly phased power regulation using adaptive compensation control
IT1319007B1 (en) * 2000-10-16 2003-09-19 St Microelectronics Srl MANAGEMENT SYSTEM OF A PLURALITY OF VRM MODULES AND RELATED SYNCHRONIZATION METHODS
EP1215808B1 (en) * 2000-12-13 2011-05-11 Semiconductor Components Industries, LLC A power supply circuit and method thereof to detect demagnitization of the power supply
US6654264B2 (en) * 2000-12-13 2003-11-25 Intel Corporation System for providing a regulated voltage with high current capability and low quiescent current
TW554605B (en) * 2000-12-20 2003-09-21 Delta Electronics Inc Output voltage adjustable electrical power switcher
US6421259B1 (en) * 2000-12-28 2002-07-16 International Business Machines Corporation Modular DC distribution system for providing flexible power conversion scalability within a power backplane between an AC source and low voltage DC outputs
US6411071B1 (en) * 2000-12-29 2002-06-25 Volterra Semiconductor Corporation Lag compensating controller having an improved transient response
US6686831B2 (en) * 2001-01-23 2004-02-03 Invensys Systems, Inc. Variable power control for process control instruments
US6975494B2 (en) * 2001-01-29 2005-12-13 Primarion, Inc. Method and apparatus for providing wideband power regulation to a microelectronic device
US6366069B1 (en) * 2001-02-01 2002-04-02 Intel Corporation Hysteretic-mode multi-phase switching regulator
TW575949B (en) * 2001-02-06 2004-02-11 Hitachi Ltd Mixed integrated circuit device, its manufacturing method and electronic apparatus
US6800957B2 (en) * 2001-02-06 2004-10-05 General Electric Company Electronic distribution system for 36V automobiles
US6400127B1 (en) 2001-02-12 2002-06-04 Philips Electronics North America Corporation Dual mode pulse-width modulator for power control applications
DE60211872T2 (en) * 2001-03-26 2006-10-26 Harman International Industries, Incorporated, Northridge PULSE WIDTH MODULATION AMPLIFIER WITH DIGITAL SIGNAL PROCESSOR
US6731023B2 (en) * 2001-03-29 2004-05-04 Autoliv Asp, Inc. Backup power supply for restraint control module
US6411072B1 (en) 2001-04-17 2002-06-25 Honeywell International Inc. PWM power supply with constant RMS output voltage control
US6744243B2 (en) * 2001-06-28 2004-06-01 Texas Instruments Incorporated System and method for dynamically regulating a step down power supply
US6577258B2 (en) * 2001-10-01 2003-06-10 Nokia Corporation Adaptive sigma-delta data converter for mobile terminals
AU2002343624A1 (en) * 2001-11-05 2003-05-19 Shakti Systems, Inc. Monolithic battery charging device
US7554828B2 (en) * 2001-12-03 2009-06-30 Igo, Inc. Power converter with retractable cable system
US6903949B2 (en) * 2001-12-12 2005-06-07 International Rectifier Corporation Resonant converter with phase delay control
US6717389B1 (en) * 2001-12-21 2004-04-06 Unisys Corporation Method and apparatus for current controlled transient reduction in a voltage regulator
US20030122429A1 (en) * 2001-12-28 2003-07-03 Zhang Kevin X. Method and apparatus for providing multiple supply voltages for a processor
US6448745B1 (en) 2002-01-08 2002-09-10 Dialog Semiconductor Gmbh Converter with inductor and digital controlled timing
US6829547B2 (en) * 2002-04-29 2004-12-07 Tektronix, Inc. Measurement test instrument and associated voltage management system for accessory device
US6850426B2 (en) * 2002-04-30 2005-02-01 Honeywell International Inc. Synchronous and bi-directional variable frequency power conversion systems
US6693811B1 (en) * 2002-07-02 2004-02-17 Tyco Electronics Power Systems, Inc. Integrated controller, method of operation thereof and power supply employing the same
US6977492B2 (en) * 2002-07-10 2005-12-20 Marvell World Trade Ltd. Output regulator
US6949916B2 (en) * 2002-11-12 2005-09-27 Power-One Limited System and method for controlling a point-of-load regulator
US7049798B2 (en) * 2002-11-13 2006-05-23 Power-One, Inc. System and method for communicating with a voltage regulator
US7000125B2 (en) * 2002-12-21 2006-02-14 Power-One, Inc. Method and system for controlling and monitoring an array of point-of-load regulators
US6825644B2 (en) * 2002-11-14 2004-11-30 Fyre Storm, Inc. Switching power converter
US6778414B2 (en) * 2002-12-20 2004-08-17 The Boeing Company Distributed system and methodology of electrical power regulation, conditioning and distribution on an aircraft
US7249267B2 (en) * 2002-12-21 2007-07-24 Power-One, Inc. Method and system for communicating filter compensation coefficients for a digital power control system
US7373527B2 (en) * 2002-12-23 2008-05-13 Power-One, Inc. System and method for interleaving point-of-load regulators
US7023672B2 (en) * 2003-02-03 2006-04-04 Primarion, Inc. Digitally controlled voltage regulator
US6850046B2 (en) * 2003-02-10 2005-02-01 Power-One Limited Digital signal processor architecture optimized for controlling switched mode power supply
JP2004259951A (en) * 2003-02-26 2004-09-16 Renesas Technology Corp Semiconductor device
US7080265B2 (en) * 2003-03-14 2006-07-18 Power-One, Inc. Voltage set point control scheme
US6936999B2 (en) * 2003-03-14 2005-08-30 Power-One Limited System and method for controlling output-timing parameters of power converters
US6888339B1 (en) * 2003-04-03 2005-05-03 Lockheed Martin Corporation Bus voltage control using gated fixed energy pulses
US6853174B1 (en) * 2003-08-11 2005-02-08 Micrel, Inc. Selective high-side and low-side current sensing in switching power supplies
US20050093594A1 (en) * 2003-10-30 2005-05-05 Infineon Technologies North America Corp. Delay locked loop phase blender circuit
US7142140B2 (en) * 2004-07-27 2006-11-28 Silicon Laboratories Inc. Auto scanning ADC for DPWM
US7141956B2 (en) * 2005-03-18 2006-11-28 Power-One, Inc. Digital output voltage regulation circuit having first control loop for high speed and second control loop for high accuracy

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0660487A2 (en) * 1993-12-27 1995-06-28 Hitachi, Ltd. Power supply system
US5929618A (en) * 1998-06-04 1999-07-27 Lucent Technologies Inc. System and method for synchronizing and interleaving power modules
WO2002031951A2 (en) * 2000-10-13 2002-04-18 Primarion, Inc. System and method for highly phased power regulation using adaptive compensation control

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008053670A1 (en) * 2008-10-29 2010-05-12 Texas Instruments Deutschland Gmbh Apparatus and method for generating clock signals for DC-DC converters
US8618850B2 (en) 2008-10-29 2013-12-31 Texas Instruments Deutschland Gmbh Device and method for generating clock signals for DC-DC converters

Also Published As

Publication number Publication date
CN100459360C (en) 2009-02-04
US20080048625A1 (en) 2008-02-28
EP1576711A1 (en) 2005-09-21
KR100785941B1 (en) 2007-12-14
KR20040083058A (en) 2004-09-30
US20040123167A1 (en) 2004-06-24
CN1685459A (en) 2005-10-19
US7373527B2 (en) 2008-05-13
US7493504B2 (en) 2009-02-17
AU2003291357A1 (en) 2004-07-29
EP1576711B1 (en) 2012-08-08

Similar Documents

Publication Publication Date Title
US7373527B2 (en) System and method for interleaving point-of-load regulators
JP5462810B2 (en) Switching power supply device and switching power supply system using the same
ES2750348T3 (en) Procedure and system for communicating filter compensation coefficients for a digital power control system
US6448746B1 (en) Multiple phase voltage regulator system
CN1685592B (en) System and method for providing digital pulse width modulation
US7109694B2 (en) Digital multiphase control system
US7518894B2 (en) Distributed power supply system having reassignable master
US7446430B2 (en) Plural load distributed power supply system with shared master for controlling remote digital DC/DC converters
EP2328263B1 (en) Multi-phase DC-to-DC converter with daisy chained pulse width modulation generators
US7502240B2 (en) Distributed power supply system with separate SYNC control for controlling remote digital DC/DC converters
WO2009008223A1 (en) Multi-output power supply device
US4039925A (en) Phase substitution of spare converter for a failed one of parallel phase staggered converters
US10063050B2 (en) Power supply system and power supply apparatus
KR20150083550A (en) Power supply device and micro server having the same
EP2163998A1 (en) Cooperation circuit
CN102136793B (en) Frequency generator and phase interleaving frequency synchronization device and method
KR100513372B1 (en) Sub-system using clock signals having different frequency for commend/address bus and data bus
JP6191698B2 (en) Power system
JP2003142993A (en) Modulation signal generating device
US10802519B2 (en) Automatic configuration of multiple-phase digital voltage regulator
KR100275442B1 (en) A clock generator using dual port ram
CN113992011A (en) Multiphase switch converter cascade system and voltage conversion circuit thereof
US20050162205A1 (en) Device and method for setting an initial value
JP2012029263A (en) Timer circuit and semiconductor integrated circuit device incorporating the same
JPS60257794A (en) Drive control system for pulse motor

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 1020047007979

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 20038A00206

Country of ref document: CN

AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NI NO NZ OM PG PH PL PT RO RU SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): BW GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2003768750

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 2003768750

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Ref document number: JP