WO2004070786A3 - Detection circuit for mixed asynchronous and synchronous memory operation - Google Patents
Detection circuit for mixed asynchronous and synchronous memory operation Download PDFInfo
- Publication number
- WO2004070786A3 WO2004070786A3 PCT/US2004/002612 US2004002612W WO2004070786A3 WO 2004070786 A3 WO2004070786 A3 WO 2004070786A3 US 2004002612 W US2004002612 W US 2004002612W WO 2004070786 A3 WO2004070786 A3 WO 2004070786A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- memory access
- mode
- detection circuit
- mode detection
- memory
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1694—Configuration of memory controller to different memory types
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1045—Read-write mode select circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
Abstract
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006503177A JP4524759B2 (en) | 2003-02-03 | 2004-01-30 | Detection circuit for mixed asynchronous and synchronous memory operations |
EP04707003A EP1595213A4 (en) | 2003-02-03 | 2004-01-30 | Detection circuit for mixed asynchronous and synchronous memory operation |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/357,862 US6920524B2 (en) | 2003-02-03 | 2003-02-03 | Detection circuit for mixed asynchronous and synchronous memory operation |
US10/357,862 | 2003-02-03 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2004070786A2 WO2004070786A2 (en) | 2004-08-19 |
WO2004070786A3 true WO2004070786A3 (en) | 2005-03-17 |
Family
ID=32771086
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2004/002612 WO2004070786A2 (en) | 2003-02-03 | 2004-01-30 | Detection circuit for mixed asynchronous and synchronous memory operation |
Country Status (6)
Country | Link |
---|---|
US (6) | US6920524B2 (en) |
EP (1) | EP1595213A4 (en) |
JP (1) | JP4524759B2 (en) |
KR (1) | KR100989287B1 (en) |
CN (1) | CN100492320C (en) |
WO (1) | WO2004070786A2 (en) |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6209071B1 (en) * | 1996-05-07 | 2001-03-27 | Rambus Inc. | Asynchronous request/synchronous data dynamic random access memory |
US6690606B2 (en) * | 2002-03-19 | 2004-02-10 | Micron Technology, Inc. | Asynchronous interface circuit and method for a pseudo-static memory device |
US6920524B2 (en) * | 2003-02-03 | 2005-07-19 | Micron Technology, Inc. | Detection circuit for mixed asynchronous and synchronous memory operation |
KR100620645B1 (en) * | 2004-04-13 | 2006-09-13 | 주식회사 하이닉스반도체 | Pseudo SRAM having mode resister set for using in combination with synchronous and asynchronous |
JP2006073062A (en) * | 2004-08-31 | 2006-03-16 | Toshiba Corp | Semiconductor memory device |
US7560956B2 (en) * | 2005-08-03 | 2009-07-14 | Micron Technology, Inc. | Method and apparatus for selecting an operating mode based on a determination of the availability of internal clock signals |
JP4234126B2 (en) | 2005-09-28 | 2009-03-04 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Memory, memory access control method |
KR100738965B1 (en) * | 2006-03-07 | 2007-07-12 | 주식회사 하이닉스반도체 | Circuit and method for detecting synchronous mode in semiconductor memory apparatus |
KR100695289B1 (en) * | 2006-03-09 | 2007-03-16 | 주식회사 하이닉스반도체 | Address Buffer and Method for Buffering Address in Semiconductor Memory Apparatus |
US8266405B2 (en) | 2006-12-13 | 2012-09-11 | Cypress Semiconductor Corporation | Memory interface configurable for asynchronous and synchronous operation and for accessing storage from any clock domain |
KR100873617B1 (en) * | 2007-04-12 | 2008-12-12 | 주식회사 하이닉스반도체 | Active Driver Control Circuit of Semiconductor Memory Apparatus |
US8024511B2 (en) | 2007-08-31 | 2011-09-20 | Siemens Industry, Inc. | Systems, devices, and/or methods to access synchronous RAM in an asynchronous manner |
US7983099B2 (en) | 2007-12-20 | 2011-07-19 | Mosaid Technologies Incorporated | Dual function compatible non-volatile memory device |
KR100929835B1 (en) * | 2008-02-29 | 2009-12-07 | 주식회사 하이닉스반도체 | Semiconductor memory device performing stable initial operation |
US7944773B2 (en) * | 2008-04-30 | 2011-05-17 | Micron Technology, Inc. | Synchronous command-based write recovery time auto-precharge control |
US7920431B2 (en) | 2008-06-02 | 2011-04-05 | Micron Technology, Inc. | Asynchronous/synchronous interface |
KR100974225B1 (en) * | 2008-12-23 | 2010-08-06 | 주식회사 하이닉스반도체 | Impedance calibration period setting circuit and semiconductor integrated circuit |
US7916575B2 (en) * | 2008-12-23 | 2011-03-29 | Emanuele Confalonieri | Configurable latching for asynchronous memories |
US8799909B1 (en) * | 2008-12-23 | 2014-08-05 | Juniper Networks, Inc. | System and method for independent synchronous and asynchronous transaction requests |
US8862966B2 (en) * | 2009-09-09 | 2014-10-14 | Advanced Micro Devices, Inc. | Adjustment of write timing based on error detection techniques |
US8700874B2 (en) * | 2010-09-24 | 2014-04-15 | Telefonaktiebolaget L M Ericsson (Publ) | Digital counter segmented into short and long access time memory |
WO2012145360A2 (en) * | 2011-04-18 | 2012-10-26 | Shaeffer Ian P | Memory circuit and method for its operation |
US9092330B2 (en) | 2013-03-15 | 2015-07-28 | International Business Machines Corporation | Early data delivery prior to error detection completion |
US9430418B2 (en) | 2013-03-15 | 2016-08-30 | International Business Machines Corporation | Synchronization and order detection in a memory system |
US9146864B2 (en) | 2013-03-15 | 2015-09-29 | International Business Machines Corporation | Address mapping including generic bits for universal addressing independent of memory type |
US9142272B2 (en) * | 2013-03-15 | 2015-09-22 | International Business Machines Corporation | Dual asynchronous and synchronous memory system |
US9535778B2 (en) | 2013-03-15 | 2017-01-03 | International Business Machines Corporation | Reestablishing synchronization in a memory system |
US9136987B2 (en) | 2013-03-15 | 2015-09-15 | International Business Machines Corporation | Replay suspension in a memory system |
US10241958B2 (en) * | 2014-08-29 | 2019-03-26 | Microsoft Technology Licensing, Llc | Configurable synchronized processing of multiple operations |
JP6447280B2 (en) * | 2015-03-18 | 2019-01-09 | 富士通株式会社 | Information processing apparatus and emulator program |
US10621119B2 (en) | 2016-03-03 | 2020-04-14 | Samsung Electronics Co., Ltd. | Asynchronous communication protocol compatible with synchronous DDR protocol |
CN109656854A (en) * | 2017-10-12 | 2019-04-19 | 光宝科技股份有限公司 | The reset circuit and its remapping method of solid state storage device |
JP6476325B1 (en) * | 2018-02-01 | 2019-02-27 | 華邦電子股▲ふん▼有限公司Winbond Electronics Corp. | Pseudo SRAM and control method thereof |
CN110059036B (en) * | 2019-04-15 | 2022-04-26 | 西安微电子技术研究所 | Access control device and method for multiple asynchronous interfaces in memory bank |
CN113253796B (en) * | 2021-07-01 | 2021-10-08 | 北京智芯微电子科技有限公司 | Asynchronous input signal synchronization method and device, central processing unit and chip |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5666321A (en) * | 1995-09-01 | 1997-09-09 | Micron Technology, Inc. | Synchronous DRAM memory with asynchronous column decode |
US6597615B2 (en) * | 2000-09-01 | 2003-07-22 | Seiko Epson Corporation | Refresh control for semiconductor memory device |
US6658544B2 (en) * | 2000-12-27 | 2003-12-02 | Koninklijke Philips Electronics N.V. | Techniques to asynchronously operate a synchronous memory |
US6675256B1 (en) * | 1999-11-19 | 2004-01-06 | Stmicroelectronics S.A. | Fast DRAM control method and adapted controller |
US6690606B2 (en) * | 2002-03-19 | 2004-02-10 | Micron Technology, Inc. | Asynchronous interface circuit and method for a pseudo-static memory device |
US6701419B2 (en) * | 2000-10-18 | 2004-03-02 | Stmicroelectronics S.R.L. | Interlaced memory device with random or sequential access |
Family Cites Families (39)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54107637A (en) * | 1978-02-13 | 1979-08-23 | Hitachi Ltd | Control system for dynamic type semiconductor memory unit |
CA1159129A (en) * | 1979-11-27 | 1983-12-20 | Kazuo Murano | Asynchronous transmission system for binary-coded information |
JPS63155494A (en) * | 1986-12-19 | 1988-06-28 | Fujitsu Ltd | Pseudo static memory device |
JPH01128294A (en) * | 1987-11-12 | 1989-05-19 | Sharp Corp | Self-refreshing device for field memory |
JP2519580B2 (en) * | 1990-06-19 | 1996-07-31 | 三菱電機株式会社 | Semiconductor integrated circuit |
US5258952A (en) | 1990-12-14 | 1993-11-02 | Sgs-Thomson Microelectronics, Inc. | Semiconductor memory with separate time-out control for read and write operations |
EP0558079B1 (en) | 1992-02-28 | 1998-04-15 | Sony Corporation | Semiconductor memory device with address transition detector |
EP0574598A1 (en) * | 1992-06-13 | 1993-12-22 | International Business Machines Corporation | Data buffer |
US5374894A (en) | 1992-08-19 | 1994-12-20 | Hyundai Electronics America | Transition detection circuit |
US5510740A (en) * | 1993-04-21 | 1996-04-23 | Intel Corporation | Method for synchronizing clocks upon reset |
US5471157A (en) | 1994-03-31 | 1995-11-28 | Sgs-Thomson Microelectronics, Inc. | Integrated circuit with centralized control of edge transition detection pulse generation |
US5721860A (en) * | 1994-05-24 | 1998-02-24 | Intel Corporation | Memory controller for independently supporting synchronous and asynchronous DRAM memories |
US5696917A (en) * | 1994-06-03 | 1997-12-09 | Intel Corporation | Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory |
US5737748A (en) * | 1995-03-15 | 1998-04-07 | Texas Instruments Incorporated | Microprocessor unit having a first level write-through cache memory and a smaller second-level write-back cache memory |
US5600605A (en) * | 1995-06-07 | 1997-02-04 | Micron Technology, Inc. | Auto-activate on synchronous dynamic random access memory |
US6209071B1 (en) * | 1996-05-07 | 2001-03-27 | Rambus Inc. | Asynchronous request/synchronous data dynamic random access memory |
US5805517A (en) | 1996-12-27 | 1998-09-08 | Intel Corporation | Self-calibrating address transition detection scheme |
US5933369A (en) * | 1997-02-28 | 1999-08-03 | Xilinx, Inc. | RAM with synchronous write port using dynamic latches |
JP3189745B2 (en) * | 1997-06-27 | 2001-07-16 | 日本電気株式会社 | Synchronous semiconductor memory device |
US5835440A (en) | 1997-08-06 | 1998-11-10 | Micron Technology, Inc. | Memory device equilibration circuit and method |
IT1294367B1 (en) | 1997-08-29 | 1999-03-24 | Sgs Thomson Microelectronics | CIRCUITERIA ATD IMMUNE AGAINST SPURIUS PULSES |
JPH11232870A (en) * | 1997-11-26 | 1999-08-27 | Texas Instr Inc <Ti> | Semiconductor memory element having back gate voltage controlling delay circuit |
JPH11238380A (en) | 1998-02-19 | 1999-08-31 | Ricoh Co Ltd | Semiconductor memory circuit |
JP2000163961A (en) * | 1998-11-26 | 2000-06-16 | Mitsubishi Electric Corp | Synchronous semiconductor integrated circuit device |
US6075751A (en) | 1999-01-15 | 2000-06-13 | Intel Corporation | Signal transition detector for asynchronous circuits |
JP2001023372A (en) * | 1999-05-06 | 2001-01-26 | Mitsubishi Electric Corp | Synchronous semiconductor memory |
JP2001155483A (en) * | 1999-11-30 | 2001-06-08 | Mitsubishi Electric Corp | Semiconductor memory |
JP3367519B2 (en) * | 1999-12-03 | 2003-01-14 | 日本電気株式会社 | Semiconductor memory device and test method therefor |
JP3778417B2 (en) | 2000-02-29 | 2006-05-24 | 富士通株式会社 | Semiconductor memory device |
JP3957469B2 (en) * | 2000-04-11 | 2007-08-15 | Necエレクトロニクス株式会社 | Semiconductor memory device |
JP4201490B2 (en) * | 2000-04-28 | 2008-12-24 | 富士通マイクロエレクトロニクス株式会社 | Memory circuit having automatic precharge function and integrated circuit device having automatic internal command function |
JP4060514B2 (en) * | 2000-05-22 | 2008-03-12 | 株式会社東芝 | Synchronous signal generation circuit |
JP2002007200A (en) * | 2000-06-16 | 2002-01-11 | Nec Corp | Memory controller and operation switching method and interface device and semiconductor integrated chip and recording medium |
JP3409059B2 (en) | 2000-07-26 | 2003-05-19 | Necエレクトロニクス株式会社 | Semiconductor storage device |
JP2002150768A (en) * | 2000-11-06 | 2002-05-24 | Fujitsu Ltd | Semiconductor storage device |
JP3624849B2 (en) | 2001-04-02 | 2005-03-02 | セイコーエプソン株式会社 | Semiconductor device, refresh method thereof, memory system, and electronic device |
US6741515B2 (en) * | 2002-06-18 | 2004-05-25 | Nanoamp Solutions, Inc. | DRAM with total self refresh and control circuit |
WO2004001761A1 (en) * | 2002-06-25 | 2003-12-31 | Fujitsu Limited | Semiconductor memory |
US6920524B2 (en) * | 2003-02-03 | 2005-07-19 | Micron Technology, Inc. | Detection circuit for mixed asynchronous and synchronous memory operation |
-
2003
- 2003-02-03 US US10/357,862 patent/US6920524B2/en not_active Expired - Lifetime
-
2004
- 2004-01-30 JP JP2006503177A patent/JP4524759B2/en not_active Expired - Fee Related
- 2004-01-30 CN CNB2004800093316A patent/CN100492320C/en not_active Expired - Lifetime
- 2004-01-30 EP EP04707003A patent/EP1595213A4/en not_active Withdrawn
- 2004-01-30 KR KR1020057014279A patent/KR100989287B1/en not_active IP Right Cessation
- 2004-01-30 WO PCT/US2004/002612 patent/WO2004070786A2/en active Application Filing
-
2005
- 2005-05-13 US US11/129,150 patent/US7320049B2/en not_active Expired - Lifetime
-
2006
- 2006-02-14 US US11/354,786 patent/US7506126B2/en not_active Expired - Fee Related
-
2007
- 2007-03-20 US US11/726,094 patent/US7640413B2/en not_active Expired - Lifetime
-
2009
- 2009-12-09 US US12/634,580 patent/US8082413B2/en not_active Expired - Lifetime
-
2011
- 2011-11-30 US US13/308,333 patent/US9772969B2/en not_active Expired - Lifetime
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5666321A (en) * | 1995-09-01 | 1997-09-09 | Micron Technology, Inc. | Synchronous DRAM memory with asynchronous column decode |
US6675256B1 (en) * | 1999-11-19 | 2004-01-06 | Stmicroelectronics S.A. | Fast DRAM control method and adapted controller |
US6597615B2 (en) * | 2000-09-01 | 2003-07-22 | Seiko Epson Corporation | Refresh control for semiconductor memory device |
US6701419B2 (en) * | 2000-10-18 | 2004-03-02 | Stmicroelectronics S.R.L. | Interlaced memory device with random or sequential access |
US6658544B2 (en) * | 2000-12-27 | 2003-12-02 | Koninklijke Philips Electronics N.V. | Techniques to asynchronously operate a synchronous memory |
US6690606B2 (en) * | 2002-03-19 | 2004-02-10 | Micron Technology, Inc. | Asynchronous interface circuit and method for a pseudo-static memory device |
Non-Patent Citations (1)
Title |
---|
See also references of EP1595213A4 * |
Also Published As
Publication number | Publication date |
---|---|
CN100492320C (en) | 2009-05-27 |
KR20050096177A (en) | 2005-10-05 |
US20070174575A1 (en) | 2007-07-26 |
EP1595213A2 (en) | 2005-11-16 |
EP1595213A4 (en) | 2010-09-08 |
US7320049B2 (en) | 2008-01-15 |
US7506126B2 (en) | 2009-03-17 |
KR100989287B1 (en) | 2010-10-22 |
JP2006517712A (en) | 2006-07-27 |
US7640413B2 (en) | 2009-12-29 |
JP4524759B2 (en) | 2010-08-18 |
WO2004070786A2 (en) | 2004-08-19 |
CN1771481A (en) | 2006-05-10 |
US20120072682A1 (en) | 2012-03-22 |
US20060136692A1 (en) | 2006-06-22 |
US8082413B2 (en) | 2011-12-20 |
US20050207254A1 (en) | 2005-09-22 |
US9772969B2 (en) | 2017-09-26 |
US6920524B2 (en) | 2005-07-19 |
US20040153602A1 (en) | 2004-08-05 |
US20100088483A1 (en) | 2010-04-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2004070786A3 (en) | Detection circuit for mixed asynchronous and synchronous memory operation | |
TW200506960A (en) | ODT mode conversion circuit and method | |
US6707723B2 (en) | Data input circuits and methods of inputting data for a synchronous semiconductor memory device | |
TW357460B (en) | Self-refresh mode semiconductor synchronous dynamic random access memory device (SDRAM device) | |
WO2003003040A3 (en) | Enhanced location methodology for a location system | |
WO2003021600A3 (en) | Methods and apparatus utilizing flash burst mode to improve processor performance | |
TW262557B (en) | Semiconductor memory device | |
US6961278B2 (en) | Synchronous self refresh exit control method and circuit in semiconductor memory device | |
TW200627114A (en) | Internal voltage generation control circuit and internal voltage generation circuit using the same | |
CN100474436C (en) | Methods and apparatus for delay circuit | |
WO2006002278A3 (en) | Apparatus and method for improving dynamic refresh in a semiconductor memory device with reduced stanby power | |
WO2005041055A2 (en) | Echo clock on memory system having wait information | |
TW200713330A (en) | Delay locked loop circuit | |
JP3941974B2 (en) | Data output buffer control method for synchronous memory | |
EP0144836A3 (en) | Address transition pulse circuit | |
US20050111268A1 (en) | Semiconductor memory device to supply stable high voltage during auto-refresh operation and method therefor | |
US6380784B1 (en) | Circuit for generating sense amplifier control signal for semiconductor memory | |
TWI263220B (en) | Semiconductor memory device including internal clock doubler | |
US11417334B2 (en) | Dynamic speech recognition method and apparatus therefor | |
US20040051567A1 (en) | Skew-free dual rail bus driver | |
JPH04258885A (en) | Semiconductor memory device | |
JP2008252864A (en) | Semiconductor device and method for driving the same | |
KR970071813A (en) | Deep power down control circuit | |
KR20010011641A (en) | internal clock generating device for testing | |
TW346628B (en) | Semiconductor memory device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): BW GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
DPEN | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed from 20040101) | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2006503177 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1020057014279 Country of ref document: KR |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2004707003 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 1020057014279 Country of ref document: KR |
|
WWE | Wipo information: entry into national phase |
Ref document number: 20048093316 Country of ref document: CN |
|
WWP | Wipo information: published in national office |
Ref document number: 2004707003 Country of ref document: EP |