WO2004079821A1 - Packaging structure of high frequency semiconductor device, high frequency transmitter and high frequency receiver employing it - Google Patents

Packaging structure of high frequency semiconductor device, high frequency transmitter and high frequency receiver employing it Download PDF

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Publication number
WO2004079821A1
WO2004079821A1 PCT/JP2003/016856 JP0316856W WO2004079821A1 WO 2004079821 A1 WO2004079821 A1 WO 2004079821A1 JP 0316856 W JP0316856 W JP 0316856W WO 2004079821 A1 WO2004079821 A1 WO 2004079821A1
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WIPO (PCT)
Prior art keywords
semiconductor device
frequency semiconductor
mounting structure
ground layer
frequency
Prior art date
Application number
PCT/JP2003/016856
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French (fr)
Japanese (ja)
Inventor
Makoto Yamamoto
Eiji Suematsu
Original Assignee
Sharp Kabushiki Kaisha
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Application filed by Sharp Kabushiki Kaisha filed Critical Sharp Kabushiki Kaisha
Priority to AU2003292839A priority Critical patent/AU2003292839A1/en
Publication of WO2004079821A1 publication Critical patent/WO2004079821A1/en

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0237High frequency adaptations
    • H05K1/0243Printed circuits associated with mounted high frequency components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/4501Shape
    • H01L2224/45012Cross-sectional shape
    • H01L2224/45014Ribbon connectors, e.g. rectangular cross-section
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/141Analog devices
    • H01L2924/1423Monolithic Microwave Integrated Circuit [MMIC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10727Leadless chip carrier [LCC], e.g. chip-modules for cards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954Other details of electrical connections
    • H05K2201/10969Metallic case or integral heatsink of component electrically connected to a pad on PCB
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives

Definitions

  • the present invention relates to a mounting structure of a high-frequency semiconductor device that handles a high-frequency signal, a high-frequency transmitting device using the same, and a high-frequency receiving device.
  • a high-frequency semiconductor device 401 employing a package for mounting a semiconductor element is mounted on an external circuit board 402.
  • Some are surface-mounted (for example, Koriyama, Kitazawa, Shino, and Minamigami, "Surface Mounted Ceramic Package for Millimeter-Wave Module", IEICE, IEICE Technical Report, ED 99-214, January 1999. , VOL. 9
  • the high-frequency semiconductor device 401 includes an insulating substrate 403 made of a dielectric and a high-frequency semiconductor element 404 mounted on the insulating substrate 403.
  • the high-frequency semiconductor element 404 is connected to a first signal line on the surface of the insulating substrate 403 by a wire 410.
  • the first signal line 405 is electromagnetically coupled with the third signal line 429 on the back surface of the insulating substrate 403 via a slot hole 408 provided in the duland layer 407 inside the insulating substrate 403.
  • the third signal line 429 is connected to the second signal line 412 on the surface of the external circuit board 402 by a conductive adhesive such as solder.
  • the external electric circuit board 502 does not have a ground layer, when a signal is transmitted from the first signal line 505 to the second signal line 512 by electromagnetic coupling.
  • the ground of the first signal line 505 does not match the ground of the second signal line.
  • reflection occurs at the end of the first and second signal lines 505 and 512, and transmission loss of a high-frequency signal increases.
  • the wavelength is short and about the same as the size of the high-frequency semiconductor device 501, so that an unnecessary transmission mode is likely to occur and transmission loss of a high-frequency signal is large. It can be lost.
  • the mounting structure disclosed in Japanese Patent Application Laid-Open No. H10-148488 even if a ground layer is provided on the external circuit board 502, the gap between the duland layer and the ground layer of the insulating board 503 can be reduced. As a result, the parallel plate mode, which is an unnecessary transmission mode, is activated, and the transmission loss of high-frequency signals may increase. Disclosure of the invention
  • an object of the present invention is to provide a mounting structure of a high-frequency semiconductor device that can reduce transmission loss of a high-frequency signal and that is easy to mount the high-frequency semiconductor device, and a high-frequency transmitting device and a high-frequency receiving device using the same. is there.
  • a mounting structure of a high-frequency semiconductor device includes a high-frequency semiconductor device having a dielectric substrate and a high-frequency semiconductor element mounted on a surface of the dielectric substrate, and a circuit board.
  • a first signal line provided on a surface of the dielectric substrate and electrically connected to the high-frequency semiconductor element, at least a part of the first signal line is embedded in the dielectric substrate,
  • a first ground layer having a slot hole at a position overlapping with the first signal line;
  • a first auxiliary duland layer provided on the back surface of the dielectric substrate; and a first ground from the first auxiliary durand layer.
  • a conductive adhesive layer provided between the first and second auxiliary ground layers to electrically and physically connect the first and second auxiliary ground layers.
  • the first ground layer which is the ground of the high-frequency semiconductor device, includes the first via-hole conductor, the first auxiliary ground layer, and the second trapping land. It is electrically connected to the second ground layer of the circuit board via the layer and the second via-hole conductor.
  • the first ground layer becomes a good ground (low ground inductance) in terms of high frequency, and the grounds of the first signal line and the second signal line match. As a result, transmission loss of a high-frequency signal can be reduced.
  • the surface area of the first and second auxiliary ground layers is reduced by the first surface.
  • the high-frequency semiconductor device can be easily mounted on the circuit board.
  • first auxiliary duland layer and the second auxiliary duland layer are physically connected, a sufficient connection strength between the high-frequency semiconductor device and the circuit board can be obtained. Further, by making the surface area of the first and second auxiliary ground layers larger than the surface area of the first and second signal lines, it occurs when connecting thin signal lines. There is no need to consider the shape of the adhesive or the like. Therefore, it is possible to realize a mounting structure that is excellent in reproducibility and mass production.
  • At least a part of the high-frequency semiconductor element is contained in a cavity formed on a surface of the dielectric substrate.
  • the first ground in the dielectric substrate is formed.
  • the mounting structure of the high-frequency semiconductor device includes a plurality of the first via holes, and an interval between adjacent ones of the plurality of the first via holes is 0 ⁇ or more and gl Z 4 ( ⁇ gl is the wavelength of the signal in the dielectric substrate).
  • the mounting structure of the high-frequency semiconductor device of the above embodiment since the interval between adjacent ones of the plurality of first vias Ho / Re 1 5 example 4 or less, lambda or gl of wavelengths
  • the signal is the same as having a metal wall, and the electromagnetic wave can be shielded by the first via hole. Therefore, unnecessary transmission modes can be suppressed by the plurality of first via holes.
  • the above interval may be 0 ⁇ m or more. However, if the distance is 50 ⁇ m or more, sufficient mechanical strength of the dielectric substrate can be obtained.
  • the mounting structure of the high-frequency semiconductor device includes a plurality of the second via holes, and an interval between adjacent ones of the plurality of the second via holes is 0 ⁇ or more; L g 2 Z 4 that it is set to: (g 2 signal wavelength during the circuit board) or less.
  • the interval between adjacent ones of the plurality of second via Honore 1 5 below lambda for lambda gl more wavelengths signals It is the same as having a metal wall, and electromagnetic waves can be shielded by a second via hole. Therefore, unnecessary transmission modes can be suppressed by the plurality of second via holes.
  • the above interval may be 0 ⁇ m or more. However, if the distance is 50 ⁇ m or more, sufficient mechanical strength of the dielectric substrate can be obtained.
  • an air layer having a thickness of not less than 5 / xm and not more than 200 / m is interposed between the dielectric substrate and the second signal line.
  • an air layer having a thickness of not less than 5 / xm and not more than 200 / m is interposed between the dielectric substrate and the second signal line.
  • the adhesive layer includes a dielectric having conductivity only in a compressed portion.
  • the adhesive layer since the adhesive layer includes a dielectric material having conductivity only in the compressed portion, the adhesive layer includes the first auxiliary duland layer and the second auxiliary durand layer. By compressing this adhesive layer, only the second auxiliary duland layer can be electrically connected to the first auxiliary ground layer. Therefore, the mounting can be easily performed without concern for the size and shape of the first and second auxiliary ground layers.
  • the first via hole is arranged so as to overlap the high-frequency semiconductor element.
  • the first via holes are arranged in a plurality so as to overlap the high-frequency semiconductor element, heat of the high-frequency semiconductor element is externally transmitted through the first via-hole conductor. Is released efficiently. Therefore, the high-frequency semiconductor element can be favorably operated.
  • the first ground layer has a lower Durand inductance.
  • the mounting structure of the high-frequency semiconductor device is such that the second signal line includes an input section and an output section provided at a predetermined interval from the input section.
  • a plurality of the second via holes are arranged so as to overlap a region between the input section and the output section.
  • the first and second via holes are arranged in a plurality so as to overlap the region between the input unit and the output unit.
  • metal walls can be provided above and below the region. Therefore, unnecessary transmission modes between input and output can be suppressed.
  • an antenna is provided on the back surface of the circuit board.
  • the high-frequency transmission device of the present invention is characterized in that the mounting structure of the high-frequency semiconductor device is used for a front end portion.
  • the front-end portion since the mounting structure of the high-frequency semiconductor device is used for the front-end portion, the front-end portion can be manufactured at low cost and with good reproducibility.
  • a high-frequency receiving device is characterized in that the mounting structure of the high-frequency semiconductor device is used for a front end portion.
  • the front-end portion since the mounting structure of the high-frequency semiconductor device is used for the front-end portion, the front-end portion can be manufactured at low cost and with good reproducibility.
  • FIG. 1 is a schematic end view of a mounting structure of a high-frequency semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic sectional view taken along line 11-11 of FIG.
  • FIG. 3 is a schematic bottom view of the dielectric substrate according to the first embodiment.
  • FIG. 4 is a schematic top view of the external circuit board according to the first embodiment.
  • FIG. 5 is a schematic cross-sectional view of the dielectric substrate of the above-described millimeter-wave semiconductor device.
  • FIG. 6 is a graph showing the results of measuring the transmission characteristics (S 21) and the reflection characteristics (S 11) of the electromagnetic coupling portion.
  • FIG. 7 is a schematic end view of the mounting structure of the high-frequency semiconductor device according to the second embodiment of the present invention.
  • FIG. 8 is a schematic end view of the mounting structure of the high-frequency semiconductor device according to the third embodiment of the present invention.
  • FIG. 9 is a schematic bottom view of the dielectric substrate according to the third embodiment.
  • FIG. 10 is a schematic top view of the external circuit board according to the third embodiment.
  • FIG. 11 is a schematic end view of the mounting structure of the high-frequency semiconductor device according to the fourth embodiment of the present invention.
  • FIG. 12 is a schematic configuration diagram of the transmission / reception device.
  • FIG. 13 is a schematic end view of a mounting structure of a conventional high-frequency semiconductor device.
  • FIG. 14 is a schematic end view of a mounting structure of another conventional high-frequency semiconductor device.
  • FIG. 1 shows a schematic end view of the mounting structure of the high-frequency semiconductor device according to the first embodiment of the present invention.
  • the millimeter-wave semiconductor device 1 as an example of the high-frequency semiconductor device is mounted on the external circuit board 2 as an example of the circuit board.
  • the above-described millimeter-wave semiconductor device 1 includes a dielectric substrate 3 having a back surface facing the front surface of an external circuit board 2, and an MM IC (monolithic microwave) as an example of a high-frequency semiconductor element mounted on the surface of the dielectric substrate 3.
  • Integrated circuit 4.
  • a first signal line 5 is provided on the surface of the dielectric substrate 3, and the first signal line 5 and the MMIC 4 are electrically connected by wires 10.
  • a cavity 9 for housing the MM IC 4 is formed on the surface of the dielectric substrate 3.
  • the MMIC 4 is sealed by a lid 11 made of a radio wave absorber. Also, a part of the first ground layer 7 is exposed from the cavity 9 and is in contact with the bottom surface of the MMIC 4. The remaining part of the first duland layer 7 is embedded in the dielectric substrate 3.
  • the ground layer 7 has a slot hole 8 at a position overlapping the first signal line 5.
  • a second signal line 12 facing the first signal line 5 is provided through a slot hole 8 of the first duland layer 7, and on the back surface of the external circuit board 2 Is provided with a second ground layer 13.
  • the second signal line 12 includes an input section 12a and an output section 12b provided at a predetermined interval from the input section 12a.
  • FIG. 2 is a schematic sectional view taken along the line II-II in FIG.
  • a first auxiliary ground layer 6 is provided on the back surface of the dielectric substrate 3.
  • a plurality of first via holes 15 extending from the first auxiliary duland layer 6 to the first ground layer 7 are formed on the back surface side of the dielectric substrate 3.
  • Each first via hole 15 is filled with a first via-hole conductor 16.
  • the first ground layer 7 and the first auxiliary duland layer 6 are electrically connected by the first via-hole conductor 16.
  • a second auxiliary ground layer 14 facing the first auxiliary ground layer 6 is provided on the surface of the external circuit board 2.
  • the second auxiliary ground layer 14 and the first auxiliary ground layer 6 are electrically and physically connected by a conductive adhesive layer 17.
  • a plurality of second via holes 18 extending from the front surface to the rear surface are formed. That is, the plurality of second via holes 18 penetrate the external circuit board 2.
  • Each second via hole 18 is filled with a second viahorne conductor 19.
  • the second via-hole conductor 19 electrically connects the second auxiliary ground layer 14 to the second ground layer 13.
  • first signal line 5 and the second signal line 12 are electromagnetically connected via the slot hole 8 of the first duland layer 7. Then, only the air layer 20 is interposed between the dielectric substrate 3 and the second signal line 12.
  • a first auxiliary ground layer 6, a second signal line 12, a second auxiliary ground layer 14, and an adhesive layer 17 are provided between the external circuit board 2 and the dielectric substrate 3. There is an area that is not provided.
  • a power supply terminal 21 is provided in addition to the first auxiliary ground layer 6.
  • a distance between adjacent ones of the plurality of first via holes 15 at the closest distance S i is set to 0 / m or more; IS i 4, ( ⁇ gl : frequency of a signal in the dielectric substrate 3) is set to the following.
  • W is set to, for example, 800 / zm.
  • a power supply line 22 composed of a microstrip line is also provided on the surface of the external circuit board 2.
  • the second signal line 12 and the second auxiliary durand layer 14 are also formed of microstrip lines, and the surface area of the second signal line 12 is smaller than that of the second auxiliary ground layer 14. The surface area is larger.
  • the interval S 2 between the plurality of second via holes 18 adjacent to each other at the closest distance is ⁇ ⁇ or more; g 2 Z 4 ( ⁇ g 2 : frequency of a signal in the external circuit board 2) It is set as follows. Incidentally, W 2 is set to, for example, 8 0 0 ⁇ ⁇ .
  • first auxiliary ground layer 6 is connected to the second auxiliary ground layer 14 and the power supply terminal 21 is connected to the power supply fountain path 22 by an adhesive such as solder. 1 is mounted on the external circuit board 2.
  • a power supply line 23 of the MMIC 4 is also provided on the surface of the dielectric substrate 3, in addition to the first signal line 5, a power supply line 23 of the MMIC 4 is also provided.
  • the power supply line 23 and the power supply terminal 21 shown in FIG. 3 are connected by a third via hole 24.
  • the power supply line 23 and the power supply terminal 21 are electrically connected.
  • the first ground layer 7, which is a land in the millimeter-wave semiconductor device 1 is connected to the second ground layer on the back surface of the external circuit board 2 via a plurality of via-hole conductors 16. Since it is electrically connected to the layer 13, it is also a good ground (low ground inductance) at high frequencies, and when a signal is transmitted from the first signal line 5 to the second signal line 12.
  • the Durand transform is performed favorably.
  • the external circuit board 2 is electrically and physically connected to the first ground layer 7 of the millimeter-wave semiconductor device 1, the signal line does not need to be physically connected, and the first signal line 5 is directly connected. Since it is electromagnetically coupled to the second signal line 12 composed of the microstrip line of the external circuit board 2, it is possible to extract a millimeter wave signal from the external circuit board 2 with low loss.
  • the MM IC 4 Since the above-mentioned millimeter-wave semiconductor device 1 has a cavity structure, the MM IC 4 The land surface and the first ground layer 6 of the millimeter-wave semiconductor device 1 are aligned, and low ground inductance can be realized in view of the MM IC 4.
  • the lid 11 is formed of a radio wave absorber, unnecessary oscillation does not occur, and stable high-frequency characteristics can be obtained.
  • first and second auxiliary ground layers 6 and 14 have a large surface area so as to cover the first auxiliary ground layer 18, the first auxiliary ground layer 6 and the second auxiliary ground layer 14 Fine connection ⁇ , no alignment required. Therefore, the first auxiliary ground layer 6 and the second auxiliary ground layer 14 can be easily connected.
  • first auxiliary duland layer 6 and the second auxiliary duland layer 14 are bonded to each other with an adhesive layer.
  • connection strength can be secured.
  • connection between the first auxiliary duland layer 6 and the second auxiliary duland layer 14 is a connection between patterns having a large surface area, the shape of an adhesive layer generated when connecting thin signal lines is formed. No characteristic degradation due to As a result, a millimeter-wave mounting structure with excellent reproducibility and mass productivity can be realized.
  • the distance S i between adjacent ones of the plurality of first via holes 15 closest to each other at the closest distance is less than gl 4, there is a metal wall for a signal having a wavelength of ⁇ gl or more.
  • the electromagnetic wave can be shielded by the first via hole 15. Therefore, the unnecessary transmission mode can be suppressed by the plurality of first via holes 15.
  • the interval S 2 between the adjacent second via holes 18 at the closest distance among the plurality of second via holes 18 is set to Ig 2 Z4 or less, electromagnetic waves can also be transmitted through the plurality of second via holes 18. It can be shielded and the unnecessary transmission mode can be further suppressed.
  • the spacing S 1 of those same workers adjacent the closest distance among the plurality of the first via hole 1 5; gl 4 and below, adjacent the closest distance among the plurality of second via hole 1 8 Since the distance S 2 between the two is less than or equal to g 2 Z4, the first ground layer 7 ⁇ the second duland layer 1 3 ⁇ the plurality of first via holes 1 5 'the plurality of second via holes At 18, a pseudo waveguide is formed. Therefore, the distance between the first via holes 15 and the distance between the second via holes 18 W 2 And ⁇ g / 2 (where ⁇ g is the dielectric forming the dielectric substrate 3, the air layer 20) and the dielectric forming the external circuit board 2.
  • the frequency at which the effective dielectric constant is equal to the wavelength of a signal in a material having the same dielectric constant) is the cut-off frequency, and unnecessary waveguide modes can be suppressed.
  • signals below the power-off frequency cannot exist inside the pseudo waveguide except in the propagation mode of the microstrip, so that unnecessary transmission modes can be suppressed.
  • the interval SL between the first via holes 15 is set to 50 ⁇ m or more, a decrease in the mechanical strength of the dielectric substrate 3 can be prevented.
  • the thickness of the air layer 20 can be controlled by controlling the amount of solder paste applied.
  • FIG. 6 shows an example of the results of measurement and evaluation of the transmission characteristics (S 21) and the reflection characteristics (S 11) of the electromagnetic coupling portion while changing the thickness h of the air layer 20.
  • the dielectric substrate 3 was an alumina ceramic having a dielectric constant of 8.7
  • the external circuit board 2 was a glass ceramic having a dielectric constant of 5.7
  • the dimensions of the slot hole 8 were 900 / zm X 20 0 m
  • the first signal line 5 has a width of 160 / im
  • the distance from one end of the first signal line 5 to the center line of the slot 8 (the distance indicated by L1 in FIG.
  • the second signal line 12 has a width of 180 ⁇ m, and the distance from one end of the second signal line 12 to the center line of the slot hole 8 (the distance indicated by L 2 in FIG. 1) is 5 0 ⁇ m, the thickness of the dielectric substrate 3 is 300 ⁇ m, the first ground layer 7 is located just halfway between the first signal line 5 and the first auxiliary duland layer 6, The thickness of the external circuit board 2 is 150 / zm.
  • solder was used as the adhesive layer 17.
  • the thickness h of the air layer 20 when the thickness h of the air layer 20 is set to 50 ⁇ , the return loss is the largest, and the input / output impedance matching is good. As described above, by adjusting the thickness h of the air layer 20, it is possible to match the input / output impedance.
  • the thickness of the air layer 20 is 5 ⁇ It is desirable to set it to 200 im or less.
  • the thickness of the adhesive layer be set to 5 / zm or more and 200 ⁇ ni or less.
  • the distance D be L4 or more.
  • the first signal line 5 and the MM IC 4 are electrically connected to each other by the wire 10.
  • the first signal line 5 and the MM IC 4 may be electrically connected by, for example, a repone or TAB (Tape Automated Bonding). Good.
  • FIG. 7 shows a schematic end view of the mounting structure of the high-frequency semiconductor device according to the second embodiment of the present invention.
  • the same components as those shown in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and description thereof is omitted.
  • an example of an adhesive layer for mounting the millimeter-wave semiconductor device 1 on the external circuit board 2 is an ACF (Anisotropic Conductive Film: ACF) having conductivity only in a vertically compressed portion.
  • An adhesive layer 117 containing a dielectric such as raw conductive finolem) is used.
  • only the adhesive layer 117 is interposed between the dielectric substrate 3 and the second signal line 12.
  • a film having a size similar to that of the bottom surface of the millimeter-wave semiconductor device 1 may be attached and mounted, and the first auxiliary dry layer 6 and There is no need to worry about the size and shape of the second auxiliary ground layer 14, and the second auxiliary ground layer 14 can be easily mounted.
  • FIG. 8 shows a schematic end view of the mounting structure of the high-frequency semiconductor device according to the second embodiment of the present invention.
  • the same components as those shown in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and description thereof is omitted.
  • a part of the second auxiliary ground layer 214 is interposed between the input section 12a and the output section 12b.
  • the first auxiliary ground layer 206 is placed on the back of the dielectric substrate 203 so as to face the second auxiliary ground layer 214. It is provided on the surface.
  • the first auxiliary duland layer 206 and the second auxiliary duland layer 214 are electrically and physically connected by a conductive adhesive layer 217.
  • a part interposed between the input section 12 a and the output section 12 b is a second via-hole conductor 2 in the second via-hole 2 18. At 19, it is electrically connected to the second ground layer 13.
  • a part of the first auxiliary ground layer 206 facing the part is electrically connected to the first duland layer 7 by the first viahorn conductor 2 16 in the first viahorn 21. It is connected to the.
  • the first auxiliary ground layer 206 has a pattern as shown in FIG.
  • the first auxiliary ground layer 206 is provided with one end portion 206 a provided on the upper surface of the back surface of the dielectric substrate 203 in the drawing, and the lower surface of the dielectric substrate 203 in the drawing. It comprises a lower end portion 206 b provided on the lower side, and a connecting portion 206 c connecting the one end portion 206 a and the other end portion 206 b.
  • the above-mentioned one end 206 a, the other end 206 b and the connecting part 206 c are respectively O / xm or more; gl / 4 ( ⁇ g: frequency of a signal in the dielectric substrate 203) ) Connected to the first via holes 215 arranged at the following intervals.
  • the second auxiliary ground layer 214 is provided with an end portion 214a provided on the upper surface of the back surface of the external circuit board 202 as an example of a circuit board, and an external circuit board 202.
  • the other end 2 14 b provided on the lower side in the figure on the back side of the figure and a connecting portion 2 14 c connecting the one end 2 14 a and the other end 2 14 b .
  • the connecting portion 2 14 c is located between the input portion 12 a and the output portion 12 b.
  • the second via holes 218 arranged at the following intervals are connected.
  • the first and second via-hole conductors 2 16 and 2 19 exist above and below the region between the input section 12 a and the output section 12 b, This is the same state as when there is a metal wall in that area, and unnecessary transmission modes are suppressed between input and output, enabling pure signal transmission.
  • the first via hole is also provided in the portion of the first ground layer 7 where the MM IC 4 contacts. Since the first and second holes are connected, the heat of the MM IC 4 is easily diffused to the outside via the first via-hole conductor 216 in the first via-hole 215. As a result, the MM IC 4 can operate well.
  • one end portion 206 a, the other end portion 206 b and the connecting portion 206 c are connected to each other in the first auxiliary ground layer 206.
  • the second auxiliary duland layer 2 14 one end 2 14 a, the other end 2 14 b and the connecting portion 2 14 c are connected, but one end 2 14 a, There may be a predetermined gap between the other end portion 214b and the connecting portion 214. That is, the second auxiliary ground layer of the present invention may be formed of a plurality of different patterns formed at predetermined intervals.
  • FIG. 11 shows a schematic end view of the mounting structure of the high-frequency semiconductor device according to the fourth embodiment of the present invention.
  • the same components as those shown in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and description thereof is omitted.
  • the millimeter-wave semiconductor device 1 is mounted on an external circuit board 302 as an example of a circuit board.
  • an external circuit board 302 On the back surface of the external circuit board 302, a microstrip patch antenna 326 as an example of an antenna and a feed line 327 connected to the microstrip patch antenna 326 are provided.
  • a second signal line 312 including an input section and an output section is provided on the surface of the external circuit board 302.
  • a second ground layer 313 having a slot hole 328 is embedded in the external circuit board 302.
  • microstrip patch antenna 32 6 is connected to the external circuit board 302 Since it is on the back side, it is possible to reduce the size of the high-frequency circuit integrated with the antenna.
  • FIG. 12 shows a schematic configuration diagram of a transmission / reception device using the mounting structure of the high-frequency semiconductor device of the present invention.
  • the transmission / reception device includes a transmission device 60 as an example of a high-frequency transmission device, and a reception device 70 as an example of a high-frequency reception device.
  • the transmission device 60 will be described.
  • the data signal input to the input terminal 61 is modulated by the modulator 62, and then transmitted to the front end unit 80 as an intermediate frequency signal, and is first input to the mixer 63. Is done.
  • a local oscillation signal generated by the local oscillator 69 is also input to the mixer 63.
  • the local oscillator 69 includes a PLL (Phase Locked Loop) oscillator 67 and a frequency multiplier 68.
  • the signal oscillated by the PLL oscillator 67 is frequency-doubled by the frequency doubler 68 and then input to the mixer 63 as a local oscillation signal.
  • PLL Phase Locked Loop
  • the mixer 63 creates an RF (radio frequency) signal by mixing the local oscillation signal and the intermediate frequency signal, and outputs the RF (radio frequency) signal to a BPF (bandpass filter) 64 in the next stage.
  • the RF signal is transmitted through the antenna 66 after the unnecessary components are removed by the BP 64 and the power is amplified by the amplifier 65.
  • the receiving device 70 the received signal input from the antenna 76 of the front end unit 90 is amplified only by the amplifier 75, and then only the desired wave signal from which unnecessary components have been removed by the BPF 74. Is input to the mixer 73. Further, a local oscillation signal generated by a local oscillator 79 is also input to the mixer 73. This local oscillator 79? ! ⁇ An oscillator 77 and a frequency multiplier 78 are provided. The frequency of the signal oscillated by the PLL oscillator 77 is multiplied by a frequency multiplier 78 and then input to the mixer 73 as a local oscillation signal.
  • the mixer 73 creates an intermediate frequency signal by mixing the local oscillation signal and the desired wave signal, and inputs the intermediate frequency signal to the demodulator 72.
  • the intermediate frequency signal is demodulated by the demodulator 72, converted back to a data signal, and output from the output terminal 71.
  • the front end sections 80 and 90 use a mounting structure of a millimeter-wave semiconductor device as an example of the present invention. At least one MM IC is mounted on the millimeter-wave semiconductor device, and a microstrip is provided on the back surface.
  • a millimeter-wave semiconductor device is mounted on an external circuit board having a patch antenna.
  • the front end sections 80 and 90 use the mounting structure of the millimeter-wave semiconductor device of the present invention, which does not need to connect thin signal lines and does not require fine positioning, so that the reproducibility is low and the cost is low. Is excellent.
  • the present invention is not limited to Embodiments 1 to 5, but can also be used for a mounting structure of a microphone mouth wave semiconductor device that handles a microphone mouth wave.
  • first ground layer of the present invention may be embedded in the dielectric substrate.

Abstract

In a high frequency semiconductor device (1), a first ground layer (7) on the surface of a dielectric substrate (3) is connected with a first auxiliary ground layer (6) on the back surface of the dielectric substrate (3) through a via hole conductor (16). A second ground layer (13) on the back surface of an outer circuit board (2) is connected with a second auxiliary ground layer (14) on the surface of the outer circuit board (2) through a via hole conductor (19). The first auxiliary ground layer (6) and the second auxiliary ground layer (14) are connected electrically and physically through a conductive adhesive layer (17). Transmission loss of high frequency signal can thereby be reduced and a structure for packaging a high frequency semiconductor device easily is provided along with a high frequency transmitter and a high frequency receiver employing it.

Description

高周波半導体装置の実装構造及びこれを用いた高周波送信装置並びに高周波受信 Mounting structure of high-frequency semiconductor device, high-frequency transmission device using the same, and high-frequency reception
技術分野 Technical field
本発明は、 高周波信号を取り扱う高周波半導体装置の実装構造及びこれを用い た高周波送信装置並びに高周波受明信装置に関する。 背景技術 田 マイクロ波ゃミリ波の高周波信号を取り扱う高周波半導体装置の実装構造とし ては、 図 13に示すように、 半導体素子搭載用パッケージを採用した高周波半導 体装置 401を外部回路基板 402に表面実装したものがある (例えば、 郡山, 北澤, 志野, 南上, 「ミリ波モジュール用表面実装セラミックパッケージ」 , 電 子情報通信学会, 信学技報, ED 99— 214, 1999年 1 1月, VOL. 9 The present invention relates to a mounting structure of a high-frequency semiconductor device that handles a high-frequency signal, a high-frequency transmitting device using the same, and a high-frequency receiving device. BACKGROUND ART As a mounting structure of a high-frequency semiconductor device that handles high-frequency signals of microwaves to millimeter waves, as shown in FIG. 13, a high-frequency semiconductor device 401 employing a package for mounting a semiconductor element is mounted on an external circuit board 402. Some are surface-mounted (for example, Koriyama, Kitazawa, Shino, and Minamigami, "Surface Mounted Ceramic Package for Millimeter-Wave Module", IEICE, IEICE Technical Report, ED 99-214, January 1999. , VOL. 9
9, NO. 440, p. 35— 42参照。 ) 。 See 9, NO.440, p.35-42. ).
上記高周波半導体装置 401は、 誘電体からなる絶縁基板 403と、 この絶縁 基板 403に搭載された高周波半導体素子 404とを備えている。 この高周波半 導体素子 404は、 ワイヤ 410により絶縁基板 403の表面の第 1の信号線路 The high-frequency semiconductor device 401 includes an insulating substrate 403 made of a dielectric and a high-frequency semiconductor element 404 mounted on the insulating substrate 403. The high-frequency semiconductor element 404 is connected to a first signal line on the surface of the insulating substrate 403 by a wire 410.
405と電気的に接続されている。 そして、 上記第 1の信号線路 405は、 絶縁 基板 403内部のダランド層 407に設けられたスロット孔 408を介して絶縁 基板 403の裏面の第 3の信号線路 429と電磁結合する。 また、 上記第 3の信 号線路 429力 外部回路基板 402の表面の第 2の信号線路 412と半田等の 導電性接着材で接続されている。 It is electrically connected to 405. Then, the first signal line 405 is electromagnetically coupled with the third signal line 429 on the back surface of the insulating substrate 403 via a slot hole 408 provided in the duland layer 407 inside the insulating substrate 403. In addition, the third signal line 429 is connected to the second signal line 412 on the surface of the external circuit board 402 by a conductive adhesive such as solder.
しかし、 図 13の高周波半導体装置の実装構造では、 とても細い第 2, 第 3の 信号線路 412, 429同士を接着材により接続しなければならないため、 第 2 の信号線路 412と第 3の信号線路 429とを精度よく接続するのが難しく、 第 However, in the mounting structure of the high-frequency semiconductor device shown in FIG. 13, since the very thin second and third signal lines 412 and 429 must be connected to each other with an adhesive, the second signal line 412 and the third signal line It is difficult to connect with 429 with high accuracy.
2の信号線路 412と第 3の信号線路 429との接続の再現性が悪レヽという問題 がある。 さらに、 上記高周波半導体装置 401と外部回路基板 402との実装部 分での反射により、 高周波信号の伝送特性が劣化してしまうという問題がある。 従来、 このような問題を解決する高周波半導体装置の実装構造が、 特開平 1 0 - 1 4 4 8 1 8号公報に開示されている。 この高周波半導体装置の実装構造では、 図 1 4に示すように、 高周波半導体装置 5 0 1を外部回路基板 5 0 2に実装する ことによって、 第 1の信号線路 5 0 5が、 絶縁基板 5 0 3内部のグランド層 5 0 7に設けられたスロット孔 5 0 8を介して第 2の信号線路 5 1 2と直接電磁結合 する。 このように、 上記第 1の信号線路 5 0 5が第 2の信号線路 5 1 2と直接電 磁結合するので、 実装部分で特性が劣化することがなくなる。 There is a problem that the reproducibility of connection between the second signal line 412 and the third signal line 429 is poor. Further, a mounting portion of the high-frequency semiconductor device 401 and the external circuit board 402 There is a problem in that the transmission characteristics of a high-frequency signal are degraded due to reflection at each minute. Conventionally, a mounting structure of a high-frequency semiconductor device that solves such a problem is disclosed in Japanese Patent Application Laid-Open No. 10-148188. In this mounting structure of the high-frequency semiconductor device, as shown in FIG. 14, by mounting the high-frequency semiconductor device 501 on the external circuit board 502, the first signal line 505 becomes the insulating substrate 50 (3) Direct electromagnetic coupling with the second signal line 512 via a slot hole 508 provided in the internal ground layer 507. As described above, the first signal line 505 is directly electromagnetically coupled to the second signal line 512, so that the characteristics are not deteriorated in the mounting part.
しかしながら、 上記構造では、 外部電気回路基板 5 0 2にグランド層がないた め、 第 1の信号線路 5 0 5から第 2の信号線路 5 1 2へ信号が電磁結合により伝 送される際に、 第 1の信号線路 5 0 5のグランドと第 2のグランドとがー致しな くなる。 その結果、 上記第 1 , 第 2の信号線路 5 0 5 , 5 1 2の線路端で反射が 生じ、 高周波信号の伝送損失が大きくなるという問題がある。  However, in the above structure, since the external electric circuit board 502 does not have a ground layer, when a signal is transmitted from the first signal line 505 to the second signal line 512 by electromagnetic coupling. However, the ground of the first signal line 505 does not match the ground of the second signal line. As a result, there is a problem that reflection occurs at the end of the first and second signal lines 505 and 512, and transmission loss of a high-frequency signal increases.
また、 上記高周波半導体装置 5 0 1がミリ波を取り扱う場合、 波長が短く高周 波半導体装置 5 0 1のサイズと同程度となるため、 不要伝送モードが立ちやすく、 高周波信号の伝送損失が大きくなつてしまうことがある。 例えば、 特開平 1 0— 1 4 4 8 1 8号公報の実装構造においては、 外部回路基板 5 0 2にグランド層を 設けても、 このダランド層と絶縁基板 5 0 3のグランド層との間で不要伝送モー ドである平行平板モードが立ち、 高周波信号の伝送損失が大きくなってしまう恐 れがある。 発明の開示  When the high-frequency semiconductor device 501 handles millimeter waves, the wavelength is short and about the same as the size of the high-frequency semiconductor device 501, so that an unnecessary transmission mode is likely to occur and transmission loss of a high-frequency signal is large. It can be lost. For example, in the mounting structure disclosed in Japanese Patent Application Laid-Open No. H10-148488, even if a ground layer is provided on the external circuit board 502, the gap between the duland layer and the ground layer of the insulating board 503 can be reduced. As a result, the parallel plate mode, which is an unnecessary transmission mode, is activated, and the transmission loss of high-frequency signals may increase. Disclosure of the invention
そこで、 本発明の課題は、 高周波信号の伝送損失を低減できて、 高周波半導体 装置の実装が容易な高周波半導体装置の実装構造及びこれを用いた高周波送信装 置並びに高周波受信装置を提供することにある。  Therefore, an object of the present invention is to provide a mounting structure of a high-frequency semiconductor device that can reduce transmission loss of a high-frequency signal and that is easy to mount the high-frequency semiconductor device, and a high-frequency transmitting device and a high-frequency receiving device using the same. is there.
上記課題を解決するため、 本発明の高周波半導体装置の実装構造は、 誘電体基 板と上記誘電体基板の表面に搭載された高周波半導体素子とを有する高周波半導 体装置と、 回路基板とを備え、 上記誘電体基板の裏面を上記回路基板の表面に対 向させて、 上記高周波半導体装置を上記回路基板に実装した高周波半導体装置の 実装構造において、 上記誘電体基板の表面に設けられると共に、 上記高周波半導 体素子に電気的に接続された第 1の信号線路と、 上記誘電体基板内に少なくとも 一部が埋め込まれ、 上記第 1の信号線路に重なる位置にスロット孔を有する第 1 のグランド層と、 上記誘電体基板の裏面に設けられた第 1の補助ダランド層と、 上記第 1の補助ダランド層から上記第 1のグランド層に達する第 1のビアホール と、 上記第 1のビアホーノレ内を埋める第 1のビアホール導電体と、 上記回路基板 の表面に設けられ、 上記第 1のダランド層のス口ット孔を介して上記第 1の信号 線路に対向する第 2の信号線路と、 上記回路基板の表面に設けられ、 上記第 1の 補助ダランド層に対向する第 2の補助ダランド層と、 上記回路基板の裏面に設け られた第 2のグランド層と、 上記回路基板を貫通する第 2のビアホールと、 上記 第 2のビアホール内を埋める第 2のビアホール導電体と、 上記第 1の補助グラン ド層と上記第 2の補助ダランド層との間に設けられ、 上記第 1の補助グランド層 と上記第 2の補助ダランド層とを電気的かつ物理的に接続する導電性の接着剤層 とを備えたことを特徴としている。 In order to solve the above-mentioned problems, a mounting structure of a high-frequency semiconductor device according to the present invention includes a high-frequency semiconductor device having a dielectric substrate and a high-frequency semiconductor element mounted on a surface of the dielectric substrate, and a circuit board. A high-frequency semiconductor device having the high-frequency semiconductor device mounted on the circuit board with the back surface of the dielectric substrate facing the front surface of the circuit substrate. In the mounting structure, a first signal line provided on a surface of the dielectric substrate and electrically connected to the high-frequency semiconductor element, at least a part of the first signal line is embedded in the dielectric substrate, A first ground layer having a slot hole at a position overlapping with the first signal line; a first auxiliary duland layer provided on the back surface of the dielectric substrate; and a first ground from the first auxiliary durand layer. A first via hole reaching the layer, a first via hole conductor filling the first via hole, and a first via hole conductor provided on the surface of the circuit board, and the first via hole through the slot hole of the first duland layer. A second signal line opposing the first signal line; a second auxiliary duland layer provided on the front surface of the circuit board, opposing the first auxiliary duland layer; and a second signal line provided on the back surface of the circuit substrate. The second A land layer, a second via hole penetrating the circuit board, a second via-hole conductor filling the second via hole, the first auxiliary ground layer and the second auxiliary duland layer. A conductive adhesive layer provided between the first and second auxiliary ground layers to electrically and physically connect the first and second auxiliary ground layers.
上記構成の高周波半導体装置の実装構造によれば、 上記高周波半導体装置のグ ランドである第 1のグランド層は、 第 1のビアホール導電体、 第 1の補助グラン ド層、 第 2の捕助ダランド層および第 2のビアホール導電体を介して回路基板の 第 2のグランド層と電気的に接続している。 これにより、 上記第 1のグランド層 は高周波的にも良好なグランド (低グランドインダクタンス) となり、 第 1の信 号線路と第 2の信号線路のグランドが一致する。 その結果、 高周波信号の伝送損 失を低減することができる。  According to the mounting structure of the high-frequency semiconductor device having the above configuration, the first ground layer, which is the ground of the high-frequency semiconductor device, includes the first via-hole conductor, the first auxiliary ground layer, and the second trapping land. It is electrically connected to the second ground layer of the circuit board via the layer and the second via-hole conductor. Thus, the first ground layer becomes a good ground (low ground inductance) in terms of high frequency, and the grounds of the first signal line and the second signal line match. As a result, transmission loss of a high-frequency signal can be reduced.
加えて、 上記第 1の補助ダランド層と第 2の補助グランド層とを導電性の接着 剤層で電気的かつ物理的に接続するので、 第 1 , 第 2の補助グランド層の表面積 を第 1 , 第 2の信号線路の表面積よりも大きくして、 高周波半導体装置を回路基 板に容易に実装することができる。  In addition, since the first auxiliary duland layer and the second auxiliary ground layer are electrically and physically connected by a conductive adhesive layer, the surface area of the first and second auxiliary ground layers is reduced by the first surface. By making the surface area larger than the surface area of the second signal line, the high-frequency semiconductor device can be easily mounted on the circuit board.
また、 上記第 1の補助ダランド層と第 2の補助ダランド層とを物理的に接続す るので、 高周波半導体装置と回路基板との十分な接続強度を得ることができる。 さらには、 上記第 1, 第 2の補助グランド層の表面積を第 1 , 第 2の信号線路 の表面積よりも大きくすることにより、 細い信号線路同士を接続する際に生じる 接着材の形状等を問題にする必要が無くなる。 したがって、 再現性'量産性に優 れた実装構造を実現することが可能となる。 In addition, since the first auxiliary duland layer and the second auxiliary duland layer are physically connected, a sufficient connection strength between the high-frequency semiconductor device and the circuit board can be obtained. Further, by making the surface area of the first and second auxiliary ground layers larger than the surface area of the first and second signal lines, it occurs when connecting thin signal lines. There is no need to consider the shape of the adhesive or the like. Therefore, it is possible to realize a mounting structure that is excellent in reproducibility and mass production.
一実施形態の高周波半導体装置の実装構造は、 上記誘電体基板の表面に形成さ れたキヤビティ内に、 上記高周波半導体素子の少なくとも一部が入っている。 上記実施形態の高周波半導体装置の実装構造によれば、 上記誘電体基板の表面 に形成されたキヤビティ内に、 高周波半導体素子の少なくとも一部が入っている ので、 誘電体基板内の第 1のグランド層をキヤビティから露出させることにより、 高周波半導体素子を第 1のダランド層に直接接触させることができる。 その結果、 上記高周波半導体素子からみて低ダランドィンダクタンスを実現できる。  In one embodiment of the mounting structure of the high-frequency semiconductor device, at least a part of the high-frequency semiconductor element is contained in a cavity formed on a surface of the dielectric substrate. According to the mounting structure of the high-frequency semiconductor device of the above embodiment, since at least a part of the high-frequency semiconductor element is contained in the cavity formed on the surface of the dielectric substrate, the first ground in the dielectric substrate is formed. By exposing the layer from the cavity, the high-frequency semiconductor device can be brought into direct contact with the first duland layer. As a result, low duland conductance can be realized from the viewpoint of the high-frequency semiconductor element.
一実施形態の高周波半導体装置の実装構造は、 上記第 1のビアホールは複数あ つて、 上記複数の第 1のビアホールのうちの隣り合うもの同士の間隔は 0 μ πι以 上え g lZ 4 ( λ g l:上記誘電体基板中における信号の波長) 以下に設定されて いる。 In one embodiment, the mounting structure of the high-frequency semiconductor device includes a plurality of the first via holes, and an interval between adjacent ones of the plurality of the first via holes is 0 μππ or more and gl Z 4 (λ gl is the wavelength of the signal in the dielectric substrate).
上記実施形態の高周波半導体装置の実装構造によれば、 上記複数の第 1のビア ホー/レ 1 5のうちの隣り合うもの同士の間隔をえ 4以下にしているので、 λ g l以上の波長の信号にとっては金属の壁があるのと同じであり、 電磁波を第 1のビアホールで遮蔽することができる。 したがって、 上記複数の第 1のビアホ ールで不要伝送モードを抑えることができる。 According to the mounting structure of the high-frequency semiconductor device of the above embodiment, since the interval between adjacent ones of the plurality of first vias Ho / Re 1 5 example 4 or less, lambda or gl of wavelengths The signal is the same as having a metal wall, and the electromagnetic wave can be shielded by the first via hole. Therefore, unnecessary transmission modes can be suppressed by the plurality of first via holes.
また、 上記間隔は 0 μ m以上であればよい。 もっとも、 上記間隔が 5 0 μ m以 上であれば、 誘電体基板の十分な機械的強度が得られる。  Further, the above interval may be 0 μm or more. However, if the distance is 50 μm or more, sufficient mechanical strength of the dielectric substrate can be obtained.
一実施形態の高周波半導体装置の実装構造は、 上記第 2のビアホールは複数あ つて、 上記複数の第 2のビアホールのうちの隣り合うもの同士の間隔は 0 μ ΐη以 上; L g 2Z 4 ( g 2 :上記回路基板中における信号の波長) 以下に設定されてい る。 In one embodiment, the mounting structure of the high-frequency semiconductor device includes a plurality of the second via holes, and an interval between adjacent ones of the plurality of the second via holes is 0 μΐη or more; L g 2 Z 4 that it is set to: (g 2 signal wavelength during the circuit board) or less.
上記実施形態の高周波半導体装置の実装構造によれば、 上記複数の第 2のビア ホーノレ 1 5のうちの隣り合うもの同士の間隔を λ 以下にしているので、 λ g l以上の波長の信号にとっては金属の壁があるのと同じであり、 電磁波を第 2のビアホールで遮蔽することができる。 したがって、 上記複数の第 2のビアホ ールで不要伝送モードを抑えることができる。 また、 上記間隔は 0 μ m以上であればよい。 もっとも、 上記間隔が 5 0 μ m以 上であれば、 誘電体基板の十分な機械的強度が得られる。 According to the mounting structure of the high-frequency semiconductor device of the above embodiment, since the interval between adjacent ones of the plurality of second via Honore 1 5 below lambda, for lambda gl more wavelengths signals It is the same as having a metal wall, and electromagnetic waves can be shielded by a second via hole. Therefore, unnecessary transmission modes can be suppressed by the plurality of second via holes. Further, the above interval may be 0 μm or more. However, if the distance is 50 μm or more, sufficient mechanical strength of the dielectric substrate can be obtained.
一実施形態の高周波半導体装置の実装構造は、 上記誘電体基板と上記第 2の信 号線路との間には、 厚さ 5 /x m以上 2 0 0 / m以下の空気層が介在している。 上記実施形態の高周波半導体装置の実装構造によれば、 上記誘電体基板と第 2 の信号線路との間に、 厚さ 5 μ πι以上 2 0 0 μ πι以下の空気層を設けているので、 入出力のインピーダンス整合を取ることができる。 In one embodiment of the mounting structure of the high-frequency semiconductor device, an air layer having a thickness of not less than 5 / xm and not more than 200 / m is interposed between the dielectric substrate and the second signal line. . According to the mounting structure of the high-frequency semiconductor device of this embodiment, between the dielectric substrate and the second signal line, since there is provided a thickness 5 μ πι more 2 0 0 μ πι following air layer, Input / output impedance matching can be achieved.
一実施形態の高周波半導体装置の実装構造は、 上記接着剤層は、 圧縮部分にの み導電性を有する誘電体を含む。  In one embodiment of the mounting structure of the high-frequency semiconductor device, the adhesive layer includes a dielectric having conductivity only in a compressed portion.
上記実施形態の高周波半導体装置の実装構造によれば、 上記接着剤層は圧縮部 分にのみ導電性を有する誘電体を含むので、 第 1の補助ダランド層と第 2の補助 ダランド層との間の接着剤層を圧縮することにより、 第 1の捕助グランド層に対 して第 2の補助ダランド層のみを電気的に接続することができる。 したがって、 上記第 1, 第 2の補助グランド層の大きさや形状を気にすることなく、 容易に実 装を行うことができる。  According to the mounting structure of the high-frequency semiconductor device of the above embodiment, since the adhesive layer includes a dielectric material having conductivity only in the compressed portion, the adhesive layer includes the first auxiliary duland layer and the second auxiliary durand layer. By compressing this adhesive layer, only the second auxiliary duland layer can be electrically connected to the first auxiliary ground layer. Therefore, the mounting can be easily performed without concern for the size and shape of the first and second auxiliary ground layers.
一実施形態の高周波半導体装置の実装構造は、 上記第 1のビアホールは、 上記 高周波半導体素子に重なるように配置されている。  In one embodiment of the mounting structure of the high-frequency semiconductor device, the first via hole is arranged so as to overlap the high-frequency semiconductor element.
上記実施形態の高周波半導体装置の実装構造によれば、 上記第 1のビアホール を高周波半導体素子に重なるように複数配置されているので、 高周波半導体素子 の熱が第 1のビアホール導電体を介して外部に効率よく放出される。 したがって、 上記高周波半導体素子を良好に動作させることができる。  According to the mounting structure of the high-frequency semiconductor device of the above embodiment, since the first via holes are arranged in a plurality so as to overlap the high-frequency semiconductor element, heat of the high-frequency semiconductor element is externally transmitted through the first via-hole conductor. Is released efficiently. Therefore, the high-frequency semiconductor element can be favorably operated.
また、 上記第 1のビアホールを高周波半導体素子に重なるように複数配置され ているので、 第 1のグランド層がより低ダランドィンダクタンスとなる。  Further, since the plurality of first via holes are arranged so as to overlap the high-frequency semiconductor element, the first ground layer has a lower Durand inductance.
一実施形態の高周波半導体装置の実装構造は、 上記第 2の信号線路は、 入力部 と、 この入力部に対して所定の間隔をあけて設けられた出力部とから成り、 上記第 1, 第 2のビアホールは、 上記入力部と上記出力部との間の領域に重な るように複数配置されている。  In one embodiment, the mounting structure of the high-frequency semiconductor device is such that the second signal line includes an input section and an output section provided at a predetermined interval from the input section. A plurality of the second via holes are arranged so as to overlap a region between the input section and the output section.
上記実施形態の高周波半導体装置の実装構造によれば、 上記第 1 , 第 2のビア ホールを入力部と出力部との間の領域に重なるように複数配置しているので、 第 1 , 第 2のビアホールのそれぞれを所定の間隔で配置することにより、 その領域 の上下に金属の壁があるようにすることができる。 したがって、 入出力間の不要 伝送モードを抑えることができる。 According to the mounting structure of the high-frequency semiconductor device of the above embodiment, since the first and second via holes are arranged in a plurality so as to overlap the region between the input unit and the output unit, By arranging the first and second via holes at predetermined intervals, metal walls can be provided above and below the region. Therefore, unnecessary transmission modes between input and output can be suppressed.
一実施形態の高周波半導体装置の実装構造は、 上記回路基板の裏面にアンテナ が設けられている。  In one embodiment of the mounting structure of the high-frequency semiconductor device, an antenna is provided on the back surface of the circuit board.
上記実施形態の高周波半導体装置の実装構造によれば、 上記回路基板の裏面に アンテナを設けているので、 アンテナ一体化の高周波回路の小型化が可能となる。 また、 本発明の高周波送信装置は、 上記高周波半導体装置の実装構造をフロン トェンド部に用いたことを特徴としている。  According to the mounting structure of the high-frequency semiconductor device of the embodiment, since the antenna is provided on the back surface of the circuit board, the high-frequency circuit integrated with the antenna can be reduced in size. Further, the high-frequency transmission device of the present invention is characterized in that the mounting structure of the high-frequency semiconductor device is used for a front end portion.
上記構成の高周波送信装置によれば、 上記高周波半導体装置の実装構造をフロ ントエンド部に用いているので、 フロントエンド部を低コストで再現性よく製造 することができる。  According to the high-frequency transmission device having the above configuration, since the mounting structure of the high-frequency semiconductor device is used for the front-end portion, the front-end portion can be manufactured at low cost and with good reproducibility.
また、 本発明の高周波受信装置は、 上記高周波半導体装置の実装構造をフロン トェンド部に用いたことを特徴としている。  Further, a high-frequency receiving device according to the present invention is characterized in that the mounting structure of the high-frequency semiconductor device is used for a front end portion.
上記構成の高周波受信装置によれば、 上記高周波半導体装置の実装構造をフロ ントエンド部に用いているので、 フロントエンド部を低コストで再現性よく製造 することができる。 図面の簡単な説明  According to the high-frequency receiving device having the above configuration, since the mounting structure of the high-frequency semiconductor device is used for the front-end portion, the front-end portion can be manufactured at low cost and with good reproducibility. BRIEF DESCRIPTION OF THE FIGURES
図 1は本発明の実施の形態 1の高周波半導体装置の実装構造の概略端面図であ る。  FIG. 1 is a schematic end view of a mounting structure of a high-frequency semiconductor device according to Embodiment 1 of the present invention.
図 2は図 1の 11一 11線矢視概略断面図である。  FIG. 2 is a schematic sectional view taken along line 11-11 of FIG.
図 3は上記実施の形態 1の誘電体基板の概略下面図である。  FIG. 3 is a schematic bottom view of the dielectric substrate according to the first embodiment.
図 4は上記実施の形態 1の外部回路基板の概略上面図である。  FIG. 4 is a schematic top view of the external circuit board according to the first embodiment.
図 5は上記ミリ波半導体装置の誘電体基板の概略横断面図である。  FIG. 5 is a schematic cross-sectional view of the dielectric substrate of the above-described millimeter-wave semiconductor device.
図 6は電磁結合部分の伝送特性 ( S 2 1 ) と反射特性 ( S 1 1 ) とを測^価 した結果を示すグラフである。  FIG. 6 is a graph showing the results of measuring the transmission characteristics (S 21) and the reflection characteristics (S 11) of the electromagnetic coupling portion.
図 7は本発明の実施の形態 2の高周波半導体装置の実装構造の概略端面図であ る。 図 8は本発明の実施の形態 3の高周波半導体装置の実装構造の概略端面図であ る。 FIG. 7 is a schematic end view of the mounting structure of the high-frequency semiconductor device according to the second embodiment of the present invention. FIG. 8 is a schematic end view of the mounting structure of the high-frequency semiconductor device according to the third embodiment of the present invention.
図 9は上記実施の形態 3の誘電体基板の概略下面図である。  FIG. 9 is a schematic bottom view of the dielectric substrate according to the third embodiment.
図 1 0は上記実施の形態 3の外部回路基板の概略上面図である。  FIG. 10 is a schematic top view of the external circuit board according to the third embodiment.
図 1 1は本発明の実施の形態 4の高周波半導体装置の実装構造の概略端面図で ある。  FIG. 11 is a schematic end view of the mounting structure of the high-frequency semiconductor device according to the fourth embodiment of the present invention.
図 1 2は送受信装置の概略構成図である。  FIG. 12 is a schematic configuration diagram of the transmission / reception device.
図 1 3は従来の高周波半導体装置の実装構造の概略端面図である。  FIG. 13 is a schematic end view of a mounting structure of a conventional high-frequency semiconductor device.
図 1 4は他の従来の高周波半導体装置の実装構造の概略端面図である。 発明を実施するための最良の形態  FIG. 14 is a schematic end view of a mounting structure of another conventional high-frequency semiconductor device. BEST MODE FOR CARRYING OUT THE INVENTION
以下、 本発明の高周波半導体装置の実装構造およびそれを用いた高周波送受信 装置を図示の実施の形態により詳細に説明する。  Hereinafter, a mounting structure of a high-frequency semiconductor device of the present invention and a high-frequency transmitting / receiving device using the same will be described in detail with reference to the illustrated embodiments.
(実施の形態 1 )  (Embodiment 1)
図 1に、 本発明の実施の形態 1の高周波半導体装置の実装構造の概略端面図を 示す。  FIG. 1 shows a schematic end view of the mounting structure of the high-frequency semiconductor device according to the first embodiment of the present invention.
上記高周波半導体装置の実装構造では、 高周波半導体装置の一例としてのミリ 波半導体装置 1を回路基板の一例としての外部回路基板2に実装している。 上記ミリ波半導体装置 1は、 外部回路基板 2の表面に裏面が対向する誘電体基 板 3と、 この誘電体基板 3の表面に搭載された高周波半導体素子の一例としての MM I C (モノリシックマイクロ波集積回路) 4とを備えている。 上記誘電体基 板 3の表面には第 1の信号線路 5を設けていて、 この第 1の信号線路 5と MM I C 4とがワイヤ 1 0により電気的に接続されている。 また、 上記誘電体基板 3の 表面には、 MM I C 4を収容するキヤビティ 9を形成している。 そして、 上記 M M I C 4は電波吸収体から成る蓋体 1 1により封止されている。 また、 上記キヤ ビティ 9からは第 1のグランド層 7の一部が露出して MM I C 4の底面と接触し ている。 この第 1のダランド層 7の残りの部分は誘電体基板 3内に埋め込まれて いる。 そして、 上記グランド層 7は、 第 1の信号線路 5と重なる位置にスロット 孔 8を有している。 上記外部回路基板 2の表面には、 第 1のダランド層 7のスロット孔 8を介して 第 1の信号線路 5に対向する第 2の信号線路 1 2を設ける一方、 外部回路基板 2 の裏面には第 2のグランド層 1 3を設けている。 その第 2の信号線路 1 2は、 入 力部 1 2 aと、 この入力部 1 2 aに対して所定の間隔をあけて設けられた出力部 1 2 bとから成っている。 In the mounting structure of the high-frequency semiconductor device, the millimeter-wave semiconductor device 1 as an example of the high-frequency semiconductor device is mounted on the external circuit board 2 as an example of the circuit board. The above-described millimeter-wave semiconductor device 1 includes a dielectric substrate 3 having a back surface facing the front surface of an external circuit board 2, and an MM IC (monolithic microwave) as an example of a high-frequency semiconductor element mounted on the surface of the dielectric substrate 3. Integrated circuit) 4. A first signal line 5 is provided on the surface of the dielectric substrate 3, and the first signal line 5 and the MMIC 4 are electrically connected by wires 10. In addition, a cavity 9 for housing the MM IC 4 is formed on the surface of the dielectric substrate 3. The MMIC 4 is sealed by a lid 11 made of a radio wave absorber. Also, a part of the first ground layer 7 is exposed from the cavity 9 and is in contact with the bottom surface of the MMIC 4. The remaining part of the first duland layer 7 is embedded in the dielectric substrate 3. The ground layer 7 has a slot hole 8 at a position overlapping the first signal line 5. On the front surface of the external circuit board 2, a second signal line 12 facing the first signal line 5 is provided through a slot hole 8 of the first duland layer 7, and on the back surface of the external circuit board 2 Is provided with a second ground layer 13. The second signal line 12 includes an input section 12a and an output section 12b provided at a predetermined interval from the input section 12a.
図 2に、 図 1の II一 II線から見た概略断面図を示す。  FIG. 2 is a schematic sectional view taken along the line II-II in FIG.
上記誘電体基板 3の裏面には第 1の補助グランド層 6を設けている。 また、 上 記誘電体基板 3の裏面側の部分には、 第 1の補助ダランド層 6から第 1のグラン ド層 7に達する第 1のビアホール 1 5を複数形成している。 そして、 各第 1のビ ァホール 1 5内には第 1のビアホール導電体 1 6を埋めている。 上記第 1のビア ホール導電体 1 6により、 第 1のグランド層 7と第 1の補助ダランド層 6とが電 気的に接続されている。  On the back surface of the dielectric substrate 3, a first auxiliary ground layer 6 is provided. In addition, a plurality of first via holes 15 extending from the first auxiliary duland layer 6 to the first ground layer 7 are formed on the back surface side of the dielectric substrate 3. Each first via hole 15 is filled with a first via-hole conductor 16. The first ground layer 7 and the first auxiliary duland layer 6 are electrically connected by the first via-hole conductor 16.
上記外部回路基板 2の表面には、 第 1の補助グランド層 6に対向する第 2の補 助グランド層 1 4を設けている。 この第 2の補助グランド層 1 4と第 1の補助グ ランド層 6とは導電性の接着剤層 1 7で電気的かつ物理的に接続されている。 ま た、 上記外部回路基板 2において、 表面から裏面に達する第 2のビアホール 1 8 を複数形成している。 つまり、 上記複数の第 2のビアホール 1 8が外部回路基板 2を貫通している。 そして、 各第 2のビアホール 1 8内には第2のビアホーノレ導 電体 1 9を埋めている。 上記第 2のビアホール導電体 1 9により、 第 2の補助グ ランド層 1 4と第 2のグランド層 1 3とが電気的に接続されている。 On the surface of the external circuit board 2, a second auxiliary ground layer 14 facing the first auxiliary ground layer 6 is provided. The second auxiliary ground layer 14 and the first auxiliary ground layer 6 are electrically and physically connected by a conductive adhesive layer 17. In the external circuit board 2, a plurality of second via holes 18 extending from the front surface to the rear surface are formed. That is, the plurality of second via holes 18 penetrate the external circuit board 2. Each second via hole 18 is filled with a second viahorne conductor 19. The second via-hole conductor 19 electrically connects the second auxiliary ground layer 14 to the second ground layer 13.
また、 上記第 1の信号線路 5と第 2の信号線路 1 2とは、 第 1のダランド層 7 のスロット孔 8を介して電磁気的に接 するようになっている。 そして、 上記誘 電体基板 3と第 2の信号線路 1 2との間には空気層 2 0のみが介在している。 ま た、 上記外部回路基板 2と誘電体基板 3との間には、 第 1の補助グランド層 6、 第 2の信号線路 1 2、 第 2の補助グランド層 1 4および接着剤層 1 7を設けてい ない領域が存在する。  Further, the first signal line 5 and the second signal line 12 are electromagnetically connected via the slot hole 8 of the first duland layer 7. Then, only the air layer 20 is interposed between the dielectric substrate 3 and the second signal line 12. A first auxiliary ground layer 6, a second signal line 12, a second auxiliary ground layer 14, and an adhesive layer 17 are provided between the external circuit board 2 and the dielectric substrate 3. There is an area that is not provided.
また、 図 3に示すように、 上記ミリ波半導体装置 1の底面 (誘電体基板 3の裏 面) には、 第 1の補助グランド層 6の他に電源端子 2 1も設けている。 そして、 上記複数の第 1のビアホール 1 5のうち最も近い距離で隣り合うもの同士の間隔 S iは、 0 / m以上; I S i 4, ( λ g l:誘電体基板 3中における信号の周波数) 以 下に設定されている。 なお、 Wは例えば 8 0 0 /z mに設定している。 Further, as shown in FIG. 3, on the bottom surface of the millimeter-wave semiconductor device 1 (the back surface of the dielectric substrate 3), a power supply terminal 21 is provided in addition to the first auxiliary ground layer 6. And a distance between adjacent ones of the plurality of first via holes 15 at the closest distance. S i is set to 0 / m or more; IS i 4, (λ gl : frequency of a signal in the dielectric substrate 3) is set to the following. Note that W is set to, for example, 800 / zm.
また、 図 4に示すように、 上記外部回路基板 2の表面には、 第 2の信号線路 1 2, 第 2の補助グランド層 1 4の他に、 マイクロストリップ線路より成る電源用 線路 2 2も設けている。 また、 上記第 2の信号線路 1 2および第 2の補助ダラン ド層 1 4もマイクロストリップ線路より成っていて、 第 2の信号線路 1 2の表面 積よりも第 2の補助グランド層 1 4の表面積のほうが広くなつている。 そして、 上記複数の第 2のビアホール 1 8のうち最も近い距離で隣り合うもの同士の間隔 S 2は、 Ο μ πι以上; g 2Z4 ( λ g 2:外部回路基板 2中における信号の周波数) 以下に設定されている。 なお、 W2は例えば 8 0 0 μ πιに設定している。 As shown in FIG. 4, on the surface of the external circuit board 2, in addition to the second signal line 12 and the second auxiliary ground layer 14, a power supply line 22 composed of a microstrip line is also provided. Provided. Further, the second signal line 12 and the second auxiliary durand layer 14 are also formed of microstrip lines, and the surface area of the second signal line 12 is smaller than that of the second auxiliary ground layer 14. The surface area is larger. The interval S 2 between the plurality of second via holes 18 adjacent to each other at the closest distance is 、 μπι or more; g 2 Z 4 (λ g 2 : frequency of a signal in the external circuit board 2) It is set as follows. Incidentally, W 2 is set to, for example, 8 0 0 μ πι.
また、 上記第 1の補助グランド層 6が第 2の補助グランド層 1 4に、 電源端子 2 1が電源用泉路 2 2にそれぞれ半田等の接着材により接続されることにより、 ミリ波半導体装置 1は外部回路基板 2上に実装されている。  Also, the first auxiliary ground layer 6 is connected to the second auxiliary ground layer 14 and the power supply terminal 21 is connected to the power supply fountain path 22 by an adhesive such as solder. 1 is mounted on the external circuit board 2.
また、 図 5に示すように、 上記誘電体基板 3の表面には、 第 1の信号線路 5の 他に MM I C 4の電源用線路 2 3も設けている。 この電源用線路 2 3と、 図 3に 示す電源端子 2 1とは第 3のビアホール 2 4で接続されている。 この第 3のビア ホール 2 4内を第 3のビアホール導電体 2 5で埋めていることにより、 電源用線 路 2 3と電源端子 2 1とが電気的に接続されている。  Further, as shown in FIG. 5, on the surface of the dielectric substrate 3, in addition to the first signal line 5, a power supply line 23 of the MMIC 4 is also provided. The power supply line 23 and the power supply terminal 21 shown in FIG. 3 are connected by a third via hole 24. By filling the inside of the third via hole 24 with the third via hole conductor 25, the power supply line 23 and the power supply terminal 21 are electrically connected.
上記構成の実装構造によれば、 ミリ波半導体装置 1内部のダランドである第 1 のグランド層 7は、 複数のビアホール導電体 1 6等を介して外部回路基板 2の裏 面の第 2のグランド層 1 3と電気的に接続されているので、 高周波的に.も良好な グランド (低グランドインダクタンス) となり、 第 1の信号線路 5から第 2の信 号線路 1 2へ信号が伝送される際にダランド変換が良好に行われる。  According to the mounting structure having the above-described configuration, the first ground layer 7, which is a land in the millimeter-wave semiconductor device 1, is connected to the second ground layer on the back surface of the external circuit board 2 via a plurality of via-hole conductors 16. Since it is electrically connected to the layer 13, it is also a good ground (low ground inductance) at high frequencies, and when a signal is transmitted from the first signal line 5 to the second signal line 12. The Durand transform is performed favorably.
また、 上記外部回路基板 2とミリ波半導体装置 1の第 1のグランド層 7とを電 気的 -物理的に接続し、 信号線路は物理的な接続不要で、 第 1の信号線路 5は直 接外部回路基板 2のマイクロストリップ線路から成る第 2の信号線路 1 2に電磁 結合されるため、 外部回路基板 2から低損失でミリ波信号を取り出すことが可能 となる。  Also, the external circuit board 2 is electrically and physically connected to the first ground layer 7 of the millimeter-wave semiconductor device 1, the signal line does not need to be physically connected, and the first signal line 5 is directly connected. Since it is electromagnetically coupled to the second signal line 12 composed of the microstrip line of the external circuit board 2, it is possible to extract a millimeter wave signal from the external circuit board 2 with low loss.
また、 上記ミリ波半導体装置 1はキヤビティ構造であるので、 MM I C 4のグ ランド面とミリ波半導体装置 1の第 1グランド層 6とがー致し、 MM I C 4力 ら みて低グランドィンダクタンスを実現できる。 Also, since the above-mentioned millimeter-wave semiconductor device 1 has a cavity structure, the MM IC 4 The land surface and the first ground layer 6 of the millimeter-wave semiconductor device 1 are aligned, and low ground inductance can be realized in view of the MM IC 4.
また、 上記蓋体 1 1が電波吸収体で形成されているため、 不要発振が起こらず、 安定した高周波特性を得ることができる。  Further, since the lid 11 is formed of a radio wave absorber, unnecessary oscillation does not occur, and stable high-frequency characteristics can be obtained.
また、 図 3及ぴ図 4に示すように、 上記複数の第 1, 第 2のビアホール 1 5, Also, as shown in FIGS. 3 and 4, the first and second via holes 15
1 8を覆うように、 第 1 , 第 2の補助グランド層 6, 1 4を表面積の大きなパタ ーンにしているので、 第 1の補助グランド層 6と第 2の補助グランド層 1 4との 接続において細力 ^、位置合わせを必要としない。 したがって、 上記第 1の補助グ ランド層 6と第 2の補助グランド層 1 4とを容易に接続できる。 Since the first and second auxiliary ground layers 6 and 14 have a large surface area so as to cover the first auxiliary ground layer 18, the first auxiliary ground layer 6 and the second auxiliary ground layer 14 Fine connection ^, no alignment required. Therefore, the first auxiliary ground layer 6 and the second auxiliary ground layer 14 can be easily connected.
また、 上記第 1の補助ダランド層 6と第 2の補助ダランド層 1 4とを接着剤層 Also, the first auxiliary duland layer 6 and the second auxiliary duland layer 14 are bonded to each other with an adhesive layer.
1 7で物理的に接続するため、 接続強度を確保できる。 Since the connection is made physically at 17, the connection strength can be secured.
さらには、 上記第 1の補助ダランド層 6と第 2の補助ダランド層 1 4との接続 は、 表面積の大きなパターン同士の接続なので、 細い信号線路同士を接続する際 に生じる接着材層の形状等による特性劣化がない。 その結果、 再現性'量産性に 優れたミリ波実装構造を実現することができる。  Further, since the connection between the first auxiliary duland layer 6 and the second auxiliary duland layer 14 is a connection between patterns having a large surface area, the shape of an adhesive layer generated when connecting thin signal lines is formed. No characteristic degradation due to As a result, a millimeter-wave mounting structure with excellent reproducibility and mass productivity can be realized.
また、 上記複数の第 1のビアホール 1 5のうち最も近い距離で隣り合うもの同 士の間隔 S iを; g l 4以下にしているので、 λ g l以上の波長の信号にとっては 金属の壁があるのと同じであり、 第 1のビアホール 1 5によって電磁波を遮蔽す ることができる。 したがって、 上記複数の第 1のビアホール 1 5で不要伝送モー ドを抑えることができる。 その上、 上記複数の第 2のビアホール 1 8のうち最も 近い距離で隣り合うもの同士の間隔 S2を; I g2Z4以下にしているので、 複数の 第 2のビアホール 1 8によっても電磁波を遮蔽することができて、 不要伝送モー ドをより抑えることができる。 In addition, since the distance S i between adjacent ones of the plurality of first via holes 15 closest to each other at the closest distance is less than gl 4, there is a metal wall for a signal having a wavelength of λ gl or more. The electromagnetic wave can be shielded by the first via hole 15. Therefore, the unnecessary transmission mode can be suppressed by the plurality of first via holes 15. In addition, since the interval S 2 between the adjacent second via holes 18 at the closest distance among the plurality of second via holes 18 is set to Ig 2 Z4 or less, electromagnetic waves can also be transmitted through the plurality of second via holes 18. It can be shielded and the unnecessary transmission mode can be further suppressed.
また、 上記複数の第 1のビアホール 1 5のうち最も近い距離で隣り合うもの同 士の間隔 S1を; g l 4以下にし、 上記複数の第 2のビアホール 1 8のうち最も 近い距離で隣り合うもの同士の間隔 S2を g2Z4以下にしているので、 上記第 1のグランド層 7 ■上記第 2のダランド層 1 3 ·上記複数の第 1のビアホール 1 5 '上記複数の第2のビアホール 1 8で擬似導波管が形成される。 したがって、 上記第 1のビアホール 1 5の間隔 および上記第 2のビアホール 1 8の間隔 W2 と、 λ g / 2 ( λ gは上記誘電体基板 3を形成する誘電体 ·上記空気層 2 0 ■上 記外部回路基板 2を形成する誘電体とで構成される上記擬似導波管内部の実効誘 電率と同じ誘電率を持つ材料内での信号の波長) とが等しくなる周波数はカツト オフ周波数となり、 不要な導波管モードも抑えることが可能となる。 つまり、 力 ットオフ周波数以下の信号は擬似導波管内部にはマイクロストリツプの伝搬モー ド以外で存在することができないため、 不要伝送モードを抑制することができる。 また、 上記第 1のビアホール 1 5の間隔 S Lを 5 0 μ m以上に設定すれば、 誘 電体基板 3の機械的強度の低下を阻止できる。 Further, the spacing S 1 of those same workers adjacent the closest distance among the plurality of the first via hole 1 5; gl 4 and below, adjacent the closest distance among the plurality of second via hole 1 8 Since the distance S 2 between the two is less than or equal to g 2 Z4, the first ground layer 7 ■ the second duland layer 1 3 · the plurality of first via holes 1 5 'the plurality of second via holes At 18, a pseudo waveguide is formed. Therefore, the distance between the first via holes 15 and the distance between the second via holes 18 W 2 And λ g / 2 (where λ g is the dielectric forming the dielectric substrate 3, the air layer 20) and the dielectric forming the external circuit board 2. The frequency at which the effective dielectric constant is equal to the wavelength of a signal in a material having the same dielectric constant) is the cut-off frequency, and unnecessary waveguide modes can be suppressed. In other words, signals below the power-off frequency cannot exist inside the pseudo waveguide except in the propagation mode of the microstrip, so that unnecessary transmission modes can be suppressed. Further, if the interval SL between the first via holes 15 is set to 50 μm or more, a decrease in the mechanical strength of the dielectric substrate 3 can be prevented.
また、 上記第 2のビアホール 1 8の間隔 S 2を 5 0 μ πι以上に設定すれば、 外 部回路基板 2の機械的強度の低下を阻止できる。 Further, by setting the distance S 2 of the second via hole 1 8 above 5 0 μ πι, can prevent reduction in the mechanical strength of the external circuit board 2.
また、 上記ミリ波半導体装置 1を外部回路基板 2に例えば半田で実装する場合、 半田ペーストの塗布量を制御することにより、 空気層 2 0の厚さを制御すること が可能となる。  When the millimeter-wave semiconductor device 1 is mounted on the external circuit board 2 with, for example, solder, the thickness of the air layer 20 can be controlled by controlling the amount of solder paste applied.
図 6に、 上記空気層 2 0の厚さ hを変えて、 電磁結合部分の伝送特性 ( S 2 1 ) と反射特性 ( S 1 1 ) とを測定評価した結果の一例を示す。 なお、 上記測定 評価において、 誘電体基板 3は誘電率 8 . 7のアルミナセラミック、 外部回路基 板 2は誘電率 5 . 7のガラスセラミック、 スロット孔 8の寸法は 9 0 0 /z m X 2 0 0 m、 第 1の信号線路 5は幅 1 6 0 /i m、 第 1の信号線路 5の一端からスロ ット孔 8の中心線までの距離 (図 1の L 1で示す距離) が1 0 0 111、 第 2の信 号線路 1 2は幅 1 8 0 μ m、 第 2の信号線路 1 2の一端からスロット孔 8の中心 線までの距離 (図 1の L 2で示す距離) が 5 0 0 μ m、 誘電体基板 3の厚さは 3 0 0 μ m、 第 1のグランド層 7は第 1の信号線路 5と第 1の補助ダランド層 6と の間のちょうど中間に位置し、 外部回路基板 2の厚さは 1 5 0 /z mである。 また、 上記測定評価では、 接着剤層 1 7として半田を用いている。  FIG. 6 shows an example of the results of measurement and evaluation of the transmission characteristics (S 21) and the reflection characteristics (S 11) of the electromagnetic coupling portion while changing the thickness h of the air layer 20. In the above measurement and evaluation, the dielectric substrate 3 was an alumina ceramic having a dielectric constant of 8.7, the external circuit board 2 was a glass ceramic having a dielectric constant of 5.7, and the dimensions of the slot hole 8 were 900 / zm X 20 0 m, the first signal line 5 has a width of 160 / im, and the distance from one end of the first signal line 5 to the center line of the slot 8 (the distance indicated by L1 in FIG. 1) is 10 0 111, the second signal line 12 has a width of 180 μm, and the distance from one end of the second signal line 12 to the center line of the slot hole 8 (the distance indicated by L 2 in FIG. 1) is 5 0 μm, the thickness of the dielectric substrate 3 is 300 μm, the first ground layer 7 is located just halfway between the first signal line 5 and the first auxiliary duland layer 6, The thickness of the external circuit board 2 is 150 / zm. In the above measurement and evaluation, solder was used as the adhesive layer 17.
図 6から判るように、 上記空気層 2 0の厚さ hを 5 0 μ πιとした場合に最もリ ターンロスが大きく、 入出力のインピーダンス整合がよくとれている。 このよう に、 上記空気層 2 0の厚さ hを調節することにより、 入出力のインピーダンス整 合を取ることが可能となる。  As can be seen from FIG. 6, when the thickness h of the air layer 20 is set to 50 μππ, the return loss is the largest, and the input / output impedance matching is good. As described above, by adjusting the thickness h of the air layer 20, it is possible to match the input / output impedance.
上記空気層 2 0の厚さは、 入出力のインピーダンス整合を取るために、 5 μ πι 以上 2 0 0 i m以下に設定するのが望ましい。 The thickness of the air layer 20 is 5 μπι It is desirable to set it to 200 im or less.
また、 上記接着材層の厚さは 5 /z m以上 2 0 0 ^ ni以下に設定するのが望まし い。  Further, it is desirable that the thickness of the adhesive layer be set to 5 / zm or more and 200 ^ ni or less.
また、 図 1に示すように、 上記誘電体基板 3に蓋体 1 1を載せるための側壁を 設ける場合は、 スロッ ト孔 8を介した電磁結合を妨げな 、ように、 スロット孔 8 からの距離 Dを L 4以上とするのが望ましい。  In addition, as shown in FIG. 1, when the dielectric substrate 3 is provided with a side wall on which the lid 11 is placed, the electromagnetic coupling through the slot hole 8 is prevented so as not to obstruct the electromagnetic coupling through the slot hole 8. It is desirable that the distance D be L4 or more.
上記実施の形態 1では、 第 1の信号線路 5と MM I C 4とをワイヤ 1 0により 電気的に接続していたが、 例えばリポンや T A B (Tape Automated Bonding) 等 により電気的に接続してもよい。  In the first embodiment, the first signal line 5 and the MM IC 4 are electrically connected to each other by the wire 10. However, the first signal line 5 and the MM IC 4 may be electrically connected by, for example, a repone or TAB (Tape Automated Bonding). Good.
(実施の形態 2 )  (Embodiment 2)
図 7に、 本発明の実施の形態 2の高周波半導体装置の実装構造の概略端面図を 示す。 なお、 図 7において、 図 1に示した構成部と同一構成部は、 図 1における 構成部と同一参照番号を付して説明を省略する。  FIG. 7 shows a schematic end view of the mounting structure of the high-frequency semiconductor device according to the second embodiment of the present invention. In FIG. 7, the same components as those shown in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and description thereof is omitted.
上記高周波半導体装置の実装構造では、 ミリ波半導体装置 1を外部回路基板 2 に実装するための接着剤層の一例として、 垂直方向の圧縮部分にのみ導電性を有 する A C F (Anisotropic Conductive Film:異方†生導電フイノレム) 等の誘電体 を含む接着材層 1 1 7を用いている。 ここで、 誘電体基板 3と第 2の信号線路 1 2との間には、 接着剤層 1 1 7のみが介在している。  In the mounting structure of the high-frequency semiconductor device described above, an example of an adhesive layer for mounting the millimeter-wave semiconductor device 1 on the external circuit board 2 is an ACF (Anisotropic Conductive Film: ACF) having conductivity only in a vertically compressed portion. An adhesive layer 117 containing a dielectric such as raw conductive finolem) is used. Here, only the adhesive layer 117 is interposed between the dielectric substrate 3 and the second signal line 12.
例えば、 A C Fを含む接着剤層 1 1 7を用いた場合、 ミリ波半導体装置 1の底 面と同じ程度の大きさのフィルムを貼り付けて実装すればよく、 第 1の補助ダラ ンド層 6及び第 2の補助グランド層 1 4の大きさや形状を気にする必要が無く、 容易に実装することができる。  For example, when an adhesive layer 117 containing ACF is used, a film having a size similar to that of the bottom surface of the millimeter-wave semiconductor device 1 may be attached and mounted, and the first auxiliary dry layer 6 and There is no need to worry about the size and shape of the second auxiliary ground layer 14, and the second auxiliary ground layer 14 can be easily mounted.
(実施の形態 3 )  (Embodiment 3)
図 8に、 本発明の実施の形態 2の高周波半導体装置の実装構造の概略端面図を 示す。 なお、 図 7において、 図 1に示した構成部と同一構成部は、 図 1における 構成部と同一参照番号を付して説明を省略する。  FIG. 8 shows a schematic end view of the mounting structure of the high-frequency semiconductor device according to the second embodiment of the present invention. In FIG. 7, the same components as those shown in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and description thereof is omitted.
上記高周波半導体装置の実装構造では、 入力部 1 2 aと出力部 1 2 bとの間に、 第 2の捕助グランド層 2 1 4の一部が介在している。 この第 2の補助グランド層 2 1 4と対向するように、 第 1の補助グランド層 2 0 6を誘電体基板 2 0 3の裏 面に設けている。 上記第 1の補助ダランド層 2 0 6と第 2の補助ダランド層 2 1 4とは、 導電性の接着剤層 2 1 7で電気的かつ物理的に接続されている。 また、 上記第 2の補助グランド層 2 1 4において入力部 1 2 aと出力部 1 2 bとの間に 介在する一部は、 第 2のビアホール 2 1 8内の第 2のビアホール導電体 2 1 9で 第 2のグランド層 1 3に電気的に接続されている。 その一部に対向する第 1の補 助グランド層 2 0 6の一部は、 第 1のビアホーノレ 2 1 5内の第 1のビアホーノレ導 電体 2 1 6で第 1のダランド層 7に電気的に接続されている。 In the mounting structure of the high-frequency semiconductor device, a part of the second auxiliary ground layer 214 is interposed between the input section 12a and the output section 12b. The first auxiliary ground layer 206 is placed on the back of the dielectric substrate 203 so as to face the second auxiliary ground layer 214. It is provided on the surface. The first auxiliary duland layer 206 and the second auxiliary duland layer 214 are electrically and physically connected by a conductive adhesive layer 217. In the second auxiliary ground layer 2 14, a part interposed between the input section 12 a and the output section 12 b is a second via-hole conductor 2 in the second via-hole 2 18. At 19, it is electrically connected to the second ground layer 13. A part of the first auxiliary ground layer 206 facing the part is electrically connected to the first duland layer 7 by the first viahorn conductor 2 16 in the first viahorn 21. It is connected to the.
上記第 1の補助グランド層 2 0 6は、 図 9に示すようなパターンを有している。 つまり、 上記第 1の補助グランド層 2 0 6は、 誘電体基板 2 0 3の裏面の図中上 側に設けられた一端部 2 0 6 aと、 誘電体基板 2 0 3の裏面の図中下側に設けら れた他端部 2 0 6 bと、 その一端部 2 0 6 aと他端部 2 0 6 bとを連結する連結 部 2 0 6 cとから成っている。 上記一端部 2 0 6 a、 他端部 2 0 6 bおよび連結 部 2 0 6 cは、 それぞれ、 O /x m以上; g l/4 ( λ g :誘電体基板 2 0 3中に おける信号の周波数) 以下の間隔で配置された第 1のビアホール 2 1 5と接続し ている。 The first auxiliary ground layer 206 has a pattern as shown in FIG. In other words, the first auxiliary ground layer 206 is provided with one end portion 206 a provided on the upper surface of the back surface of the dielectric substrate 203 in the drawing, and the lower surface of the dielectric substrate 203 in the drawing. It comprises a lower end portion 206 b provided on the lower side, and a connecting portion 206 c connecting the one end portion 206 a and the other end portion 206 b. The above-mentioned one end 206 a, the other end 206 b and the connecting part 206 c are respectively O / xm or more; gl / 4 (λg: frequency of a signal in the dielectric substrate 203) ) Connected to the first via holes 215 arranged at the following intervals.
上記第2の補助グランド層2 1 4は、 図 1 0に示すようなパターンを有してい る。 つまり、 上記第 2の補助グランド層 2 1 4は、 回路基板の一例としての外部 回路基板 2 0 2の裏面の図中上側に設けられた一端部 2 1 4 aと、 外部回路基板 2 0 2の裏面の図中下側に設けられた他端部 2 1 4 bと、 その一端部 2 1 4 aと 他端部 2 1 4 bとを連結する連結部 2 1 4 cとから成っている。 この連結部 2 1 4 cが入力部 1 2 aと出力部 1 2 bとの間に位置している。 そして、 上記一端部 2 1 4 a , 他端部 2 1 4 bおよび連結部 2 1 4 cは、 それぞれは、 0 μ m以上; L g 2/ 4 ( λ g 2:外部回路基板 2 0 2中における信号の周波数) 以下の間隔で配 置された第 2のビアホール 2 1 8と接続している。 It said second auxiliary ground layer 2 1 4 that has a pattern as shown in FIG. 1 0. In other words, the second auxiliary ground layer 214 is provided with an end portion 214a provided on the upper surface of the back surface of the external circuit board 202 as an example of a circuit board, and an external circuit board 202. The other end 2 14 b provided on the lower side in the figure on the back side of the figure and a connecting portion 2 14 c connecting the one end 2 14 a and the other end 2 14 b . The connecting portion 2 14 c is located between the input portion 12 a and the output portion 12 b. Then, the one end portion 2 1 4 a, the other end portion 2 1 4 b and the connecting portion 2 1 4 c, each, 0 mu m or more; L g 2/4 (λ g 2: external circuit board 2 0 2 (The frequency of the signal inside) The second via holes 218 arranged at the following intervals are connected.
上記構成の実装構造によれば、 入力部 1 2 aと出力部 1 2 bとの間の領域の上 下において第 1, 第 2のビアホール導電体 2 1 6 , 2 1 9が存在するので、 その 領域に金属の壁があるのと同じ状態になり、 入出力間で不要伝送モードが抑えら れ、 純粋な信号の伝送が可能となる。  According to the mounting structure of the above configuration, since the first and second via-hole conductors 2 16 and 2 19 exist above and below the region between the input section 12 a and the output section 12 b, This is the same state as when there is a metal wall in that area, and unnecessary transmission modes are suppressed between input and output, enabling pure signal transmission.
また、 上記 MM I C 4が接触する第 1のグランド層 7の部分にも第 1のビアホ ール 2 1 5が接続しているので、 第 1のビアホール 2 1 5内の第 1のビアホール 導電体 2 1 6を介して MM I C 4の熱が外部へ拡散し易くなる。 その結果、 上記 MM I C 4を良好に動作させることができる。 In addition, the first via hole is also provided in the portion of the first ground layer 7 where the MM IC 4 contacts. Since the first and second holes are connected, the heat of the MM IC 4 is easily diffused to the outside via the first via-hole conductor 216 in the first via-hole 215. As a result, the MM IC 4 can operate well.
上記実施の形態 3では、 第 1の捕助グランド層 2 0 6において、 一端部 2 0 6 a, 他端部 2 0 6 bと連結部 2 0 6 cとは連結されていたが、 一端部 2 0 6 a , 他端部 2 0 6 bと連結部 2 0 6との間に所定の隙間があってもよい。 すなわち、 本発明の第 1の補助グランド層は、 所定の間隔をあけて形成された異なる複数の パターンから成ってもよい。  In the third embodiment, one end portion 206 a, the other end portion 206 b and the connecting portion 206 c are connected to each other in the first auxiliary ground layer 206. There may be a predetermined gap between 206 a and the other end 206 b and the connecting portion 206. That is, the first auxiliary ground layer of the present invention may be composed of a plurality of different patterns formed at predetermined intervals.
また、 上記第 2の補助ダランド層 2 1 4において、 一端部 2 1 4 a, 他端部 2 1 4 bと連結部 2 1 4 cとは連結されていたが、 一端部 2 1 4 a , 他端部 2 1 4 bと連結部 2 1 4との間に所定の隙間があってもよい。 すなわち、 本発明の第 2 の捕助グランド層は、 所定の間隔をあけて形成された異なる複数のパターンから 成ってもよい。  Also, in the second auxiliary duland layer 2 14, one end 2 14 a, the other end 2 14 b and the connecting portion 2 14 c are connected, but one end 2 14 a, There may be a predetermined gap between the other end portion 214b and the connecting portion 214. That is, the second auxiliary ground layer of the present invention may be formed of a plurality of different patterns formed at predetermined intervals.
(実施の形態 4 )  (Embodiment 4)
図 1 1に、 本発明の実施の形態 4の高周波半導体装置の実装構造の概略端面図 を示す。 なお、 図 1 1において、 図 1に示した構成部と同一構成部は、 図 1にお ける構成部と同一参照番号を付して説明を省略する。  FIG. 11 shows a schematic end view of the mounting structure of the high-frequency semiconductor device according to the fourth embodiment of the present invention. In FIG. 11, the same components as those shown in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and description thereof is omitted.
上記高周波半導体装置の実装構造では、 ミリ波半導体装置 1を回路基板の一例 としての外部回路基板 3 0 2に実装している。 この外部回路基板 3 0 2の裏面に は、 アンテナの一例としてのマイクロストリップパッチアンテナ 3 2 6と、 この マイクロストリップパッチアンテナ 3 2 6に接続された給電線路 3 2 7とを設け ている。 一方、 上記外部回路基板 3 0 2の表面には、 入力部と出力部とから成る 第 2の信号線路 3 1 2を設けている。 また、 上記外部回路基板 3 0 2内には、 ス ロット孔 3 2 8を有する第 2のグランド層 3 1 3が埋め込まれている。  In the mounting structure of the high-frequency semiconductor device, the millimeter-wave semiconductor device 1 is mounted on an external circuit board 302 as an example of a circuit board. On the back surface of the external circuit board 302, a microstrip patch antenna 326 as an example of an antenna and a feed line 327 connected to the microstrip patch antenna 326 are provided. On the other hand, on the surface of the external circuit board 302, a second signal line 312 including an input section and an output section is provided. In addition, a second ground layer 313 having a slot hole 328 is embedded in the external circuit board 302.
上記実装構造によれば、 上記第 2の信号線路 3 1 2の入力部, 出力部のうちの According to the mounting structure, of the input portion and the output portion of the second signal line 312,
—方が、 第 2のグランド層 3 1 3のスロット孔 3 2 8を介して給電線路 3 2 7と 電磁結合する。 これにより、 上記マイクロストリップパッチアンテナ 3 2 6に給 電することができる。 — Is electromagnetically coupled to the feed line 3 27 through the slot hole 3 28 of the second ground layer 3 13. Thereby, power can be supplied to the microstrip patch antenna 32.
また、 上記マイクロストリップパッチアンテナ 3 2 6が外部回路基板 3 0 2の 裏面にあるので、 ァンテナ一体化の高周波回路の小型化が可能となる。 Also, the microstrip patch antenna 32 6 is connected to the external circuit board 302 Since it is on the back side, it is possible to reduce the size of the high-frequency circuit integrated with the antenna.
また、 本発明の高周波半導体装置の実装構造を用いているので、 信号損失が少 なく、 再現性 ·量産性に優れる。  Further, since the mounting structure of the high-frequency semiconductor device of the present invention is used, signal loss is small, and reproducibility and mass productivity are excellent.
(実施の形態 5 )  (Embodiment 5)
図 1 2に、 本発明の高周波半導体装置の実装構造を用いた送受信装置の概略構 成図を示す。  FIG. 12 shows a schematic configuration diagram of a transmission / reception device using the mounting structure of the high-frequency semiconductor device of the present invention.
上記送受信装置は、 高周波送信装置の一例としての送信装置 6 0と、 高周波受 信装置の一例としての受信装置 7 0とを備えている。  The transmission / reception device includes a transmission device 60 as an example of a high-frequency transmission device, and a reception device 70 as an example of a high-frequency reception device.
まず、 上記送信装置 6 0から説明する。 上記送信装置 6 0において、 入力端子 6 1に入力されたデータ信号は、 変調器 6 2で変調された後、 中間周波数信号と してフロントエンド部 8 0に送出され、 まずミキサ 6 3に入力される。 このミキ サ 6 3には、 局部発振器 6 9が棻生する局部発振信号も入力される。 この局部 発振器 6 9は、 P L L (Phase Locked Loop) 発振器 6 7と周波数遁倍器 6 8と を備えている。 上記 P L L発振器 6 7が発振する信号は、 周波数通倍器 6 8によ つて周波数が遁倍された後、 局部宪振信号としてミキサ 6 3に入力される。 上記 ミキサ 6 3では局部発振信号と中間周波数信号とを混合することにより R F (無 線周波) 信号を作成して次段の B P F (バンドパスフィルタ) 6 4に出力する。 その R F信号は、 B P F 6 4によって不要成分が除去され且つ増幅器 6 5により 電力増幅されたのちアンテナ 6 6を介して送信される。  First, the transmission device 60 will be described. In the transmitting device 60, the data signal input to the input terminal 61 is modulated by the modulator 62, and then transmitted to the front end unit 80 as an intermediate frequency signal, and is first input to the mixer 63. Is done. A local oscillation signal generated by the local oscillator 69 is also input to the mixer 63. The local oscillator 69 includes a PLL (Phase Locked Loop) oscillator 67 and a frequency multiplier 68. The signal oscillated by the PLL oscillator 67 is frequency-doubled by the frequency doubler 68 and then input to the mixer 63 as a local oscillation signal. The mixer 63 creates an RF (radio frequency) signal by mixing the local oscillation signal and the intermediate frequency signal, and outputs the RF (radio frequency) signal to a BPF (bandpass filter) 64 in the next stage. The RF signal is transmitted through the antenna 66 after the unnecessary components are removed by the BP 64 and the power is amplified by the amplifier 65.
次に、 上記受信装置 7 0について説明する。 上記受信装置 7 0において、 フロ ントエンド部 9 0のアンテナ 7 6から入力された受信信号は、 増幅器 7 5によつ て増幅された後、 B P F 7 4によって不要成分が除去された所望波信号のみとな つてミキサ 7 3に入力される。 また、 上記ミキサ 7 3には局部発振器 7 9が発生 する局部発振信号も入力される。 この局部発振器 7 9は、 ?!^ 発振器7 7と周 波数通倍器 7 8とを備えている。 上記 P L L発振器 7 7が発振する信号は、 周波 数通倍器 7 8によつて周波数が通倍された後、 局部発振信号としてミキサ 7 3に 入力される。 上記ミキサ 7 3では局部発振信号と所望波信号とを混合することに より中間周波数信号を作成して復調器 7 2へ入力する。 その中間周波数信号は、 復調器 7 2で復調されてデータ信号に戻されて出力端子 7 1から出力される。 上記フロントエンド部 8 0 , 9 0には、 本発明の一例としてのミリ波半導体装 置の実装構造を用いており、少なくとも 1つの MM I Cをミリ波半導体装置に搭 載し、 裏面にマイクロストリップパッチアンテナを有した外部回路基板にミリ波 半導体装置を実装して成る。 Next, the receiving device 70 will be described. In the receiving device 70, the received signal input from the antenna 76 of the front end unit 90 is amplified only by the amplifier 75, and then only the desired wave signal from which unnecessary components have been removed by the BPF 74. Is input to the mixer 73. Further, a local oscillation signal generated by a local oscillator 79 is also input to the mixer 73. This local oscillator 79? ! ^ An oscillator 77 and a frequency multiplier 78 are provided. The frequency of the signal oscillated by the PLL oscillator 77 is multiplied by a frequency multiplier 78 and then input to the mixer 73 as a local oscillation signal. The mixer 73 creates an intermediate frequency signal by mixing the local oscillation signal and the desired wave signal, and inputs the intermediate frequency signal to the demodulator 72. The intermediate frequency signal is demodulated by the demodulator 72, converted back to a data signal, and output from the output terminal 71. The front end sections 80 and 90 use a mounting structure of a millimeter-wave semiconductor device as an example of the present invention. At least one MM IC is mounted on the millimeter-wave semiconductor device, and a microstrip is provided on the back surface. A millimeter-wave semiconductor device is mounted on an external circuit board having a patch antenna.
上記フロントエンド部 8 0 , 9 0は、 細い信号線路同士を接続する必要が無く、 細かい位置合わせを必要としない本発明のミリ波半導体装置の実装構造を用いて いるので、 低コストで再現性に優れている。  The front end sections 80 and 90 use the mounting structure of the millimeter-wave semiconductor device of the present invention, which does not need to connect thin signal lines and does not require fine positioning, so that the reproducibility is low and the cost is low. Is excellent.
本発明は上記実施の形態 1〜 5に限定される訳ではなく、 マイク口波を取り扱 うマイク口波半導体装置の実装構造にも用いることができる。  The present invention is not limited to Embodiments 1 to 5, but can also be used for a mounting structure of a microphone mouth wave semiconductor device that handles a microphone mouth wave.
また、 本宪明の第 1のグランド層は、 全部が誘電体基板内に埋め込まれてもよ い。  Further, the entire first ground layer of the present invention may be embedded in the dielectric substrate.

Claims

請 求 の 範 囲 The scope of the claims
1. 誘電体基板 (3, 203) と上記誘電体基板 (3, 203) の表面に搭載 された高周波半導体素子 (4) とを有する高周波半導体装置 (1) と、 回路基板 (2, 202, 302) とを備え、 上記誘電体基板 ( 3, 203) の裏面を上記 回路基板 (2, 202, 302) の表面に対向させて、 上記高周波半導体装置1. A high-frequency semiconductor device (1) having a dielectric substrate (3, 203) and a high-frequency semiconductor element (4) mounted on the surface of the dielectric substrate (3, 203); 302) with the back surface of the dielectric substrate (3, 203) facing the surface of the circuit board (2, 202, 302).
(1) を上記回路基板 (2, 202, 302) に実装した高周波半導体装置の実 装構造において、 In the mounting structure of the high-frequency semiconductor device in which (1) is mounted on the circuit board (2, 202, 302),
上記誘電体基板 (3, 203) の表面に設けられると共に、 上記高周波半導体 素子 (4) に電気的に接続された第 1の信号線路 (5) と、  A first signal line (5) provided on the surface of the dielectric substrate (3, 203) and electrically connected to the high-frequency semiconductor element (4);
上記誘電体基板 (3, 203) 内に少なくとも一部が埋め込まれ、 上記第 1の 信号線路 (5) に重なる位置にスロット孔 (8) を有する第 1のグランド層  A first ground layer that is at least partially embedded in the dielectric substrate (3, 203) and has a slot hole (8) at a position overlapping the first signal line (5);
(7) と、  (7) and
上記誘電体基板 (3, 203) の裏面に設けられた第 1の補助グランド層 (6, 206) と、  A first auxiliary ground layer (6, 206) provided on the back surface of the dielectric substrate (3, 203);
上記第 1の補助グランド層 (6, 206) から上記第 1のグランド層 (7) に 達する第 1のビアホール (15, 215) と、  A first via hole (15, 215) extending from the first auxiliary ground layer (6, 206) to the first ground layer (7);
上記第 1のビアホール (15, 215) 内を埋める第 1のビアホール導電体 (16, 216) と、  A first via-hole conductor (16, 216) filling the first via-hole (15, 215);
上記回路基板 (2, 202, 302) の表面に設けられ、 上記第 1のダランド 層 (7) のスロット孔 (8) を介して上記第 1の信号 f泉路 (5) に対向する第 2 の信号線路 (12, 312) と、  A second signal line provided on the surface of the circuit board (2, 202, 302) and facing the first signal f spring path (5) through the slot hole (8) of the first duland layer (7). Signal lines (12, 312)
上記回路基板 (2, 202, 302) の表面に設けられ、 上記第 1の補助グラ ンド層 (6, 206) に対向する第 2の補助グランド層 (14, 214) と、 上記回路基板 (2, 202, 302) の裏面に設けられた第 2のグランド層 A second auxiliary ground layer (14, 214) provided on the surface of the circuit board (2, 202, 302) and facing the first auxiliary ground layer (6, 206); , 202, 302) second ground layer
(13, 313) と、 (13, 313)
上記回路基板 (2, 202, 302) を貫通する第 2のビアホール (18, 2 18) と、  A second via hole (18, 218) penetrating the circuit board (2, 202, 302);
上記第 2のビアホール (18, 218) 内を埋める第 2のビアホール導電体 (19, 219) と、 Second via hole conductor filling the second via hole (18, 218) (19, 219),
上記第 1の補助グランド層 (6, 206) と上記第 2の補助グランド層 (14, 214) との間に設けられ、 上記第 1の補助グランド層 (6, 206) と上記第 2の補助グランド層 (14, 214) とを電気的かつ物理的に接続する導電性の 接着剤層 (17, 117, 217) と  The first auxiliary ground layer (6, 206) and the second auxiliary ground layer (6, 206) are provided between the first auxiliary ground layer (6, 206) and the second auxiliary ground layer (14, 214). A conductive adhesive layer (17, 117, 217) that electrically and physically connects the ground layer (14, 214)
を備えたことを特徴とする高周波半導体装置の実装構造。 A mounting structure for a high-frequency semiconductor device, comprising:
2. 請求項 1に記載の高周波半導体装置の実装構造において、 2. In the mounting structure of the high-frequency semiconductor device according to claim 1,
上記誘電体基板 (3, .203) の表面に形成されたキヤビティ内に、 上記高周 波半導体素子 (4) の少なくとも一部が入っていることを特徴とする高周波半導  A high-frequency semiconductor device characterized in that at least a part of the high-frequency semiconductor element (4) is contained in a cavity formed on the surface of the dielectric substrate (3, .203).
3. 請求項 1に記載の高周波半導体装置の実装構造において、 3. In the mounting structure of the high-frequency semiconductor device according to claim 1,
上記第 1のビアホール (15, 215) は複数あって、 上記複数の第 1のビア ホール (15, 215) のうちの隣り合うもの同士の間隔は Ομΐη以上 glZSaid first via hole (15, 215) is of multiple, gl Z adjacent ones spacing between the Ομΐη or more of the plurality of first via holes (15, 215)
4 ( gl :上記誘電体基板 (3, 203) 中における信号の波長) 以下に設定 されていることを特徴とする高周波半導体装置の実装構造。 4 ( gl : signal wavelength in the above dielectric substrate (3, 203)) A mounting structure of a high-frequency semiconductor device characterized by being set to or below.
4. 請求項 1に記載の高周波半導体装置の実装構造において、 4. In the mounting structure of the high-frequency semiconductor device according to claim 1,
上記第 2のビアホール (18, 218) は複数あつて、 上記複数の第 2のビア ホール (18, 218) のうちの隣り合うもの同士の間隔は O/xm以上; L g2ZA plurality of the second via holes (18, 218) are provided, and an interval between adjacent ones of the plurality of the second via holes (18, 218) is O / xm or more; L g 2 Z
4 ( g2:上記回路基板 (2, 202, 302) 中における信号の波長) 以下 に設定されていることを特徴とする高周波半導体装置の実装構造。 4: the mounting structure of the high-frequency semiconductor device, characterized in that it is set to (g 2 signal wavelength in the circuit board (2, 202, 302) in) or less.
5. 請求項 1に記載の高周波半導体装置の実装構造において、 5. In the mounting structure of the high-frequency semiconductor device according to claim 1,
上記誘電体基板 (3) と上記第 2の信号線路 (12) との間には、 厚さ 以上 200 μ m以下の空気層 (20) が介在していることを特徴とする高周波半  An air layer (20) having a thickness of not less than 200 μm is interposed between the dielectric substrate (3) and the second signal line (12).
6. 請求項 1に記載の高周波半導体装置の実装構造において、 上記接着剤層 (1 7, 1 1 7, 21 7) は、 圧縮部分にのみ導電性を有する誘 電体を含むことを特徴とする高周波半導体装置の実装構造。 6. In the mounting structure of the high-frequency semiconductor device according to claim 1, The mounting structure of a high-frequency semiconductor device, wherein the adhesive layer (17, 117, 217) includes a dielectric having conductivity only in a compressed portion.
7. 請求項 1に記載の高周波半導体装置の実装構造において、 7. In the mounting structure of the high-frequency semiconductor device according to claim 1,
上記第 1のビアホーノレ (2 1 5) は、 上記高周波半導体素子 (4) に重なるよ うに配置されていることを特徴とする高周波半導体装置の実装構造。  The mounting structure of a high-frequency semiconductor device, wherein the first via-horne (2 15) is disposed so as to overlap the high-frequency semiconductor element (4).
8. 請求項 1に記載の高周波半導体装置の実装構造において、 8. In the mounting structure of the high-frequency semiconductor device according to claim 1,
上記第 2の信号線路 (1 2) は、 入力部 (1 2 a) と、 この入力部 (1 2 a) に対して所定の間隔をあけて設けられた出力部 (1 2 b) とから成り、  The second signal line (1 2) is composed of an input section (1 2a) and an output section (1 2b) provided at a predetermined distance from the input section (1 2a). Consisting of
上記第 1, 第 2のビアホール (21 5, 21 8) は、 上記入力部 (1 2 a) と 上記出力部 (1 2 b) との間の領域に重なるように複数配置されていることを特 徴とする高周波半導体装置の実装構造。  A plurality of the first and second via holes (215, 218) are arranged so as to overlap a region between the input section (1 2a) and the output section (1 2b). The featured mounting structure of high-frequency semiconductor devices.
9. 請求項 1に記載の高周波半導体装置の実装構造において、 9. In the mounting structure of the high-frequency semiconductor device according to claim 1,
上記回路基板 (302) の裏面にアンテナ (326) が設けられていることを 特徴とする高周波半導体装置の実装構造。  A mounting structure for a high-frequency semiconductor device, wherein an antenna (326) is provided on a back surface of the circuit board (302).
10. 請求項 1に記載の高周波半導体装置 ( 1 ) の実装構造をフロントエンド 部 (80) に用いたことを特徴とする高周波送信装置。 10. A high-frequency transmission device, wherein the mounting structure of the high-frequency semiconductor device (1) according to claim 1 is used for a front-end part (80).
1 1. 請求項 1に記載の高周波半導体装置 ( 1 ) の実装構造をフロントエンド 部 (90) に用いたことを特徴とする高周波受信装置。 1 1. A high-frequency receiving device characterized in that the mounting structure of the high-frequency semiconductor device (1) according to claim 1 is used for a front-end part (90).
PCT/JP2003/016856 2003-03-05 2003-12-26 Packaging structure of high frequency semiconductor device, high frequency transmitter and high frequency receiver employing it WO2004079821A1 (en)

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