WO2004088727A3 - Multi-chip ball grid array package and method of manufacture - Google Patents

Multi-chip ball grid array package and method of manufacture Download PDF

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Publication number
WO2004088727A3
WO2004088727A3 PCT/IB2004/001734 IB2004001734W WO2004088727A3 WO 2004088727 A3 WO2004088727 A3 WO 2004088727A3 IB 2004001734 W IB2004001734 W IB 2004001734W WO 2004088727 A3 WO2004088727 A3 WO 2004088727A3
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WO
WIPO (PCT)
Prior art keywords
opening
base
substrate
manufacture
grid array
Prior art date
Application number
PCT/IB2004/001734
Other languages
French (fr)
Other versions
WO2004088727A8 (en
WO2004088727A2 (en
WO2004088727B1 (en
Inventor
Fung Leng Chen
Seong Kwang Brandon Kim
Wee Lim Cha
Yi-Sheng Anthony Sun
Wolfgang Hetzel
Jochen Thomas
Original Assignee
United Test & Assembly Ct Ltd
Infineon Technologies
Fung Leng Chen
Seong Kwang Brandon Kim
Wee Lim Cha
Yi-Sheng Anthony Sun
Wolfgang Hetzel
Jochen Thomas
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Test & Assembly Ct Ltd, Infineon Technologies, Fung Leng Chen, Seong Kwang Brandon Kim, Wee Lim Cha, Yi-Sheng Anthony Sun, Wolfgang Hetzel, Jochen Thomas filed Critical United Test & Assembly Ct Ltd
Priority to DE112004000572T priority Critical patent/DE112004000572B4/en
Priority to US10/552,046 priority patent/US7851899B2/en
Publication of WO2004088727A2 publication Critical patent/WO2004088727A2/en
Publication of WO2004088727A3 publication Critical patent/WO2004088727A3/en
Publication of WO2004088727A8 publication Critical patent/WO2004088727A8/en
Publication of WO2004088727B1 publication Critical patent/WO2004088727B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

A BGA package (500) is disclosed including a base IC structure (300) having a base substrate (302), with an opening (301c) running lengthwise therethrough. A first semiconductor chip (315) is mounted face-down on the base substrate (301) so that the bond pads (317) thereof are accessible through the opening (301c). The package (500) also includes a secondary IC structure (400) including a secondary substrate (401), having an opening (401c) running there through, and a second semiconductor chip (415). The second chip (415) is mounted face-down on the secondary substrate (401) so that the bond pads (417) thereof are accessible through the opening (401c) in the secondary substrate (401). An encapsulant (425) fills the opening (401c) in the secondary substrate (401) and forms a substantially planar surface (425a) over the underside of the secondary substrate (401). The substantially planar surface (425a) is mounted to the first chip (315) of the base IC structure (300) through an adhesive (504). Wires (521) connect a conductive portion (406) of the secondary IC structure (400) to a conductive portion (303) of the base IC structure (300).
PCT/IB2004/001734 2003-04-02 2004-04-02 Multi-chip ball grid array package and method of manufacture WO2004088727A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE112004000572T DE112004000572B4 (en) 2003-04-02 2004-04-02 Multi-chip ball grid array housing and manufacturing process
US10/552,046 US7851899B2 (en) 2004-04-02 2004-04-02 Multi-chip ball grid array package and method of manufacture

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US45935303P 2003-04-02 2003-04-02
US60/459,353 2003-04-02

Publications (4)

Publication Number Publication Date
WO2004088727A2 WO2004088727A2 (en) 2004-10-14
WO2004088727A3 true WO2004088727A3 (en) 2004-11-11
WO2004088727A8 WO2004088727A8 (en) 2004-12-29
WO2004088727B1 WO2004088727B1 (en) 2005-03-10

Family

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Family Applications (1)

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PCT/IB2004/001734 WO2004088727A2 (en) 2003-04-02 2004-04-02 Multi-chip ball grid array package and method of manufacture

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DE (1) DE112004000572B4 (en)
TW (1) TWI338927B (en)
WO (1) WO2004088727A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200536089A (en) * 2004-03-03 2005-11-01 United Test & Assembly Ct Ltd Multiple stacked die window csp package and method of manufacture
SG130055A1 (en) 2005-08-19 2007-03-20 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
SG130066A1 (en) 2005-08-26 2007-03-20 Micron Technology Inc Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010012526A1 (en) * 1997-07-09 2001-08-09 Tandy Patrick W. Package stack via bottom leaded plastic (BLP) packaging
US6424033B1 (en) * 1999-08-31 2002-07-23 Micron Technology, Inc. Chip package with grease heat sink and method of making
US20020127771A1 (en) * 2001-03-12 2002-09-12 Salman Akram Multiple die package
US20020189852A1 (en) * 1998-09-22 2002-12-19 Kabushiki Kaisha Toshiba Fabricating method of semiconductor devices, fabricating method of printed wired boards, and printed wired board

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10259221B4 (en) * 2002-12-17 2007-01-25 Infineon Technologies Ag Electronic component comprising a stack of semiconductor chips and method of making the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010012526A1 (en) * 1997-07-09 2001-08-09 Tandy Patrick W. Package stack via bottom leaded plastic (BLP) packaging
US20020189852A1 (en) * 1998-09-22 2002-12-19 Kabushiki Kaisha Toshiba Fabricating method of semiconductor devices, fabricating method of printed wired boards, and printed wired board
US6424033B1 (en) * 1999-08-31 2002-07-23 Micron Technology, Inc. Chip package with grease heat sink and method of making
US20020127771A1 (en) * 2001-03-12 2002-09-12 Salman Akram Multiple die package

Also Published As

Publication number Publication date
TW200504894A (en) 2005-02-01
WO2004088727A8 (en) 2004-12-29
TWI338927B (en) 2011-03-11
WO2004088727A2 (en) 2004-10-14
DE112004000572B4 (en) 2008-05-29
WO2004088727B1 (en) 2005-03-10
DE112004000572T5 (en) 2006-03-23

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