WO2004100232A1 - Method for forming the top plate of a mim capacitor with a single mask in a copper dual damascene integration scheme - Google Patents

Method for forming the top plate of a mim capacitor with a single mask in a copper dual damascene integration scheme Download PDF

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Publication number
WO2004100232A1
WO2004100232A1 PCT/EP2004/050716 EP2004050716W WO2004100232A1 WO 2004100232 A1 WO2004100232 A1 WO 2004100232A1 EP 2004050716 W EP2004050716 W EP 2004050716W WO 2004100232 A1 WO2004100232 A1 WO 2004100232A1
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insulating layer
layer
capacitor
forming
depositing
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PCT/EP2004/050716
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French (fr)
Inventor
Hans-Joachim Barth
Petra Felsner
Gerald Rudolf Friese
Erdem Kaltalioglu
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Infineon Technologies Ag
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Publication of WO2004100232A1 publication Critical patent/WO2004100232A1/en

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805—Capacitors only
    • H—ELECTRICITY
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    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising transition metals
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31616—Deposition of Al2O3
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/318—Inorganic layers composed of nitrides
    • H01L21/3185—Inorganic layers composed of nitrides of siliconnitrides
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    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material

Definitions

  • the present invention relates generally to the fabrication of semiconductor devices, and more particularly to a method of manufacturing a mclal-insulator-metal (MIM) capacitor and structure thereof.
  • MIM mclal-insulator-metal
  • Capacitors arc used extensively in electronic devices for storing an electric charge.
  • Capacitors essentially comprise two conductive plates separated by an insulator. Capacitors arc used in filters, analog-to- digital converters, memory devices, various control applications, and mixed signal and analog devices, for example.
  • MIM capacitor MIM capacitor
  • a MIM capacitor is a particular type of capacitor having two metal plates sandwiched around a capacitor dielectric that is parallel to a semiconductor wafer surface. They are rather large in size, being several hundred micrometers wide, for example, depending on the capacitance, which is much larger than a transistor or memory cell, for example.
  • MIM capacitors are typically used as decoupling capacitors for microprocessor units (MPU's), RF capacitors in high frequency circuits, and filter and analog capacitors in mixed-signal products, as examples.
  • the top capacitor metal plate is formed by a planar deposition of a conductive material, and lithographically patterning and etching the conductive material using a reactive ion etch (RJE) process, for example.
  • RJE reactive ion etch
  • the MIM capacitor bottom plate e.g., the MIM capacitor bottom plate
  • vias to connect to interconnect layers e.g., the MIM capacitor bottom plate
  • MIM dielectric materials due to potential interaction with or diffusion of the metals (such as copper) used for the metal plates.
  • the MIM dielectric material restriction may result in limited area capacitance.
  • Another problem in fabricating MIM capacitors is that, in order to avoid problems that arise in fabricating semiconductor devices using copper, often higher resistive plate materials such as aluminum, titanium nitride, and tungsten, as examples, arc used for the top and bottom metal plates, which results in reduced high frequency capability.
  • the use of copper, which has a lower resistivity, for the lop and bottom metal plates is therefore desired.
  • the use of copper for the lop and bottom metal capacitor plates also produces a MIM capacitor having higher quality factors (Q- values).
  • a further problem in the manufacturing of MIM capacitors is etch slop problems during subsequent via etches. Vias arc typically used lo connect Ihc lop and bottom metal plates to subsequently formed metallization layers. Because of topography differences for the top and
  • top plate of a MIM capacitor is formed in a damascene process, and both die top plate and bottom plate are covered with a cap layer d at acts as a diffusion barrier.
  • a mask is not required to pattern the top plalc, bul rather, the top plate is formed by the planarization of the damascene structure formed within an insulating material.
  • a method of fabricating a MIM capacitor includes providing a semiconductor wafer, forming at least one first capacitor plate over the wafer, and forming a first insulating layer over the wafer, wherein a top surface of the at least one first capacitor plate is exposed.
  • a first cap layer is selectively formed over the al leasl one firsl capacitor plalc lop surface, and a second insulating layer is formed over the first insulating layer and die first cap layer, the second insulating layer having a top surface.
  • the second insulating layer is patterned with at leasl one second capacitor plate pattern, and a capacitor dielectric layer is deposited over the second insulating layer.
  • a second capacitor plalc material is deposited over the capacitor dielectric layer, and the wafer is planarized to remove the second capacitor plate material and capacitor dielectric layer from over the second insulating layer top surface and form at least one second capacitor plate within the patterned second insulating layer.
  • the at least one second capacitor plate, capacitor dielectric layer and at least one first capacitor plate form a MIM capacitor.
  • a MIM capacitor includes a semiconductor wafer, a first insulating material disposed over the wafer, and a first capacitor plate disposed over the semiconductor wafer wilhin the first insulating material.
  • the MIM capacitor includes a first cap layer disposed over the first capacitor plate, a second insulating layer disposed over the firsl insulating layer and first cap layer, and a capacitor dielectric disposed over and abutting at least a portion of the first cap layer within the second insulating layer.
  • a second capacitor plate is disposed over and abutting the capacitor dielectric within the second insulating layer, and a second cap layer is disposed over the second capacitor plalc.
  • Embodiments of the present invention achieve technical advantages by providing a simplified integration scheme for forming a MIM capacitor, resulting in a reduction in lithography steps, and reduced cost.
  • the invention provides for increased area capacitance, because of a wider range of MIM capacitor dielectric materials that may be used. Because cap layers arc used over the capacitor plates, the choice of the MIM capacitor dielectric is not limited by copper diffusion or by poor adhesion between the copper material and MIM capacitor dielectric material. The cap layers prevent affecting the copper of the capacitor plates during the MIM dielectric deposition.
  • Embodiments of the invention result in the elimination or reduction of different via heights for vias for the top and bottom plates.
  • Copper may be used as a material for the top and bottom plate in the integration scheme, which results in a higher frequency capability. Because the top plate is formed in a damascene process, after a planarizing step, a mask and etch process is not required to form the top plate, which solves alignment problems for the top plate. Thus, embodiments of the present invention solve several problems simultaneously.
  • Figures 1, 2, and 3a show cross-sectional views of an embodiment of the present invention at various stages of fabrication, wherein cap layers are formed over the bottom capacitor plate and top capacitor plate, and wherein the top capacitor plate is formed in a damascene process;
  • Figure 3b shows an embodiment of the invention, wherein a trough for conductive line is formed in a subsequent insulating layer, making electrical contact of a conductive line directly to the top plate;
  • Figures 4 and 5 illustrate cross-sectional views of an embodiment of the invention at various stages of fabrication, wherein the bottom capacitor plate makes electrical contact to an underlying interconnect layer;
  • Figure 6 shows and embodiment of the invention, wherein cap layers are formed on the bottom and top capacitor plates by recessing the plate conductive material, forming a catalytic activation layer over the conductive material, and selectively forming a conductive barrier layer within the conductive material recess.
  • the substrate 110 typically comprises a semiconductor material such as single- crystal silicon, and may include other conductive layers or other semiconductor elements such as transistors or diodes, as examples (not shown).
  • the substrate 110 may alternatively comprise compound semiconductors such as GaAs, InP, Si Ge, SiC, as examples.
  • the substrate 110 may also be referred to herein as a workpiece, and may comprise a silicon-on-insulator (SOI) substrate, for example.
  • SOI silicon-on-insulator
  • the substrate 110 or workpiece may include field oxide, active component regions, and/or shallow trench isolation or deep trench isolation regions, not shown.
  • a first insulating layer 120 is deposited or formed over the substrate 110.
  • the first insulating layer 120 may comprise silicon dioxide, and may also comprise a low-dielectric constant material, having a dielectric constant k of 3.6 or less, for example.
  • the first insulating layer 120 is patterned and etched with a pattern for a bottom capacitor plate in a damascene process, for example.
  • the patterned first insulating layer 120 is filled with a first conductive material 122, and die wafer is planarized, e.g., using a chemical-mechanical polish process, to remove excess first conductive material 122 from the surface of the firsl insulating layer 120, for example.
  • the bottom capacitor plate may be formed using a non-damascene process, such as by depositing and patterning the first conductive material 122, followed by the deposition of the first insulating material 120, for example, and planarization of the first insulating material 120 to remove excess first insulating material 120 from the top surface of the first conductive material 122.
  • the first conductive material 122 preferably comprises a metal such as a copper alloy, such as Cu-Al, Cu-Mg, Cu-Sn, Cu-In, Cu-Zr, and Cu-Ag, as examples.
  • the first conductive material 122 may alternatively comprise aluminum, tungsten, titanium or copper, or combinations thereof, as examples.
  • the first conductive material 122 may comprise a thickness ranging from 500 to 1000 nm, and more preferably may comprise a thickness of about 700 nm, for example.
  • the first conductive material 122 may alternatively comprise other conductive materials, for example.
  • the first conductive material 122 may include a liner (not shown; see 216 in Figure 4).
  • the first conductive material 122 comprises copper, which has a low resistivity compared to other metals, for example.
  • a liner/copper seed layer combination (not shown in Figure 1; sec Figure 4) may be deposited, as described for the formation of a bottom capacitive plate in U.S. 6,451,664 Bl, enti ⁇ ed "Method of Making MIM Capacitor with Self-Passivating Plates," which is incorporated herein by reference.
  • a liner is deposited over the first dielectric layer 120.
  • the liner may comprise Ta, TaN, W, WN, Ti, TiN deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD), as examples.
  • a seed layer is then deposited over the liner, the seed layer comprising a copper alloy seed layer deposited by PVD or CVD, as example.
  • the first conductive material 122 is deposited over the liner/seed layer by electroplating, PVD or CVD, as examples.
  • a first cap layer 124 is then formed over the first conductive material 122.
  • the first cap layer 124 may comprise a sclf-passivaling material as described in U.S. Patent No.
  • the first capacitor plate 122 is preferably formed in a damascene process. Forming the first capacitor plate comprises patterning the first insulating layer 120 witii a pattern for tire first capacitor plate, and depositing an alloy-contaming seed layer (not shown in Figure 1; see Figure 4) over the patterned first insulating layer 120. The first conductive material 122 is then deposited over the seed layer. When the wafer is annealed, the firsl cap layer 124 is selectively formed by the dopants, e.g., the alloy in the seed layer for the first conductive material passivates the top surface of the at least one first capacitor plate 122 and forms the first cap layer 124.
  • the dopants e.g., the alloy in the seed layer for the first conductive material passivates the top surface of the at least one first capacitor plate 122 and forms the first cap layer 124.
  • the first cap layer 124 is formed by die segregation of the dopants from the seed layer or alternatively, (for example, if a seed layer is not used) a dopant or alloy in the bulk first conductive material 122, to the top surface of the first conductive material 122. Note that the segregation of dopants during the anneal process results in the first cap layer 124 being formed at all surfaces of the first conductive material 122, including the sides and bottom surface, as described in U.S. Patent No. 6,451,664 Bl; however, only the passivated surface at the top surface is of concern in the present invention and is thus shown in the figures. Thus, in this embodiment, the firsl cap layer 124 comprises a dopant-rich layer, formed by annealing.
  • the first cap layer 124 may comprise a selectively deposited material such as CoWP, CoP, CoWB, NiMoP, Re or Ru, as examples, as described in U.S. patent application entitled, "Method to Form Selective Cap Layers on Metal Features with Narrow Spaces," application Serial Number xx/xxx,xxx, which is filed herewith and which is incorporated herein by reference.
  • the first conductive material 122 is recessed (not shown; see Figure 6), and then a catalytic activation layer is formed over the top surface of the firsl conductive material 122.
  • a conductive barrier layer is then selectively deposited over the catalytic activation barrier.
  • the first cap layer 124 in this embodiment comprises die catalytic activation barrier and the conductive barrier layer, to be described further herein with reference to Figure 6. [0028]
  • the first cap layer 124 protects the first conductive material 122 top surface from any reactive agents or chemicals introduced during the subsequent deposition of the MEM dielectric material.
  • an optional dielectric cap layer may be deposited over the exposed portions of the first insulating layer 120 and first cap layer 124 (not shown in Figure 1; see Figure 4 at 226).
  • a MIM capacitor top plate 134/136 and capacitor dielectric 132 are formed using a damascene process.
  • a second insulating layer 130 is deposited over the exposed portions of the first insulating layer 120 and the first cap layer 124, (or over the optional dielectric cap layer, if one is used, not shown.)
  • the second insulating layer 130 preferably comprises a conventional dielechic, such as an oxide, e.g., silicon dioxide, fluorinated silicate glass (FSG), a low dielectric constant material, such as SiLKTM, FlareTM, SiCOH, CoralTM, Black DiamondTM, or a porous low dielectric constant material, as examples.
  • the second insulating layer 130 is thin, comprising a thickness of 250 nm or less, and more preferably comprising a thickness of 50 nm or less, for example.
  • the thin second insulating layer 130 allows the formation of a thin MIM capacitor dielechic layer and thin MEM capacitor top plate, e.g., having a thickness of about 50 to 150 nm or less each. This is advantageous, because the depth difference of the contacting vias to the top plate 136 and the bottom plate 122 can be reduced.
  • the second insulating layer 130 is relatively thick, e.g., 300 to 1000 nm thick.
  • the MIM capacitor lop plate 136 may not require a via connection, advantageously, because the top plate 136 can be contacted in a trough etch of a
  • the second insulating layer 130 is patterned using photolithography and etch processes to create an opening 128 for the top plalc, shown in phantom in Figure 1.
  • a photoresist 129 may be deposited, exposed and developed, and the photoresist 129 may then be used to pallem the second insulating layer 130.
  • a top surface of the first cap layer 124 is exposed after the patterning of the second insulating layer 130, for example.
  • the etch process is preferably designed to stop on top of or within the first cap layer 124. Subsequently, the photoresist 129 is stripped.
  • the first cap layer 124 comprises a self-passivation layer
  • a portion of the self- passivation layer may be removed during the etch process, due to an over-etch, for example.
  • the self-passivation layer e.g., firsl cap layer 124
  • the self-passivation layer may be repaired by an optional anneal step, e.g., at approximately 400 degrees C or less, to induce another dopant segregation and copper self-passivation, for example.
  • the second insulating layer 130 comprises a photosensitive low-k material, such as mclhylsilscsquiazanc (MSZ), having a dielectric constant k of approximately 2.7, porous MSZ, having a k of less than 2.7, or another mechanically stable and photosensitive material, as examples.
  • a photosensitive low-k material such as mclhylsilscsquiazanc (MSZ)
  • MSZ mclhylsilscsquiazanc
  • the etch and ship processes may not be required, if a photosensitive low-k material is used for the second insulatmg layer 130 material.
  • the patterning of the second insulating layer 130 is preferably by UV lithography or electron beam irradiation, when the second insulating layer 130 comprises a photosensitive low-k material.
  • a capacitor dielectric material layer 132 is deposited over the patterned second insulating layer 130 and exposed first cap layer 124 top surface.
  • the capacitor dielectric layer 132 typically comprises an insulator, such as silicon dioxide or silicon nitride, and alternatively, the capacitor dielectric layer 132 may comprise high dielectric constant materials, for example.
  • the capacitor dielechic layer 132 may alternatively comprise other dielectric materials.
  • the capacitor dielectric layer 132 may be about 540 Angstroms thick or less, for example, and may alternatively comprise 1000 Angstroms or less, for example.
  • the capacitor dielectric layer 132 is preferably confo ⁇ nal and is evenly deposited over the top surface and sidewalls of the paltemed second insulating layer 130 and lop surface of Ihc exposed first cap layer 124, for example.
  • d e bottom capacitor plate 122 includes a first cap layer 124
  • die bottom plate 122 surface is passivatcd, allowing an increased selection of materials for the MIM capacitor dielectric layer 132.
  • the MIM capacitor dielectric material layer 132 may comprise an oxide, silicon nitride, or various high k materials, such as AI 2 O 3 , Ta 2 ⁇ 5 , or BSTO, as examples.
  • the MIM capacitor dielectric material layer 132 may be deposited using atomic-layer CVD, and may comprise a highly conformal and or low temperature dielectric material, for example.
  • a second conductive material 136 is formed or deposited over the capacitor dielectric layer 132.
  • the second conductive material 136 typically comprises a metal such as aluminum, tungsten, titanium, or copper, or combinations thereof.
  • the second conductive material 136 may be 600 Angstroms thick, for example, and may alternatively comprise 1000 Angstroms or less, for example.
  • the second conductive material 136 may alternatively comprise other conductive materials, for example.
  • the second conductive material 136 comprises copper or a copper alloy, such as Cu-Al, Cu-Mg, Cu-Sn, Cu-In, Cu-Zr, or Cu-Ag, as examples, due to the lower resistivity of copper and to achieve improved electrical results.
  • a liner/copper seed layer 134 combination may be deposited, as described for the formation of a bottom capacitive plate in U.S. 6,451,664 Bl, for example.
  • a liner is deposited over the capacitor dielectric layer 132.
  • the liner may comprise Ta, TaN, W, WN, Ti, TiN deposited by PVD or CVD, as example.
  • a seed layer is deposited over the liner, the seed layer comprising a copper alloy seed layer deposited by PVD or CVD, as an example.
  • the second conductive material 136 is deposited over the liner/seed layer 134 by electroplating, PVD or CVD, as examples.
  • second conductive material 136, liner/seed layer 134, and capacitor dielectric layer 132 arc then removed from the top surface of the second insulating layer 130, using a CMP process, or RIE, as examples, as shown in Figure 3a.
  • the lop plate material 134/136 does not need to be patterned using lithography. Rather, because the second insulating layer 130 has been paltemed before deposition of the top plate materials 134/136, the planarization of the second insulating layer 130 forms the top plalc 134/136 and also patterns the capacitor dielectric layer 132.
  • a second cap layer 138 may be formed on the top surface of the second conductive material 136, as described for the first conductive material 122.
  • the second cap layer 138 may be formed in a similar process as described for the first cap layer 124, for example.
  • the second cap layer 138 may comprise a sclf-passivating material, such as a dopant-rich layer, formed by annealing, or alternatively, the second cap layer 138 may comprise a selectively deposited material such as CoWP, CoWB, CoP, NiMoP, Re or Ru, as examples.
  • the second cap layer 138 protects the second conductive material 136 top surface from any reactive agents or chemicals introduced during die subsequent deposition of a dielectric material, to be described further herein.
  • the M capacitor 150 comprises bottom plate 122/124, capacitor dielectric 132, and top plate 134/136/138. Additional dielectric or insulating layers such as a third insulating layer 140 may then be deposited and a single or dual damascene process sequence may be continued, to pattern and fill the next via and wiring levels, for example.
  • the third insulating layer 140 and second insulating layer 130 may be patterned and etched with first vias 142 to the MIMcap lop plate 132/134/136 and second vias 144 to the MIMcap bottom plate 122/124, for example, as shown in phantom in Figure 3a. If the second insulating layer 130 is thin, as in a preferred embodiment of the invention, then tiiere is less variation in the height of die first vias 142 and the second vias 144, advantageously.
  • the second insulating layer 130 is relatively thick, e.g., 300 to 1000 nm thick.
  • the MIM capacitor top plate 136 may not require a via connection, advantageously, because the top plate 136 can be contacted in a trough etch of a subsequent damascene interconnect level 140, for example, as shown.
  • the only part or the second insulating layer 130 that must be opened is the via 152 to the bottom plate 122/124.
  • the second insulating layer 130 and third insulating layer 140 in this embodiment may be patterned in a dual damascene process (e.g., second insulating layer 130 is patterned, followed by the patterning of the third insulating layer 140, or vice versa).
  • conductive line 154 that abut the top metal plate 134/136/138, via 152, and conductive hne 156 diat is an extension of via 152 are formed at once. Excess conductive material is then removed from die top surface of the third insulating layer 140, e.g. in a planarization step.
  • the MIM capacitor bottom plate 122/124 needs to be contacted by vias, but those may be patterned on the same metallization level as conductive lines 154 to the lop plate and other contacting vias e.g., for other elements of the semiconductor wafer (not shown) are formed, as shown in Figure 3b.
  • FIG. 4 Another embodiment of the present invention is shown in Figures 4 and 5. While not all preferred and alternative materials are described herein with reference to Figures 4, 5 and 6 to avoid repetition, corresponding numerals are used that were used to describe Figures 1 through 3.
  • element lxx in Figures 1-3 corresponds to and preferably comprises similar materials and thickness as clement 2xx in Figures 4 and 5, and element 3xx in Figure 6.
  • first metallization lines 212 arc formed beneath the bottom plate 216/222 before the bottom plate 216/222 is formed. Vias 214 are formed in the first insulating layer 220 to contact the bottom plate 216/222.
  • the bottom plate 216/222 includes a liner 216, which may comprise a bi-laycr of a liner such as TaN, TiN, WN, Ta or combinations thereof, as examples, and a seed layer comprising a copper alloy, for example.
  • First insulating layer 220 may include three separate dielectric layers (not shown), one for d e first metallization lines 212, one layer for vias 214, and anotiier layer for the MIM capacitor bottom plate 216/222, for example.
  • a first cap layer 224 is formed over the first conductive material 222.
  • the first cap layer 224 may comprise a self-passivating layer
  • a dielechic cap layer 226 is deposited or formed over the first cap layer 224 and exposed portions of the first insulating layer 220.
  • the dielectric cap layer 226 preferably comprises SiN, SiC, SiCN or BloKTM or another dielectric material with diffusion barrier properties against metal ion or metal atom diffusion, as examples. Alternatively, the dielectric cap layer 226 may comprise other dielectric materials.
  • the second insulating layer 230 is deposited over the dielectric cap layer 226, and the second insulating layer 230 and dielectric cap layer 226 are patterned with the top plate pattern 228, as shown in phantom in Figure 4.
  • a MIM capacitor dielechic layer 232 is deposited or formed over the patterned second insulating layer 230, and a lincr/sccd layer 234 is deposited over the capacitor dielectric layer 232.
  • a second conductive material 236 is deposited over the lincr/sccd layer 234.
  • the wafer is planarized to form the MIM capacitor top plate, which comprises liner/seed layer 232 and conductive material 236.
  • a second cap layer 238 is selectively fonned over the MIMcap top plate 234/236.
  • a third insulating layer 240 is deposited over the MIM capacitor 250, and the third insulating layer 240 is patterned witii vias 242 and second metallization lines 246, for example, in a dual damascene process. Note that the vias 242 contain the same height, solving the etch stop problems of prior art via formation due to the varying depths of the vias for contacting the top plate 234/236/238 and bottom plate 216/222/224.
  • the patterned third insulating layer 240 is filled with a conductive material to form vias 242 and second metallization lines 246.
  • the capacitor plates are considered to also comprise the first and second cap layers.
  • Figure 6 Another embodiment of the present invention is shown in Figure 6.
  • die cap layers for the bottom and top capacitor plates are formed as described in U.S. Patent Application Serial No. xx/xxx,xxx, filed herewith, entitled, "Method to Form Selective Cap Layers on Metal Features with Narrow Spaces,” which is incorporated herein by reference.
  • an optional liner 316 is deposited or formed over Ihc first insulating layer 320.
  • the firsl conductive material 322 is deposited or formed and then recessed to a height slightly below, e.g., 20 nm or less, below the top surface of the first insulating layer 320. All or a portion of the finer 316 may be removed during the recessing of the first conductive material 322, depending on the method used to recess the first conductive material 322.
  • a catalytic activation layer 362 is then deposited over the top surface of the first conductive material 322.
  • the catalytic activation layer 362 may comprise palladium (Pd) deposited in a layer of approximately one to three atoms thick, for example.
  • a conductive barrier layer 364 is then deposited over the catalytic activation layer 362.
  • the conductive bamer layer 364 preferably comprises a material such as CoWP, CoP, CoWB, NiMoP, Re or Ru, as examples.
  • die cap layer for Hie bottom capacitor plate comprises catalytic
  • the MIM capacitor 350 is then fabricated as described herein for the other embodiments.
  • the second conductive material 336 is recessed below the lop surface of the second insulating layer 330, e.g., 20 nm or less, below the top surface of the second insulating layer 330.
  • a portion of or all of the optional liner 334 may be removed during the recessing of the second insulating layer 330.
  • a catalytic activation layer 358 comprising, for example, one lo three atom layers of Pd, is then deposited over the top surface of the second conductive material 322.
  • a conductive barrier layer 360 comprises a material such as CoWP, CoP, CoWB, NiMoP, Re or Ru, as examples, is then deposited over the catalytic activation layer 358.
  • excess conductive barrier layer 360 on the lop surface of the second insulating layer 330 is removed, resulting in the conductive barrier layer 360 having a top surface that is co-planar with the lop surface of die second insulating layer 330.
  • the cap layer for the top capacitor plate comprises catalytic activation layer 358 and conductive barrier layer 360.
  • the MIM capacitor 350 includes bottom plate 316/322/362/364, capacitor dielectric 332, and top plate 334/336/358/360.
  • Embodiments of the present invention provided a simplified integration scheme for forming a MIM capacitor 150/250/350, a reduction in lidiography steps, and reduced cost.
  • the novel integration schemes for fabricating a MIM capacitor described herein solve several problems simultaneously.
  • embodiments of the present invention provide for increased area capacitance, because of a wider range of MIM capacitor dielectric materials that may be used.
  • the choice of die MIM capacitor dielechic is not limited by copper diffusion or by poor adhesion between the copper material and MIM capacitor dielectric material, or by affecting the copper during the MIM dielechic deposition, because of the barrier provided by the first cap layers 124, 224 and 362/364 and second cap layers 138, 238 and 358/360.

Abstract

A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bottom plate. The insulating layer is patterned with a MIM capacitor top plate pattern, and a MIM dielectric material is deposited over the patterned insulating layer. A conductive material is deposited over the MIM dielectric material, and the wafer is planarized to remove the conductive material and MIM dielectric material from the top surface of the insulating layer and form a MINI capacitor top plate. A second cap layer is selectively formed over the MIM capacitor top plate.

Description

METHOD FOR FORMING THE TOP PLATE OF A MIM CAPACITOR WITH A SINGLE MASK IN A COPPER DUAL DAMASCENE INTEGRATION SCHEME
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application relates to the following co-pending and commonly assigned patent application: Serial No. xx/xxx,xxx, filed herewith, entitled, "Method to Form Selective Cap Layers on Metal Features with Narrow Spaces," which application is hereby incorporated herein by reference.
TECHNICAL FIELD
[0002] The present invention relates generally to the fabrication of semiconductor devices, and more particularly to a method of manufacturing a mclal-insulator-metal (MIM) capacitor and structure thereof.
BACKGROUND
[0003] Capacitors arc used extensively in electronic devices for storing an electric charge.
Capacitors essentially comprise two conductive plates separated by an insulator. Capacitors arc used in filters, analog-to- digital converters, memory devices, various control applications, and mixed signal and analog devices, for example.
[0004] There is a demand in semiconductor device technology to integrate many different functions on a single chip, e.g. manufacturing analog and digital circuitry on the same die. MIM capacitor (MIMcap's) are often used in these integrated circuits. A MIM capacitor is a particular type of capacitor having two metal plates sandwiched around a capacitor dielectric that is parallel to a semiconductor wafer surface. They are rather large in size, being several hundred micrometers wide, for example, depending on the capacitance, which is much larger than a transistor or memory cell, for example. MIM capacitors are typically used as decoupling capacitors for microprocessor units (MPU's), RF capacitors in high frequency circuits, and filter and analog capacitors in mixed-signal products, as examples.
[0005] To form a MIM capacitor, the top capacitor metal plate is formed by a planar deposition of a conductive material, and lithographically patterning and etching the conductive material using a reactive ion etch (RJE) process, for example. The patterning of the top metal plate requires the use of a mask, and there can be alignment problems to underlying features
(e.g., the MIM capacitor bottom plate) and vias to connect to interconnect layers.
[0006] Another problem in fabricating MIM capacitors is a restriction in the selection of the
MIM dielectric materials, due to potential interaction with or diffusion of the metals (such as copper) used for the metal plates. The MIM dielectric material restriction may result in limited area capacitance.
[0007] Another problem in fabricating MIM capacitors is that, in order to avoid problems that arise in fabricating semiconductor devices using copper, often higher resistive plate materials such as aluminum, titanium nitride, and tungsten, as examples, arc used for the top and bottom metal plates, which results in reduced high frequency capability. The use of copper, which has a lower resistivity, for the lop and bottom metal plates is therefore desired. The use of copper for the lop and bottom metal capacitor plates also produces a MIM capacitor having higher quality factors (Q- values).
[0008] A further problem in the manufacturing of MIM capacitors is etch slop problems during subsequent via etches. Vias arc typically used lo connect Ihc lop and bottom metal plates to subsequently formed metallization layers. Because of topography differences for the top and
bottom metal plates, more insulating material must be etched lo reach Ihe bottom plate than to reach the top plate, and this can create etch stop problems when etching the vias. [0009] What is needed in the art is an improved integration scheme for fabricating a MIM capacitor thai solves these problems in the prior art.
SUMMARY OF THE INVENTION
[0010] These and other problems are generally solved or circumvented, and technical advantages arc generally achieved, by preferred embodiments of the present invention, which provide an improved integration scheme for fabricating a MIM capacitor. The top plate of a MIM capacitor is formed in a damascene process, and both die top plate and bottom plate are covered with a cap layer d at acts as a diffusion barrier. A mask is not required to pattern the top plalc, bul rather, the top plate is formed by the planarization of the damascene structure formed within an insulating material.
[0011] In accordance with a preferred embodiment of the present invention, a method of fabricating a MIM capacitor includes providing a semiconductor wafer, forming at least one first capacitor plate over the wafer, and forming a first insulating layer over the wafer, wherein a top surface of the at least one first capacitor plate is exposed. A first cap layer is selectively formed over the al leasl one firsl capacitor plalc lop surface, and a second insulating layer is formed over the first insulating layer and die first cap layer, the second insulating layer having a top surface. The second insulating layer is patterned with at leasl one second capacitor plate pattern, and a capacitor dielectric layer is deposited over the second insulating layer. A second capacitor plalc material is deposited over the capacitor dielectric layer, and the wafer is planarized to remove the second capacitor plate material and capacitor dielectric layer from over the second insulating layer top surface and form at least one second capacitor plate within the patterned second insulating layer. The at least one second capacitor plate, capacitor dielectric layer and at least one first capacitor plate form a MIM capacitor.
[0012] In accordance with another preferred embodiment of the present invention, a MIM capacitor includes a semiconductor wafer, a first insulating material disposed over the wafer, and a first capacitor plate disposed over the semiconductor wafer wilhin the first insulating material. The MIM capacitor includes a first cap layer disposed over the first capacitor plate, a second insulating layer disposed over the firsl insulating layer and first cap layer, and a capacitor dielectric disposed over and abutting at least a portion of the first cap layer within the second insulating layer. A second capacitor plate is disposed over and abutting the capacitor dielectric within the second insulating layer, and a second cap layer is disposed over the second capacitor plalc.
[0013] Embodiments of the present invention achieve technical advantages by providing a simplified integration scheme for forming a MIM capacitor, resulting in a reduction in lithography steps, and reduced cost. The invention provides for increased area capacitance, because of a wider range of MIM capacitor dielectric materials that may be used. Because cap layers arc used over the capacitor plates, the choice of the MIM capacitor dielectric is not limited by copper diffusion or by poor adhesion between the copper material and MIM capacitor dielectric material. The cap layers prevent affecting the copper of the capacitor plates during the MIM dielectric deposition. Embodiments of the invention result in the elimination or reduction of different via heights for vias for the top and bottom plates. Copper may be used as a material for the top and bottom plate in the integration scheme, which results in a higher frequency capability. Because the top plate is formed in a damascene process, after a planarizing step, a mask and etch process is not required to form the top plate, which solves alignment problems for the top plate. Thus, embodiments of the present invention solve several problems simultaneously.
[0014] The foregoing has outlined rather broadly the features and technical advantages of embodiments of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of embodiments of the invention will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of embodiments of the present invention. It should also be realized by those skilled hi the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
[0016] Figures 1, 2, and 3a show cross-sectional views of an embodiment of the present invention at various stages of fabrication, wherein cap layers are formed over the bottom capacitor plate and top capacitor plate, and wherein the top capacitor plate is formed in a damascene process;
[0017] Figure 3b shows an embodiment of the invention, wherein a trough for conductive line is formed in a subsequent insulating layer, making electrical contact of a conductive line directly to the top plate;
[0018] Figures 4 and 5 illustrate cross-sectional views of an embodiment of the invention at various stages of fabrication, wherein the bottom capacitor plate makes electrical contact to an underlying interconnect layer; and
[0019] Figure 6 shows and embodiment of the invention, wherein cap layers are formed on the bottom and top capacitor plates by recessing the plate conductive material, forming a catalytic activation layer over the conductive material, and selectively forming a conductive barrier layer within the conductive material recess.
[0020] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures arc drawn to clearly illustrate the relevant aspects of the preferred embodiments and arc not necessarily drawn to scale.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS [0021] The making and using of the presently preferred embodiments arc discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use die invention, and do not limit the scope of the invention. Only one MIM capacitor is shown in each figure, although many MIM capacitors, other components and/or conductive lines may be present within each layer.
[0022] With reference now to Figure 1, therein is shown a semiconductor wafer 100 having a substrate 110. The substrate 110 typically comprises a semiconductor material such as single- crystal silicon, and may include other conductive layers or other semiconductor elements such as transistors or diodes, as examples (not shown). The substrate 110 may alternatively comprise compound semiconductors such as GaAs, InP, Si Ge, SiC, as examples. The substrate 110 may also be referred to herein as a workpiece, and may comprise a silicon-on-insulator (SOI) substrate, for example. The substrate 110 or workpiece may include field oxide, active component regions, and/or shallow trench isolation or deep trench isolation regions, not shown. [0023] A first insulating layer 120 is deposited or formed over the substrate 110. The first insulating layer 120 may comprise silicon dioxide, and may also comprise a low-dielectric constant material, having a dielectric constant k of 3.6 or less, for example. The first insulating layer 120 is patterned and etched with a pattern for a bottom capacitor plate in a damascene process, for example. The patterned first insulating layer 120 is filled with a first conductive material 122, and die wafer is planarized, e.g., using a chemical-mechanical polish process, to remove excess first conductive material 122 from the surface of the firsl insulating layer 120, for example. Alternatively, the bottom capacitor plate may be formed using a non-damascene process, such as by depositing and patterning the first conductive material 122, followed by the deposition of the first insulating material 120, for example, and planarization of the first insulating material 120 to remove excess first insulating material 120 from the top surface of the first conductive material 122.
[0024] The first conductive material 122 preferably comprises a metal such as a copper alloy, such as Cu-Al, Cu-Mg, Cu-Sn, Cu-In, Cu-Zr, and Cu-Ag, as examples. The first conductive material 122 may alternatively comprise aluminum, tungsten, titanium or copper, or combinations thereof, as examples. The first conductive material 122 may comprise a thickness ranging from 500 to 1000 nm, and more preferably may comprise a thickness of about 700 nm, for example. The first conductive material 122 may alternatively comprise other conductive materials, for example. The first conductive material 122 may include a liner (not shown; see 216 in Figure 4).
[0025] In a preferred embodiment, the first conductive material 122 comprises copper, which has a low resistivity compared to other metals, for example. When copper or a copper alloy is used for the firsl conductive material 122, before the first conductive material 122 is deposited, a liner/copper seed layer combination (not shown in Figure 1; sec Figure 4) may be deposited, as described for the formation of a bottom capacitive plate in U.S. 6,451,664 Bl, entiύed "Method of Making MIM Capacitor with Self-Passivating Plates," which is incorporated herein by reference. When the first conductive material 122 comprises copper, preferably, a liner is deposited over the first dielectric layer 120. The liner may comprise Ta, TaN, W, WN, Ti, TiN deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD), as examples. A seed layer is then deposited over the liner, the seed layer comprising a copper alloy seed layer deposited by PVD or CVD, as example. Then, the first conductive material 122 is deposited over the liner/seed layer by electroplating, PVD or CVD, as examples. [0026] Referring again to Figure 1, in accordance with an embodiment of the present invention, a first cap layer 124 is then formed over the first conductive material 122. The first cap layer 124 may comprise a sclf-passivaling material as described in U.S. Patent No. 6,451,664 Bl , for example. In this embodiment, the first capacitor plate 122 is preferably formed in a damascene process. Forming the first capacitor plate comprises patterning the first insulating layer 120 witii a pattern for tire first capacitor plate, and depositing an alloy-contaming seed layer (not shown in Figure 1; see Figure 4) over the patterned first insulating layer 120. The first conductive material 122 is then deposited over the seed layer. When the wafer is annealed, the firsl cap layer 124 is selectively formed by the dopants, e.g., the alloy in the seed layer for the first conductive material passivates the top surface of the at least one first capacitor plate 122 and forms the first cap layer 124. The first cap layer 124 is formed by die segregation of the dopants from the seed layer or alternatively, (for example, if a seed layer is not used) a dopant or alloy in the bulk first conductive material 122, to the top surface of the first conductive material 122. Note that the segregation of dopants during the anneal process results in the first cap layer 124 being formed at all surfaces of the first conductive material 122, including the sides and bottom surface, as described in U.S. Patent No. 6,451,664 Bl; however, only the passivated surface at the top surface is of concern in the present invention and is thus shown in the figures. Thus, in this embodiment, the firsl cap layer 124 comprises a dopant-rich layer, formed by annealing. [0027] In accordance with another embodiment of the present invention, alternatively, the first cap layer 124 may comprise a selectively deposited material such as CoWP, CoP, CoWB, NiMoP, Re or Ru, as examples, as described in U.S. patent application entitled, "Method to Form Selective Cap Layers on Metal Features with Narrow Spaces," application Serial Number xx/xxx,xxx, which is filed herewith and which is incorporated herein by reference. In this embodiment, after the deposition of the firsl conductive material 122, the first conductive material 122 is recessed (not shown; see Figure 6), and then a catalytic activation layer is formed over the top surface of the firsl conductive material 122. A conductive barrier layer is then selectively deposited over the catalytic activation barrier. The first cap layer 124 in this embodiment comprises die catalytic activation barrier and the conductive barrier layer, to be described further herein with reference to Figure 6. [0028] The first cap layer 124 protects the first conductive material 122 top surface from any reactive agents or chemicals introduced during the subsequent deposition of the MEM dielectric material. Next, an optional dielectric cap layer may be deposited over the exposed portions of the first insulating layer 120 and first cap layer 124 (not shown in Figure 1; see Figure 4 at 226).
[0029] Referring again to Figure 1, next, in accordance with preferred embodiments of the present invention, a MIM capacitor top plate 134/136 and capacitor dielectric 132 are formed using a damascene process. A second insulating layer 130 is deposited over the exposed portions of the first insulating layer 120 and the first cap layer 124, (or over the optional dielectric cap layer, if one is used, not shown.) The second insulating layer 130 preferably comprises a conventional dielechic, such as an oxide, e.g., silicon dioxide, fluorinated silicate glass (FSG), a low dielectric constant material, such as SiLK™, Flare™, SiCOH, Coral™, Black Diamond™, or a porous low dielectric constant material, as examples.
[0030] Preferably, in accordance with one embodiment, the second insulating layer 130 is thin, comprising a thickness of 250 nm or less, and more preferably comprising a thickness of 50 nm or less, for example. In this embodiment, the thin second insulating layer 130 allows the formation of a thin MIM capacitor dielechic layer and thin MEM capacitor top plate, e.g., having a thickness of about 50 to 150 nm or less each. This is advantageous, because the depth difference of the contacting vias to the top plate 136 and the bottom plate 122 can be reduced. [0031] In another embodiment, the second insulating layer 130 is relatively thick, e.g., 300 to 1000 nm thick. In this embodiment, the MIM capacitor lop plate 136 may not require a via connection, advantageously, because the top plate 136 can be contacted in a trough etch of a
subsequent damascene interconnect level, for example, as shown in Figure 3b, to be described further herein.
[0032] Referring again to Figure 1, the second insulating layer 130 is patterned using photolithography and etch processes to create an opening 128 for the top plalc, shown in phantom in Figure 1. For example, a photoresist 129 may be deposited, exposed and developed, and the photoresist 129 may then be used to pallem the second insulating layer 130. A top surface of the first cap layer 124 is exposed after the patterning of the second insulating layer 130, for example. The etch process is preferably designed to stop on top of or within the first cap layer 124. Subsequently, the photoresist 129 is stripped.
[0033] Jjf the first cap layer 124 comprises a self-passivation layer, a portion of the self- passivation layer may be removed during the etch process, due to an over-etch, for example. In this case, the self-passivation layer (e.g., firsl cap layer 124) may be repaired by an optional anneal step, e.g., at approximately 400 degrees C or less, to induce another dopant segregation and copper self-passivation, for example.
[0034] In one embodiment of the present invention, the second insulating layer 130 comprises a photosensitive low-k material, such as mclhylsilscsquiazanc (MSZ), having a dielectric constant k of approximately 2.7, porous MSZ, having a k of less than 2.7, or another mechanically stable and photosensitive material, as examples. Advantageously, the etch and ship processes may not be required, if a photosensitive low-k material is used for the second insulatmg layer 130 material. The patterning of the second insulating layer 130 is preferably by UV lithography or electron beam irradiation, when the second insulating layer 130 comprises a photosensitive low-k material. Advantageously, Hie etch and strip may be omitted in this case, providing a cost savings. [0035] Referring now lo Figure 2, a capacitor dielectric material layer 132 is deposited over the patterned second insulating layer 130 and exposed first cap layer 124 top surface. The capacitor dielectric layer 132 typically comprises an insulator, such as silicon dioxide or silicon nitride, and alternatively, the capacitor dielectric layer 132 may comprise high dielectric constant materials, for example. The capacitor dielechic layer 132 may alternatively comprise other dielectric materials. The capacitor dielectric layer 132 may be about 540 Angstroms thick or less, for example, and may alternatively comprise 1000 Angstroms or less, for example. The capacitor dielectric layer 132 is preferably confoπnal and is evenly deposited over the top surface and sidewalls of the paltemed second insulating layer 130 and lop surface of Ihc exposed first cap layer 124, for example.
[0036] Because d e bottom capacitor plate 122 includes a first cap layer 124, die bottom plate 122 surface is passivatcd, allowing an increased selection of materials for the MIM capacitor dielectric layer 132. For example, the MIM capacitor dielectric material layer 132 may comprise an oxide, silicon nitride, or various high k materials, such as AI2O3, Ta2θ5, or BSTO, as examples. The MIM capacitor dielectric material layer 132 may be deposited using atomic-layer CVD, and may comprise a highly conformal and or low temperature dielectric material, for example. [0037] A second conductive material 136 is formed or deposited over the capacitor dielectric layer 132. The second conductive material 136 typically comprises a metal such as aluminum, tungsten, titanium, or copper, or combinations thereof. The second conductive material 136 may be 600 Angstroms thick, for example, and may alternatively comprise 1000 Angstroms or less, for example. The second conductive material 136 may alternatively comprise other conductive materials, for example. However, in accordance with a preferred embodiment of the present invention, the second conductive material 136 comprises copper or a copper alloy, such as Cu-Al, Cu-Mg, Cu-Sn, Cu-In, Cu-Zr, or Cu-Ag, as examples, due to the lower resistivity of copper and to achieve improved electrical results.
[0038] When copper or a copper alloy is used for the second conductive material 136, before the second conductive material 136 is deposited, a liner/copper seed layer 134 combination may be deposited, as described for the formation of a bottom capacitive plate in U.S. 6,451,664 Bl, for example. A liner is deposited over the capacitor dielectric layer 132. The liner may comprise Ta, TaN, W, WN, Ti, TiN deposited by PVD or CVD, as example. A seed layer is deposited over the liner, the seed layer comprising a copper alloy seed layer deposited by PVD or CVD, as an example. Then, the second conductive material 136 is deposited over the liner/seed layer 134 by electroplating, PVD or CVD, as examples.
[0039] Excess second conductive material 136, liner/seed layer 134, and capacitor dielectric layer 132 arc then removed from the top surface of the second insulating layer 130, using a CMP process, or RIE, as examples, as shown in Figure 3a. Advantageously, the lop plate material 134/136 does not need to be patterned using lithography. Rather, because the second insulating layer 130 has been paltemed before deposition of the top plate materials 134/136, the planarization of the second insulating layer 130 forms the top plalc 134/136 and also patterns the capacitor dielectric layer 132.
[0040] Next, shown in Figure 3a, in an optional step, a second cap layer 138 may be formed on the top surface of the second conductive material 136, as described for the first conductive material 122. The second cap layer 138 may be formed in a similar process as described for the first cap layer 124, for example. The second cap layer 138 may comprise a sclf-passivating material, such as a dopant-rich layer, formed by annealing, or alternatively, the second cap layer 138 may comprise a selectively deposited material such as CoWP, CoWB, CoP, NiMoP, Re or Ru, as examples. The second cap layer 138 protects the second conductive material 136 top surface from any reactive agents or chemicals introduced during die subsequent deposition of a dielectric material, to be described further herein.
[0041] The M capacitor 150 comprises bottom plate 122/124, capacitor dielectric 132, and top plate 134/136/138. Additional dielectric or insulating layers such as a third insulating layer 140 may then be deposited and a single or dual damascene process sequence may be continued, to pattern and fill the next via and wiring levels, for example. The third insulating layer 140 and second insulating layer 130 may be patterned and etched with first vias 142 to the MIMcap lop plate 132/134/136 and second vias 144 to the MIMcap bottom plate 122/124, for example, as shown in phantom in Figure 3a. If the second insulating layer 130 is thin, as in a preferred embodiment of the invention, then tiiere is less variation in the height of die first vias 142 and the second vias 144, advantageously.
[0042] In accordance with one embodiment of the present invention, shown in Figure 3b, the second insulating layer 130 is relatively thick, e.g., 300 to 1000 nm thick. In this embodiment, the MIM capacitor top plate 136 may not require a via connection, advantageously, because the top plate 136 can be contacted in a trough etch of a subsequent damascene interconnect level 140, for example, as shown. In this embodiment, the only part or the second insulating layer 130 that must be opened is the via 152 to the bottom plate 122/124. The second insulating layer 130 and third insulating layer 140 in this embodiment may be patterned in a dual damascene process (e.g., second insulating layer 130 is patterned, followed by the patterning of the third insulating layer 140, or vice versa). In a single fill process, conductive line 154 that abut the top metal plate 134/136/138, via 152, and conductive hne 156 diat is an extension of via 152 are formed at once. Excess conductive material is then removed from die top surface of the third insulating layer 140, e.g. in a planarization step. In this embodiment, only the MIM capacitor bottom plate 122/124 needs to be contacted by vias, but those may be patterned on the same metallization level as conductive lines 154 to the lop plate and other contacting vias e.g., for other elements of the semiconductor wafer (not shown) are formed, as shown in Figure 3b. This is advantageous because all vias to be patterned (e.g. for the MIM capacitor bottom plate) will have the same depth, which solves some of the etch slop problems found in prior art MIM capacitor fabrication.
[0043] Another embodiment of the present invention is shown in Figures 4 and 5. While not all preferred and alternative materials are described herein with reference to Figures 4, 5 and 6 to avoid repetition, corresponding numerals are used that were used to describe Figures 1 through 3. For example, element lxx in Figures 1-3 corresponds to and preferably comprises similar materials and thickness as clement 2xx in Figures 4 and 5, and element 3xx in Figure 6. [0044] In the embodiment shown in Figure 4, first metallization lines 212 arc formed beneath the bottom plate 216/222 before the bottom plate 216/222 is formed. Vias 214 are formed in the first insulating layer 220 to contact the bottom plate 216/222. The bottom plate 216/222 includes a liner 216, which may comprise a bi-laycr of a liner such as TaN, TiN, WN, Ta or combinations thereof, as examples, and a seed layer comprising a copper alloy, for example. First insulating layer 220 may include three separate dielectric layers (not shown), one for d e first metallization lines 212, one layer for vias 214, and anotiier layer for the MIM capacitor bottom plate 216/222, for example.
[0045] After the bottom plate 216/222 is formed, a first cap layer 224 is formed over the first conductive material 222. The first cap layer 224 may comprise a self-passivating layer
formed by annealing, or may alternatively comprise a selective deposition of CoWP, CoP or Ru, as examples.
[0046] After the first cap layer 224 is formed, a dielechic cap layer 226 is deposited or formed over the first cap layer 224 and exposed portions of the first insulating layer 220. The dielectric cap layer 226 preferably comprises SiN, SiC, SiCN or BloK™ or another dielectric material with diffusion barrier properties against metal ion or metal atom diffusion, as examples. Alternatively, the dielectric cap layer 226 may comprise other dielectric materials. The second insulating layer 230 is deposited over the dielectric cap layer 226, and the second insulating layer 230 and dielectric cap layer 226 are patterned with the top plate pattern 228, as shown in phantom in Figure 4.
[0047] A MIM capacitor dielechic layer 232 is deposited or formed over the patterned second insulating layer 230, and a lincr/sccd layer 234 is deposited over the capacitor dielectric layer 232. A second conductive material 236 is deposited over the lincr/sccd layer 234. The wafer is planarized to form the MIM capacitor top plate, which comprises liner/seed layer 232 and conductive material 236. A second cap layer 238 is selectively fonned over the MIMcap top plate 234/236. A third insulating layer 240 is deposited over the MIM capacitor 250, and the third insulating layer 240 is patterned witii vias 242 and second metallization lines 246, for example, in a dual damascene process. Note that the vias 242 contain the same height, solving the etch stop problems of prior art via formation due to the varying depths of the vias for contacting the top plate 234/236/238 and bottom plate 216/222/224. The patterned third insulating layer 240 is filled with a conductive material to form vias 242 and second metallization lines 246.
[0048] Note that because the firsl and second cap layers 124, 224, 138, and 238 preferably comprise a metal and are conductive, after the formation of the first and second cap layers, the capacitor plates are considered to also comprise the first and second cap layers. [0049] Another embodiment of the present invention is shown in Figure 6. In this embodiment, die cap layers for the bottom and top capacitor plates are formed as described in U.S. Patent Application Serial No. xx/xxx,xxx, filed herewith, entitled, "Method to Form Selective Cap Layers on Metal Features with Narrow Spaces," which is incorporated herein by reference. After the deposition and patterning of the firsl insulating layer 320, an optional liner 316 is deposited or formed over Ihc first insulating layer 320. The firsl conductive material 322 is deposited or formed and then recessed to a height slightly below, e.g., 20 nm or less, below the top surface of the first insulating layer 320. All or a portion of the finer 316 may be removed during the recessing of the first conductive material 322, depending on the method used to recess the first conductive material 322.
[0050] A catalytic activation layer 362 is then deposited over the top surface of the first conductive material 322. The catalytic activation layer 362 may comprise palladium (Pd) deposited in a layer of approximately one to three atoms thick, for example. [0051] A conductive barrier layer 364 is then deposited over the catalytic activation layer 362. The conductive bamer layer 364 preferably comprises a material such as CoWP, CoP, CoWB, NiMoP, Re or Ru, as examples. If any excess conductive barrier layer 364 resides on die top surface of the first insulating layer 320, it is preferably removed, resulting in the conductive barrier layer 364 having a top surface that is co-planar with the top surface of the first insulating layer 320. In this embodiment, die cap layer for Hie bottom capacitor plate comprises catalytic
activation layer 362 and conductive bamer layer 364. The MIM capacitor 350 is then fabricated as described herein for the other embodiments.
[0052] After the deposition of the second conductive material 336, again, as described for the bottom plate 316/322/362/364, the second conductive material 336 is recessed below the lop surface of the second insulating layer 330, e.g., 20 nm or less, below the top surface of the second insulating layer 330. A portion of or all of the optional liner 334 may be removed during the recessing of the second insulating layer 330.
[0053] A catalytic activation layer 358 comprising, for example, one lo three atom layers of Pd, is then deposited over the top surface of the second conductive material 322. A conductive barrier layer 360 comprises a material such as CoWP, CoP, CoWB, NiMoP, Re or Ru, as examples, is then deposited over the catalytic activation layer 358. In an optional step, excess conductive barrier layer 360 on the lop surface of the second insulating layer 330 is removed, resulting in the conductive barrier layer 360 having a top surface that is co-planar with the lop surface of die second insulating layer 330. In this embodiment, the cap layer for the top capacitor plate comprises catalytic activation layer 358 and conductive barrier layer 360. The MIM capacitor 350 includes bottom plate 316/322/362/364, capacitor dielectric 332, and top plate 334/336/358/360.
[0054] Embodiments of the present invention provided a simplified integration scheme for forming a MIM capacitor 150/250/350, a reduction in lidiography steps, and reduced cost. The novel integration schemes for fabricating a MIM capacitor described herein solve several problems simultaneously. First, embodiments of the present invention provide for increased area capacitance, because of a wider range of MIM capacitor dielectric materials that may be used. The choice of die MIM capacitor dielechic is not limited by copper diffusion or by poor adhesion between the copper material and MIM capacitor dielectric material, or by affecting the copper during the MIM dielechic deposition, because of the barrier provided by the first cap layers 124, 224 and 362/364 and second cap layers 138, 238 and 358/360. Problems with the via etch process due to topography differences using an etch stop may be solved, resulting in the reduction of (Figures 1, 2 and 3a) or elimination of (Figures 3b, 4, 5 and 6) different via heights between the vias for the top and bottom plates. Copper may be used in the integration scheme for the top capacitor plate conductive material 122, 222 and 322 and bottom capacitor plate conductive material 136, 236 and 336, which results in a higher frequency capability of the MIM capacitor 150/250/350 and ix MIM capacitor 150/250/350 having a higher Q factor. Because the top plate is formed in a damascene process, after a CMP step, a mask and etch process is not required to form the top plate, which solves alignment problems for the top plate. [0055] Although embodiments of the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from die spirit and scope of the invention as defined by the appended claims. For example, it will be readily understood by those skilled in the art that the materials and process steps may be varied while remaining within the scope of the present invention. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, diat perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to die present invention. Accordingly, the appended claims are intended lo include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

WHAT IS CLAIMED IS:
1. A method of fabricating a melal-insulator-metal (MIM) capacitor, the method comprising: providing a semiconductor wafer; forming at least one first capacitor plate over the wafer; forming a firsl insulating layer over the wafer, wherein a top surface of the al least one first capacitor plate is exposed; selectively forming a first cap layer over die at least one first capacitor plate top surface; forming a second insulating layer over the firsl insulating layer and the first cap layer, the second insulating layer having a lop surface; patterning the second insulating layer witii at least one second capacitor plate pattern; depositing a capacitor dielectric layer over the second insulating layer; depositing a second capacitor plate material over the capacitor dielectric layer; and planarizing the wafer to remove the second capacitor plate material and capacitor dielechic layer from over the second insulating layer top surface and fonri at leasl one second capacitor plalc within the patterned second insulating layer, wherein the at least one second capacitor plate, capacitor dielectric layer and at least one first capacitor plate form a MIM capacitor.
2. The method according to Claim 1, further comprising depositing a dielectric cap layer over the first cap layer and first insulating layer, before forming the second insulating layer, wherein patterning die second insulating layer includes patterning the dielectric cap layer with the al least one second capacitor plalc pattern.
3. The method according lo Claim 2, wherein depositing the dielectric cap layer comprises depositing SiN, SiC, SiCN or BloK™, or a dielectric material with diffusion barrier properties againsl metal ion or metal atom diffusion.
4. The mediod according to Claim 1, further comprising selectively forming a second cap layer over Uie second capacitor plate.
5. The method according to Claim 4, wherein depositing the second capacitor plate material comprises depositing an alloy-containing seed layer over die patterned second insulatmg layer, wherein selectively fonning the second cap layer comprises passivating the top surface of the second capacitor plate material by annealing the semiconductor wafer.
6. The method according lo Claim 5, further comprising depositing a third insulating layer over at least the second insulating layer, and patterning the third insulating layer to Torni a via pattern abutting the second cap layer, wherein a portion of the second cap layer is removed when patterning die third insulating layer, further comprising annealing the semiconductor wafer to repair the removed second cap layer, after palteming the third insulating layer.
7. The mediod according to Claim 4, wherein selectively forming die second cap layer comprises selectively depositing a metallic diffusion bamer.
8. The method according to Claim 7, wherein depositing the metallic diffusion hairier comprises depositing CoWP, CoWB, CoP, NiMoP, Re or Ru.
9. The method according to Claim 7, further comprising: recessing the second capacitor plate material below a top surface of the second insulating layer and forming a catalytic activation layer over a lop surface of the recessed second capacitor plate material, before selectively depositing a metallic diffusion barrier.
10. The method according to Claim 9, wherein forming the catalytic activation layer comprises depositing Pd.
11. The method according to Claim 1, further comprising depositing a third insulating layer over the at least one second capacitor plate, and forming a first conductive line making electrical connection to the second capacitor plate within the third insulating layer.
12. The method according to Claim 11 , further comprising forming via within die second insulating layer making electrical connection to the first capacitor plate, and forming a second conductive hne within the tiiird insulating layer making electrical connection to the via.
13. The method according to Claim 1, wherein forming at least one first capacitor plate comprises patterning the first insulating layer with a pattern for the first capacitor plate, and depositing an alloy-containing seed layer over the patterned first insulating layer, wherein selectively forming a first cap layer comprises passivating the top surface of the al least one first capacitor plalc by annealing the semiconductor wafer.
14. The method according to Claim 13, wherein a portion of the first cap layer is removed when patterning the second insulating layer, further comprising annealing the semiconductor wafer to repair die removed first cap layer, after patterning the second insulating layer.
15. The method according to Claim 1, wherein selectively forming a first cap layer comprises selectively depositing a metallic diffusion baiiier.
16. The method according to Claim 15, wherein depositing the metallic diffusion barrier comprises depositing CoWP, CoWB, CoP, NiMoP, Re or Ru.
17. The method according to Claim 15, further comprising: recessing the first capacitor plate material below a top surface of the first insulating layer and forming a catalytic activation layer over a lop surface of the recessed first capacitor plate material, before selectively depositing a metallic diffusion barrier.
18. The method according to Claim 17, wherein forming the catalytic activation layer comprises depositing Pd.
19. The mediod according to Claim 1, wherein forming die second insulating layer comprises forming a second insulating layer comprising a thickness of 250 nm or less.
20. The method according to Claim 19, wherein forming the second insulating layer comprises depositing oxide, silicon dioxide, fluorinated silicate glass (FSG), a low dielectric constant material, or a porous low dielechic constant material.
21. The method according to Claim 1, wherein forming die second insulating layer comprises depositing a photosensitive low-k material.
22. The method according to Claim 21, wherein patterning the second insulating layer comprises utilizing UV iography or electron beam irradiation.
23. The method according to Claim 23 , wherein depositing the photosensitive low-k material comprises depositing as mefliylsilsesquiazane (MSZ).
24. The method according to Claim 1 , wherein forming at least one first capacitor plate comprises forming at least one first capacitor plate comprising copper, wherein depositing a second capacitor plate material comprises depositing copper.
25. Tlie method according to Claim 24, wherein forming at least one first capacitor plate comprises forming at least one first capacitor plate comprising Cu-Al, Cu-Mg, Cu-Sn, Cu-In, Cu-Zr, or Cu-Ag, wherein depositing a second capacitor plate material comprises depositing Cu- Al, Cu-Mg, Cu-Sn, Cu-In, Cu-Zr, or Cu-Ag.
26. A mctal-insulator-metal (MIM) capacitor, comprising: a semiconductor wafer; a first insulating material disposed over the wafer; a firsl capacitor plate disposed over the semiconductor wafer within the firsl insulating material; a first cap layer disposed over the first capacitor plate; a second insulating layer disposed over the first insulating layer and first cap layer; a capacitor dielectric disposed over and abutting at least a portion of the first cap layer witiiin die second insulating layer; a second capacitor plate disposed over and abutting the capacitor dielectric within the second insulating layer; and a second cap layer disposed over the second capacitor plate.
27. The MIM capacitor according to Claim 26, wherein the first capacitor plalc and second capacitor plate comprise copper.
28. The MIM capacitor according to Claim 26, further comprising a dielectric cap layer disposed over the first insulating material.
29. Tlie MIM capacitor according to Claim 28, wherein the dielectric cap layer comprises SIN, SiC, SiCN or BloKI M, or a dielectric material with diffusion banner properties against metal ion or metal atom diffusion.
30. The MEVI capacitor according to Claim 26, wherein the first cap layer and second cap layer comprise a sclf-passivated layer formed by annealing.
31. The MEM capacitor according to Claim 26, wherein the first cap layer and second cap layer comprise selectively-deposited metallic diffusion banners.
32. The MIM capacitor according to Claim 31 , wherein the first cap layer and second cap layer comprise CoWP, CoWB, CoP, NiMoP, Re or Ru.
33. Tlie MIM capacitor according to Claim 26, further comprising: a third insulating layer disposed over the second cap layer and the second insulating layer; a first conductive line formed in the third insulating layer abutting the second cap layer; a via formed in the second insulating layer abutting the first cap layer; and a second conductive hne formed in the third insulating layer abutting the via.
PCT/EP2004/050716 2003-05-05 2004-05-05 Method for forming the top plate of a mim capacitor with a single mask in a copper dual damascene integration scheme WO2004100232A1 (en)

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US6949442B2 (en) 2005-09-27
US7843035B2 (en) 2010-11-30

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