WO2004109525A3 - Memory module architecture daisy chain topology detects and reports presence of outer memory module to inner module - Google Patents

Memory module architecture daisy chain topology detects and reports presence of outer memory module to inner module Download PDF

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Publication number
WO2004109525A3
WO2004109525A3 PCT/US2004/015978 US2004015978W WO2004109525A3 WO 2004109525 A3 WO2004109525 A3 WO 2004109525A3 US 2004015978 W US2004015978 W US 2004015978W WO 2004109525 A3 WO2004109525 A3 WO 2004109525A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory module
module
daisy chain
architecture
chain topology
Prior art date
Application number
PCT/US2004/015978
Other languages
French (fr)
Other versions
WO2004109525A2 (en
Inventor
Pete Vogt
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to EP04752906A priority Critical patent/EP1629392B1/en
Priority to JP2006514912A priority patent/JP4210300B2/en
Priority to DE602004008067T priority patent/DE602004008067T2/en
Publication of WO2004109525A2 publication Critical patent/WO2004109525A2/en
Publication of WO2004109525A3 publication Critical patent/WO2004109525A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures

Abstract

A memory agent may include a first port and a second port, wherein the memory agent is capable of detecting the presence of another memory agent on the second port. A method may include performing a presence detect operation on a first port of a memory agent, and reporting the results of the presence detect operation through a second port of the memory agent.
PCT/US2004/015978 2003-06-03 2004-05-20 Memory module architecture daisy chain topology detects and reports presence of outer memory module to inner module WO2004109525A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP04752906A EP1629392B1 (en) 2003-06-03 2004-05-20 Memory module architecture daisy chain topology detects and reports presence of outer memory module to inner module
JP2006514912A JP4210300B2 (en) 2003-06-03 2004-05-20 Memory channels that can be added / removed while the power is on
DE602004008067T DE602004008067T2 (en) 2003-06-03 2004-05-20 MEMORY MODULE ARCHITECTURE REIGENT TOPOLOGY, DETECTIONS AND MESSAGES, PRESENCE OF OUTER MEMORY MODULE TO INNER MODULE

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/454,399 2003-06-03
US10/454,399 US7194581B2 (en) 2003-06-03 2003-06-03 Memory channel with hot add/remove

Publications (2)

Publication Number Publication Date
WO2004109525A2 WO2004109525A2 (en) 2004-12-16
WO2004109525A3 true WO2004109525A3 (en) 2005-01-27

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/015978 WO2004109525A2 (en) 2003-06-03 2004-05-20 Memory module architecture daisy chain topology detects and reports presence of outer memory module to inner module

Country Status (9)

Country Link
US (1) US7194581B2 (en)
EP (1) EP1629392B1 (en)
JP (1) JP4210300B2 (en)
KR (1) KR100806445B1 (en)
CN (1) CN100483380C (en)
AT (1) ATE369589T1 (en)
DE (1) DE602004008067T2 (en)
TW (1) TW200502732A (en)
WO (1) WO2004109525A2 (en)

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Also Published As

Publication number Publication date
KR100806445B1 (en) 2008-02-21
WO2004109525A2 (en) 2004-12-16
CN1799040A (en) 2006-07-05
US20040250024A1 (en) 2004-12-09
KR20060023983A (en) 2006-03-15
JP2006526846A (en) 2006-11-24
JP4210300B2 (en) 2009-01-14
DE602004008067T2 (en) 2007-11-22
EP1629392B1 (en) 2007-08-08
CN100483380C (en) 2009-04-29
ATE369589T1 (en) 2007-08-15
TW200502732A (en) 2005-01-16
DE602004008067D1 (en) 2007-09-20
EP1629392A2 (en) 2006-03-01
US7194581B2 (en) 2007-03-20

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