WO2004111659A2 - Methods and apparatus for packaging integrated circuit devices - Google Patents

Methods and apparatus for packaging integrated circuit devices Download PDF

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Publication number
WO2004111659A2
WO2004111659A2 PCT/IL2004/000521 IL2004000521W WO2004111659A2 WO 2004111659 A2 WO2004111659 A2 WO 2004111659A2 IL 2004000521 W IL2004000521 W IL 2004000521W WO 2004111659 A2 WO2004111659 A2 WO 2004111659A2
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WO
WIPO (PCT)
Prior art keywords
integrated circuit
packaging layer
chip scale
scale packaging
forming
Prior art date
Application number
PCT/IL2004/000521
Other languages
French (fr)
Other versions
WO2004111659A3 (en
Inventor
Gil Zilber
Reuven Katraro
Julia Aksenton
Vage Oganesian
Original Assignee
Shellcase Ltd.
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Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=33511504&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO2004111659(A2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Shellcase Ltd. filed Critical Shellcase Ltd.
Priority to KR1020057024161A priority Critical patent/KR101173075B1/en
Publication of WO2004111659A2 publication Critical patent/WO2004111659A2/en
Publication of WO2004111659A3 publication Critical patent/WO2004111659A3/en

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Definitions

  • the present invention relates to methods and apparatus for producing integrated circuit devices and to integrated circuit devices produced thereby and more particularly to an integrally packaged die.
  • Packaging An essential step in the manufacture of all integrated circuit devices is known as "packaging" and involves mechanical and environmental protection of a silicon chip which is at the heart of the integrated circuit as well as electrical interconnection between predetermined locations on the silicon chip and external electrical terminals.
  • Wire bonding employs heat and ultrasonic energy to weld gold bonding wires between bond pads on the chip and contacts on the package.
  • Tape automatic bonding employs a copper foil tape instead of bonding wire.
  • the copper foil tape is configured for each specific die and package combination and includes a pattern of copper traces suited thereto.
  • the individual leads may be connected individually or as a group to the various bond pads on the chip.
  • Flip chips are integrated circuit dies which have solder bumps formed on top of the bonding pads, thus allowing the die to be "flipped" circuit side down and directly soldered to a substrate. Wire bonds are not required and considerable savings in package spacing may be realized.
  • Both wire bonding and TAB bonding are prone to bad bond formation and subject the die to relatively high temperatures and mechanical pressures.
  • Both wire bond and TAB technologies are problematic from a package size viewpoint, producing integrated circuit devices having a die-to-package area ratio ranging from about 10% to 60%.
  • the flip-chip does not provide packaging but rather only interconnection. The interconnection encounters problems of uniformity in the solder bumps as well as in thermal expansion mismatching, which limits available substrates to silicon or to materials which have thermal expansion characteristics similar to those of silicon.
  • chip scale packaging to include any packaging process with a ratio of packaging, to die less than or equal to 1.2:1. Additionally, the packaging layer conventionally provides protection to the encased semiconductor or integrated circuit.
  • an integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.
  • an integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over at least one edge surface of the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.
  • an integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the second generally planar, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.
  • an integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one edge surface of the crystalline substrate, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.
  • the at least one chip scale packaging layer is formed of a crystalline material.
  • the at least one chip scale packaging layer is formed of at least one of metal, plastic, thermoplastic, thermosetting and ceramic.
  • the at least one chip scale packaging layer is formed of silicon.
  • the crystalline substrate and the at least one chip scale packaging layer are both formed of silicon.
  • the integrally packaged integrated circuit device also includes an insulation layer formed over the at least one chip scale packaging layer and directly underlying the at least one electrical contact.
  • the insulation layer includes at least one of a passivation layer and a dielectric layer.
  • the insulation layer includes at least one of epoxy, silicon oxide, solder mask, silicon nitride, silicon oxinitride, polyimide, BCBTM, parylene, polynaphthalenes, fluorocarbons and accrylates.
  • the integrally packaged integrated circuit device also includes at least one gap formed between the crystalline substrate and the at least one packaging layer. Additionally, the gap is formed as a recess in the at least one packaging layer.
  • the integrally packaged integrated circuit device also includes at least one gap formed in the crystalline substrate.
  • the integrally packaged integrated circuit device also includes at least one gap formed in the crystalline substrate and at least one chip scale packaging layer formed underlying the crystalline substrate and sealing the gap formed in the crystalline substrate.
  • a method of producing integrally packaged integrated circuit devices including providing a plurality of integrated circuit dies formed on a wafer, each of the dies having first and second generally planar surfaces, and an active surface and at least one pad formed on the first generally planar surface, the active surface including circuitry, forming at least one chip scale packaging layer over the active surface, forming at least one electrical contact over the at least one chip scale packaging layer, the at least one electrical contact being connected to the circuitry by the at least one pad and subsequently separating the wafer into a plurality of packaged integrated circuit devices.
  • a method of producing integrally packaged integrated circuit devices including providing a plurality of integrated circuit dies formed on a wafer, each of the dies having first and second generally planar surfaces, and an active surface and at least one pad formed on the first generally planar surface, the active surface including circuitry, forming at least one chip scale packaging layer over the active surface, forming at least one electrical contact over at least one edge surface of the at least one chip scale packaging layer, the at least one electrical contact being connected to the circuitry by the at least one pad and subsequently separating the wafer into a plurality of packaged integrated circuit devices.
  • a method of producing integrally packaged integrated circuit devices including providing a plurality of integrated circuit dies formed on a wafer, each of the dies having first and second generally planar surfaces and edge surfaces, and an active surface and at least one pad formed on the first generally planar surface, the active surface including circuitry, forming at least one chip scale packaging layer over the active surface, forming at least one electrical contact over the second generally planar surface, the at least one electrical contact being connected to the circuitry by the at least one pad and subsequently separating the wafer into a plurality of packaged integrated circuit devices.
  • a method of producing integrally packaged integrated circuit devices including providing a plurality of integrated circuit dies formed on a wafer, each of the dies having first and second generally planar surfaces and edge surfaces, and an active surface and at least one pad formed on the first generally planar surface, the active surface including circuitry, forming at least one chip scale packaging layer over the active surface, forming at least one electrical contact over the edge surfaces of the integrated circuit dies, the at least one electrical contact being connected to the circuitry by the at least one pad and subsequently separating the wafer into a plurality of packaged integrated circuit devices.
  • the forming at least one chip scale packaging layer includes forming at least one crystalline material chip scale packaging layer.
  • the forming at least one chip scale packaging layer includes forming a chip scale packaging layer of at least one of metal, plastic, thermoplastic, thermosetting and ceramic.
  • the forming at least one chip scale packaging layer includes forming at least one silicon chip scale packaging layer.
  • the forming at least one chip scale packaging layer includes forming at least one silicon chip scale packaging layer and the providing a plurality of integrated circuit dies formed on a wafer includes providing a plurality of integrated circuit dies formed on a silicon wafer.
  • the method also includes forming an insulation layer over the at least one chip scale packaging layer and wherein the forming at least one electrical contact includes forming the at least one electrical contact directly over the insulation layer.
  • the method also includes forming at least one gap between the plurality of dies and the at least one packaging layer. Additionally, the forming at least one gap includes forming a recess in the at least one packaging layer. Alternatively, the forming at least one gap includes forming at least one gap in the plurality of dies. Alternatively, the method also includes forming at least one gap in the plurality of dies.
  • the method also includes forming at least one gap in. the plurality of dies and forming at least one chip scale packaging layer over the second generally planar surface, thereby sealing the gap.
  • the forming at least one chip scale packaging layer includes bonding the chip scale packaging layer to the plurality of dies using a bonding layer.
  • the bonding layer includes at least one of an adhesive, intermetallic bonding and anodic bonding.
  • the forming at least one chip scale packaging layer also includes thinning the packaging layer from an original thickness to a decreased thickness.
  • the thinning includes at least one of grinding, lapping and etching.
  • the decreased thickness is approximately between 50 - 250 microns.
  • the method also includes thinning the plurality of dies from an original thickness to a decreased thickness, subsequent to the forming at least one chip scale packaging layer and prior to the separating.
  • the thinning includes at least one of grinding, lapping and etching.
  • the decreased thickness is approximately between 10 - 150 microns.
  • the thinning includes thinning the second planar surface.
  • the method also includes forming at least one first gap in the plurality of dies and forming at least one second gap in the at least one chip scale packaging layer, the second gap communicating with the first gap. Additionally, the method also includes forming at least one chip scale packaging layer over the second generally planar surface, thereby sealing the first gap.
  • the at least one chip scale packaging layer over the second generally planar surface includes at least one of silicon, glass, metal, plastic, thermoplastic, thermosetting and ceramic.
  • the forming at least one chip scale packaging layer over the second generally planar surface includes bonding the chip scale packaging layer over the second generally planar surface to the plurality of dies using a bonding layer.
  • the bonding layer includes at least one of an adhesive, intermetallic bonding and anodic bonding.
  • the forming at least one chip scale packaging layer over the second generally planar surface also includes thinning the packaging layer from an original thickness to a decreased thickness.
  • the thinning includes at least one of grinding, lapping and etching.
  • the decreased thickness is approximately between 50 - 250 microns.
  • Figs. IA and IB are, respectively, a simplified pictorial illustration and a simplified sectional illustration of an integrally packaged integrated circuit device constructed and operative in accordance with a preferred embodiment of the present invention, the sectional illustration being taken along lines IB - IB in Fig. IA;
  • Figs. 1C and ID are, respectively, a simplified pictorial illustration and a simplified sectional illustration of an integrally packaged integrated circuit device constructed and operative in accordance with another preferred embodiment of the present invention, the sectional illustration being taken along lines ID - ID in Fig. 1C;
  • FIGs. 2A and 2B are simplified pictorial illustrations of the attachment of a protective insulating cover plate to a wafer containing a plurality of integrated circuit dies in accordance with a preferred embodiment of the present invention
  • Figs. 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 31 and 3J are sectional illustrations of various stages in the manufacture of integrally packaged integrated circuit devices in accordance with a preferred embodiment of the present invention
  • Fig. 4 is a partially cut away detailed pictorial illustration of an integrally packaged integrated circuit device produced from the wafer of Fig. 3J;
  • FIG. 5 and 6 together provide a simplified block diagram illustration of apparatus for carrying out the method of the present invention.
  • Figs. 7A, 7B and 7C are simplified pictorial illustrations of three alternative embodiments of an integrally packaged integrated circuit device constructed and operative in accordance with yet another preferred embodiment of the present invention.
  • Figs. 8A and 8B are simplified pictorial illustrations of the attachment of a protective insulating cover plate to a wafer containing a plurality of integrated circuit dies in accordance with another preferred embodiment of the present invention;
  • Figs. 9A, 9B, 9C, 9D, 9E, 9F, 9G, 9H, 91 and 9J are sectional illustrations of various stages in the manufacture of integrally packaged integrated circuit devices in accordance with another preferred embodiment of the present invention.
  • Fig. 10 is a partially cut away detailed pictorial illustration of an integrally packaged integrated circuit device produced from the wafer of Fig. 9 J;
  • FIG. 11 and 12 together provide a simplified block diagram illustration of apparatus for carrying out the method of the present invention
  • Figs. 13 A and 13B are, respectively, a simplified pictorial illustration and a simplified sectional illustration of an integrally packaged integrated circuit device constructed and operative in accordance with a preferred embodiment of the present invention, the sectional illustration being taken along lines XlULB - XIIIB in Fig. IA;
  • Figs. 13C and 13D are, respectively, a simplified pictorial illustration and a simplified sectional illustration of an integrally packaged integrated circuit device constructed and operative in accordance with another preferred embodiment of the present invention, the sectional illustration being taken along lines XiIlD - XIHD in
  • Figs. 14A and 14B are simplified pictorial illustrations of the attachment of a protective insulating cover plate to a wafer containing a plurality of integrated circuit dies in accordance with a preferred embodiment of the present invention
  • Figs. 15A, 15B, 15C, 15D, 15E, 15F, 15G, 15H, 151 and 15J are sectional illustrations of various stages in the manufacture of integrally packaged integrated circuit devices in accordance with a preferred embodiment of the present invention
  • Fig. 16 is a partially cut away detailed pictorial illustration of an integrally packaged integrated circuit device produced from the wafer of Fig. 15 J;
  • FIG. 17 and 18 together provide a simplified block diagram illustration of apparatus for carrying out the method of the present invention.
  • Figs. 19A and 19B are simplified pictorial illustrations of three alternative embodiments of an integrally packaged integrated circuit device constructed and operative in accordance with yet another preferred embodiment of the present invention.
  • Figs. 2OA and 2OB are simplified pictorial illustrations of the attachment of a protective insulating cover plate to a wafer containing a plurality of integrated circuit dies in accordance with another preferred embodiment of the present invention;
  • Figs. 21A, 21B, 21C, 21D, 21E, 21F, 21G, 21H, 211 and 21J are sectional illustrations of various stages in the manufacture of integrally packaged integrated circuit devices in accordance with another preferred embodiment of the present invention
  • FIg. 22 is a partially cut away detailed pictorial illustration of an integrally packaged integrated circuit device produced from the wafer of Fig. 2 IJ;
  • FIG. 23 and 24 together provide a simplified block diagram illustration of apparatus for carrying out the method of the present invention.
  • the integrated circuit device includes a relatively thin and compact, environmentally protected and mechanically strengthened, integrated circuit package 10, having a multiplicity of electrical conductors 12.
  • conductors 12 are electrically connected to pads 16, and are preferably formed directly over an insulation layer 18 overlying at least one chip scale packaging layer 20 overlying an integrated circuit die
  • insulation layer 18 may be partially or entirely obviated. Insulation layer 18 may be any suitable insulation layer, such as a dielectric layer or a passivation layer. Pads 16 are connected to circuitry on the active surface 24.
  • the chip scale packaging layer 20 is formed of a crystalline material, most preferably silicon. As a further alternative, the chip scale packaging layer
  • 20 is formed of at least one of metal, plastic, thermoplastic, thermosetting and ceramic.
  • conductors 12 extend over edge surfaces 25 onto a planar surface 26 of the insulation layer 18. This contact arrangement permits flat surface mounting of package 10 onto a circuit board.
  • integrated circuit package 10 may also include contact bumps, such as solder bumps 28 formed on electrical conductors 12, at apertures formed in a solder mask 30 formed over insulation layer 18 and packaging layer 20.
  • the conductors 12 do not extend beyond edge surfaces 25 onto planar surface 26 or extend onto planar surface 26 only to a limited extent, thereby defining peripheral contacts.
  • Figs. 2A and 2B are simplified pictorial illustrations of the attachment of a protective insulating chip scale packaging layer plate to a wafer, preferably formed of silicon and containing a plurality of integrated circuit dies in accordance with the present invention.
  • a silicon wafer 40 has a plurality of finished dies 22 formed thereon by conventional techniques, and is bonded at active surfaces 24 of dies 22 onto a chip scale packaging layer plate 42.
  • wafer 40 having a plurality of finished dies 22 formed thereon by conventional techniques, is bonded at active surfaces 24 to plate 42 by bonding layer
  • Bonding layer 32 may include one or more of an adhesive such as epoxy or polyurethane, intermetallic bonding such as solder and anodic bonding. Alternatively, bonding layer 32 may include any other suitable bonding material. As seen in Fig. 3A, electrical pads 16 are formed on the active surfaces 24 defined on wafer 40.
  • chip scale packaging layer plate 42 is preferably thinned from an original thickness Ll, typically in the range of 400 to 1000 microns, to a decreased thickness L2, typically in the range of 10-250 microns, as shown in Fig. 3B. Thinning of chip scale packaging layer plate 42 may be achieved by grinding, lapping, etching or any other suitable method. Similarly, the silicon wafer 40 is preferably thinned from an original thickness Ll, typically in the range of 400 to 1000 microns, to a decreased thickness L2, typically in the range of 10-250 microns, as shown in Fig. 3B. Thinning of chip scale packaging layer plate 42 may be achieved by grinding, lapping, etching or any other suitable method. Similarly, the silicon wafer 40 is preferably thinned from an original thickness Ll, typically in the range of 400 to 1000 microns, to a decreased thickness L2, typically in the range of 10-250 microns, as shown in Fig. 3B. Thinning of chip scale packaging layer plate 42 may be achieved by grinding, lapping,
  • wafer 40 may be thinned to a decreased thickness approximating 0 microns, leaving only the circuitry and pads on the active surface 24 bonded to the packaging layer plate 42. Thinning of wafer 40 may be achieved by grinding, lapping, etching or any other suitable method. As seen in Fig. 3B, wafer 40 is preferably thinned on a planar surface opposite active surface 24. This reduction in wafer thickness is enabled by the additional mechanical strength provided by the bonding thereto of plate 42. The reduction in thickness of the silicon wafer need not necessarily take place at this stage, but may take place at any suitable later stage.
  • the chip scale packaging layer plate 42 preferably formed of silicon, is etched, using a photolithography process, along its top surface 46 along predetermined dice lines that separate the individual dies. Etched channels 52 are thus produced, which extend entirely through the thickness of the chip scale packaging layer plate 42, typically in the range of 10-250 microns, and through the bonding layer 32 as well as any other layers, such as insulation layers which may be present, thereby exposing pads 16.
  • the etched packaged wafer including a plurality of chip scale packaging layers 20 and a corresponding plurality of integrated circuit dies 22 bonded thereto, is shown in Fig. 3C.
  • etching typically is achieved by a dry etching process using SF O , C4F8 or other suitable dry etching gasses.
  • the etching takes place in conventional silicon etching solution, such as a combination of 2.5% hydrofluoric acid,
  • the result of the silicon etching is a plurality of chip scale packaging layers 20, each of which includes silicon of thickness in the range of 10-250 microns.
  • etched channels 52 are preferably coated with a dielectric material, such as epoxy, silicon oxide, solder mask, or any other suitable dielectric material, such as silicon nitride, silicon oxinitride, polyimide, BCBTM, parylene, polynaphthalenes, fluorocarbons or accrylates.
  • the resulting insulation layer 18 is preferably formed by spin coating, or may be formed by any suitable method, such as spray coating, curtain coating, liquid phase deposition, physical vapor deposition, chemical vapor deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, rapid thermal chemical vapor deposition or atmospheric pressure chemical vapor deposition. Following the formation of insulation layer 18, as seen in Fig.
  • an opening 56 is formed in the insulation layer 18 between each pair of adjacent dies, by any suitable method. Openings 56 extend through insulation layer 18, thereby exposing pads 16.
  • Fig. 3F shows the formation of a conductive layer 58, which covers insulation layer 18 and extends into openings 56.
  • Conductive layer 58 is preferably formed of aluminum, or may be formed of any suitable conductive material or combination of materials, such as aluminum, copper, titanium, titanium tungsten, or chrome.
  • Fig. 3G shows patterning of the conductive layer 58, typically by conventional photolithographic techniques, to define the plurality of conductors 12 which electrically contact edges of one or more pads 16 on dies 22 and are appropriately plated.
  • Fig. 3H shows the wafer being coated with a protective material, preferably solder mask 30 or other protective material such as parylene, BCBTM, or polyamide, which is patterned to define apertures 60 therein, communicating with conductors 12.
  • a protective material preferably solder mask 30 or other protective material such as parylene, BCBTM, or polyamide, which is patterned to define apertures 60 therein, communicating with conductors 12.
  • Fig. 31 shows the formation of contact bumps, such as solder bumps 28, at apertures 60 in electrical contact with conductors 12.
  • the wafer is then separated, as shown in Fig. 3 J, along lines 64, to provide individual integrated circuit packages, each including a single integrated circuit die 22 and being similar to integrated circuit package 10 of Figs. IA and IB.
  • Fig. 4 is a partially cut away, detailed, pictorial illustration of an integrally packaged integrated circuit device 10 produced from the wafer of Fig. 3 J.
  • the integrated circuit package 10 includes chip scale packaging layer 20, joined by bonding layer 32 to die 22. Surfaces of pads 16 are in electrical contact with conductors 12, which are directly formed over dielectric insulation layer 18, as described hereinabove.
  • FIG. 5 and 6 illustrate apparatus for producing integrated circuit devices in accordance with a preferred embodiment of the present invention.
  • a conventional wafer fabrication facility 180 provides wafers 40.
  • chip scale packaging layer plates 42 such as silicon substrates
  • bonding apparatus 182 preferably having facilities for rotation of the wafer 40, the chip scale packaging layer plates 42 and the bonding layer 32 so as to obtain even distribution of the bonding layer 32.
  • the chip scale packaging layer plate 42 and optionally the wafer 40 bonded thereto are thinned as by grinding apparatus 183, such as model BFG 841, which is commercially available from Disco Ltd. of Japan.
  • the chip scale packaging layer plate 42 is then etched in a pattern preferably defined by using conventional photolithography techniques, such as by using conventional spin-coated photoresist as indicated by reference numeral 184.
  • a suitable photoresist is commercially available from Hoechst, under the brand designation AZ 4562.
  • the photoresist is preferably mask exposed by a suitable UV exposure system 185, such as a Suss MicrTech AG, model MA200, through a lithography mask 186.
  • a suitable UV exposure system 185 such as a Suss MicrTech AG, model MA200
  • the photoresist is then developed in a development bath (not shown), baked and then the chip scale packaging layer plate is preferably etched by a dry etching process using CFe, C 4 Fg or other suitable dry etching gasses.
  • Commercially available equipment for this purpose includes a dry etch machine 188 manufactured by Surface Technology
  • the etching is achieved using a silicon etch solution located in a temperature . controlled bath (not shown).
  • a silicon etch solution located in a temperature . controlled bath (not shown).
  • Commercially available equipment for this purpose includes a Chemkleen bath and a WHRV circulator both of which are manufactured by Wafab Inc. of the U.S.A.
  • a suitable wet etching conventional silicon etching solution is Isoform Silicon etch, which is commercially available from Micro- Image Technology Ltd. of England.
  • the packaged wafer is conventionally rinsed after etching and photoresist stripping is performed.
  • the resulting etched wafer is shown in Fig. 3C.
  • the etched channels 52 in packaging layer plate 42 are then coated with insulation layer 18, as seen in step 190 and shown in Fig. 3D. Openings are formed in the insulation layer 18, preferably by using conventional photolithography techniques, to expose pads 16, as seen in step 192 and shown in Fig. 3E.
  • anti-corrosion treatment may be provided as seen in step 194.
  • Conductive layer deposition apparatus 196 which operates by vacuum deposition techniques, such as a sputtering machine manufactured by Balzers AG of Liechtenstein, is employed to produce a conductive layer 58 (Fig. 3F) over the chip scale packaging layer plate 42.
  • Configuration of conductors is carried out preferably by using conventional electro-deposited photoresist, which is commercially available from DuPont under the brand name Primecoat or from Shipley, under the brand name Eagle.
  • the photoresist is applied to the wafers in a photoresist bath assembly 198, which is commercially available from DuPont or Shipley.
  • the photoresist is preferably light configured by a UV exposure system 200, using a mask 202 to define suitable etching patterns.
  • the photoresist is then developed in a development bath 204, and then etched in a metal etch solution 206 located in an etching bath 208, thus providing a conductor configuration such as that shown in Figs.
  • the exposed conductive strips shown in Fig. 3 G are then plated, preferably by an electroless plating apparatus 210, which is commercially available from Okuno of Japan.
  • the wafer is then coated with a solder mask as indicated at reference numeral 212 to define the locations 60 (Fig. 3H) of bumps 28, which are then formed in a conventional manner (Fig. 31). Alternatively, the bumps 28 may not be required.
  • the wafer is then separated into individual pre-packaged integrated circuit devices by a dicing blade 214, as shown in Fig. 3 J.
  • dicing blade 214 is a diamond resinoid blade of thickness 2 - 12 mils.
  • the wafer could be separated into individual circuit devices using any other conventional method such as scribing, etching, laser and water jet.
  • the resulting packaged dies appear as illustrated generally in Figs. IA and IB.
  • each integrated circuit device includes a relatively thin and compact, environmentally protected and mechanically strengthened integrated circuit package having a multiplicity of electrical conductors plated directly over an insulation layer overlying a chip scale packaging layer.
  • Fig. 7A shows integrated circuit package 310, having a multiplicity of electrical conductors 312.
  • Conductors 312 are electrically connected to pads 316, and are preferably formed directly over an insulation layer 318 overlying at least one chip scale packaging layer 320 overlying an integrated circuit die 322 having an active surface 324.
  • insulation layer 318 may be partially or entirely obviated.
  • Insulation layer 318 may be any suitable insulation layer, such as a dielectric layer or a passivation layer.
  • Pads 316 are connected to circuitry on the active surface 324.
  • the chip scale packaging layer 320 is formed of a crystalline material, most preferably silicon.
  • the chip scale packaging layer 320 is formed of at least one of metal, plastic, thermoplastic, thermosetting and ceramic. Conductors 312 extend over edge surfaces 325 onto a planar surface 326 of the insulation layer 318. This contact arrangement permits flat surface mounting of package 310 onto a circuit board.
  • Integrated circuit package 310 may also include contact bumps, such as solder bumps 328 formed on electrical conductors 312, at apertures formed in a solder mask 330 formed over insulation layer 318 and packaging layer 320.
  • the integrated circuit package 310 also preferably includes a bonding layer 332, used to attach packaging layer 320 to integrated circuit die 322. Bonding layer 332 may include one or more of an adhesive such as epoxy or polyurethane, intermetallic bonding such as solder and anodic bonding.
  • Fig. 7A is particularly characterized in that chip scale packaging layer 320 is formed with a recess 334 overlying the active surface 324 of the die 322.
  • Fig. 7B shows integrated circuit package 350, having a multiplicity of electrical conductors 352.
  • Conductors 352 are electrically connected to pads 356, and are preferably formed directly over an insulation layer 358 overlying at least one chip scale packaging layer 360 overlying an integrated circuit die 362 having an active surface 364.
  • insulation layer 358 may be partially or entirely obviated.
  • Insulation layer 358 may be any suitable insulation layer, such as a dielectric layer or a passivation layer.
  • Pads 356 are connected to circuitry on the active surface 364.
  • the chip scale packaging layer 360 is formed of a crystalline material, most preferably silicon.
  • the chip scale packaging layer 360 is formed of at least one of metal, plastic, thermoplastic, thermosetting and ceramic.
  • Conductors 352 extend over edge surfaces 365 onto a planar surface 366 of the package 350. This contact arrangement permits flat surface mounting of package 350 onto a circuit board.
  • Integrated circuit package 350 may also include contact bumps, such as solder bumps 368 formed on electrical conductors 352, at apertures formed in a solder mask 370 formed over insulation layer 358 and packaging layer 360.
  • the integrated circuit package 350 also preferably includes a bonding layer 372, used to attach packaging layer 360 to integrated circuit die 362.
  • Bonding layer 372 may be one or more of an adhesive such as epoxy or polyurethane, intermetallic bonding such as solder and anodic bonding.
  • Fig. 7B The embodiment of Fig. 7B is particularly characterized in that chip scale packaging layer 360 is formed with a recess 374 overlying the active surface 364 of the die 362 and that die 362 is formed with an opening 376 communicating with recess 374.
  • An additional protective layer 378 typically formed of glass, is preferably attached to the underside of die 362, preferably in a waferwise manner prior to separating.
  • Protective layer 378 may be formed of silicon, glass, metal, plastic, thermoplastic, thermosetting, ceramic, any combination thereof, or any other suitable material.
  • integrated circuit package 350 also includes a bonding layer 380, used to attach additional protective layer 378 to die 362.
  • Bonding layer 380 may be one or more of an adhesive such as epoxy or polyurethane, intermetallic bonding such as solder and anodic bonding.
  • protective layer 378 is preferably thinned from an original thickness, typically in the range of 400 to 1000 microns, to a decreased thickness, typically in the range of 10-250 microns. Thinning of protective layer 378 may be achieved by grinding, lapping, etching or any other suitable method.
  • Fig. 7C shows integrated circuit package 390, having a multiplicity of electrical conductors 392.
  • Conductors 392 are electrically connected to pads 396, and are preferably formed directly over an insulation layer 398 overlying at least one chip scale packaging layer 400 overlying an integrated circuit die 402 having an active surface 404.
  • insulation layer 398 may be partially or entirely obviated.
  • Insulation layer 398 may be any suitable insulation layer, such as a dielectric layer or a passivation layer.
  • Pads 396 are connected to circuitry on the active surface 404.
  • the chip scale packaging layer 400 is formed of a crystalline material, most preferably silicon.
  • the chip scale packaging layer 400 is formed of at least one of metal, plastic, thermoplastic, thermosetting and ceramic.
  • Conductors 392 extend over edge surfaces 405 onto a planar surface 406 of the insulation layer 398. This contact arrangement permits flat surface mounting of package 390 onto a circuit board.
  • Integrated circuit package 390 may also include contact bumps, such as solder bumps 408 formed on electrical conductors 392, at apertures formed in a solder mask 410 formed over insulation layer 398 and packaging layer 400.
  • the integrated circuit package 390 also preferably includes a bonding layer 412, used to attach packaging layer 400 to integrated circuit die 402.
  • Bonding layer 412 may include one or more of an adhesive such as epoxy or polyurethane, intermetallic bonding such as solder and anodic bonding.
  • Fig. 7C is particularly characterized in that chip scale packaging layer 400 is formed with multiple recesses 414 overlying the active surface 404 of the die 402. It is appreciated that the methods described hereinbelow provide integrated circuit packages 310, 350 and 390 that are in the range defined as chip scale packages, typically no more than 20% larger in area than the size of the chip. It is also appreciated that the methods described hereinbelow provide integrated circuit packages 310, 350 and 390 in which the packaging process is carried out at wafer level up to separating of a wafer-wise package into separate packaged dies.
  • Figs. 8A and 8B are simplified pictorial illustrations of the attachment of a protective insulating chip scale packaging layer plate to a wafer, preferably formed of silicon and containing a plurality of integrated circuit dies in accordance with the present invention.
  • a silicon wafer 340 has a plurality of finished dies 322 formed thereon by conventional techniques, and is bonded at active surfaces 324 of dies 322 onto a chip scale packaging layer plate 342.
  • wafer 540 having a plurality of finished dies 522 formed thereon by conventional techniques is bonded at active surfaces 524 to plate 542 by bonding layer 532.
  • plate 542 includes multiple recesses 534, which are aligned to dies 522 before plate 542 is bonded to wafer 540.
  • Bonding layer 532 may include one or more of an adhesive such as epoxy or polyurethane, intermetallic bonding such as solder and anodic bonding. Alternatively, bonding layer 532 may include any other suitable bonding material.
  • electrical pads 516 are formed on the active surfaces 524 defined on wafer 540.
  • chip scale packaging layer plate 542 is preferably thinned from an original thickness Ll, typically in the range of 400 to 1000 microns, to a decreased thickness L2, typically in the range of 10-250 microns, as shown in Fig. 9B. Thinning of chip scale packaging layer plate 542 may be achieved by grinding, lapping, etching or any other suitable method.
  • the silicon wafer 540 is preferably thinned from an original thickness L3, typically in the range of 400 to 1000 microns, to a decreased thickness L4, typically in the range of 10-150 microns, as shown in Fig. 9B.
  • wafer 540 may be thinned to a decreased thickness approximating 0 microns, leaving only the circuitry and pads on the active surface 524 bonded to the packaging layer plate 542. Thinning of wafer 540 may be achieved by grinding, lapping, etching or any other suitable method.
  • wafer 540 is preferably thinned on a planar surface opposite active surface 524. This reduction in wafer thickness is enabled by the additional mechanical strength provided by the bonding thereto of plate 542. The reduction in thickness of the silicon wafer need not necessarily take place at this stage, but may take place at any suitable later stage.
  • the chip scale packaging layer plate 542 preferably formed of silicon is etched, using a photolithography process, along its top surface 546 along predetermined dice lines that separate the individual dies. Etched channels 552 are thus produced, which extend entirely through the thickness of the chip scale packaging layer plate 542, typically in the range of 10-250 microns, and through the bonding layer 532 as well as any other layers, such as insulation layers which may be present, thereby exposing pads 516.
  • the etched packaged wafer including a plurality of chip scale packaging layers 520 each including at least one recess 534, and a corresponding plurality of integrated circuit dies 522 bonded thereto, is shown in Fig. 9C.
  • the aforementioned etching typically is achieved by a dry etching process using SF 6 , C 4 Fg or other suitable dry etching gasses.
  • the etching takes place in conventional silicon etching solution, such as a combination of 2.5% hydrofluoric acid, 50% nitric acid, 10% acetic acid and 37.5% water, so as to etch the chip scale packaging layer plate 542 down to the pads 516, as shown in Fig. 9C.
  • the result of the silicon etching is a plurality of chip scale packaging layers 520, each of which includes silicon of thickness in the range of 10-250 microns.
  • etched channels 552 are preferably coated with a dielectric material, such as epoxy, silicon oxide, solder mask, or any other suitable dielectric material, such as silicon nitride, silicon oxinitride, polyimide, BCBTM, parylene, polynaphthalenes, fluorocarbons or accrylates.
  • the resulting insulation layer 518 is preferably formed by spin coating, or may be formed by any suitable method, such as spray coating, curtain coating, liquid phase deposition, physical vapor deposition, chemical vapor deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, rapid thermal chemical vapor deposition or atmospheric pressure chemical vapor deposition.
  • an opening 556 is formed in the insulation layer 518 between each pair of adjacent dies, by any suitable method. Openings 556 extend through insulation layer 518, thereby exposing pads 516.
  • Fig. 9F shows the formation of a conductive layer 558, which covers insulation layer 518 and extends into openings 556.
  • Conductive layer 558 is preferably formed of aluminum, or may be formed of any suitable conductive material or combination of materials, such as aluminum, copper, titanium, titanium tungsten, or chrome.
  • Fig. 9G shows patterning of the conductive layer 558, typically by conventional photolithographic techniques, to define the plurality of conductors 512 which electrically contact edges of one or more pads 516 on dies 522 and are appropriately plated.
  • Fig. 9H shows the wafer being coated with a protective material, preferably solder mask 530 or other protective material such as parylene, BCBTM, or polyamide, which is patterned to define apertures 560 therein, communicating with conductors 512.
  • a protective material preferably solder mask 530 or other protective material such as parylene, BCBTM, or polyamide
  • Fig. 91 shows the formation of contact bumps, such as solder bumps 528, at apertures 560 in electrical contact with conductors 512.
  • the wafer is then separated, as shown in Fig. 9 J, along lines 564, to provide individual integrated circuit packages, each including a single integrated circuit die 522 and at least one recess 534, and being similar to one of integrated circuit packages 310, 350 and 390 of Figs. 7A, 7B and 7C.
  • Fig. 10 is a partially cut away, detailed, pictorial illustration of an integrally packaged integrated circuit device 510 produced from the wafer of Fig. 9 J.
  • the integrated circuit package 510 includes chip scale packaging layer 520 including at least one recess 534, joined by bonding layer 532 to die 522. Surfaces of pads 516 are in electrical contact with conductors 512, which are directly formed over dielectric insulation layer 518, as described hereinabove.
  • FIG. 11 and 12 illustrate apparatus for producing integrated circuit devices in accordance with a preferred embodiment of the present invention.
  • a conventional wafer fabrication facility 580 provides wafers 540.
  • chip scale packaging layers 542 such as silicon substrates, and then bonded on their active surfaces to chip scale packaging layer plates
  • bonding apparatus 582 using bonding layer 532, by bonding apparatus 582, preferably having facilities for rotation of the wafer 540, the chip scale packaging layer plates 542 and the bonding layer 532 so as to obtain even distribution of the bonding layer 532.
  • the chip scale packaging layer plate 542 and optionally the wafer 540 bonded thereto are thinned as by grinding apparatus 583, such as model BFG 841, which is commercially available from Disco Ltd. of Japan.
  • the chip scale packaging layer plate 542 is then etched in a pattern preferably defined by using conventional photolithography techniques, such as by using conventional spin-coated photoresist as indicated by reference numeral 584.
  • a suitable photoresist is commercially available from Hoechst, under the brand designation AZ 4562.
  • the photoresist is preferably mask exposed by a suitable UV exposure system 585, such as a Suss MicrTech AG, model MA200, through a lithography mask 586.
  • a suitable UV exposure system 585 such as a Suss MicrTech AG, model MA200
  • the photoresist is then developed in a development bath (not shown), baked and then the chip scale packaging layer plate is preferably etched by a dry etching process using SF O , C 4 Fs or other suitable dry etching gasses.
  • Commercially available equipment for this purpose includes a dry etch machine 588 manufactured by Surface Technology Systems of England.
  • the etching is achieved using a silicon etch solution located in a temperature controlled bath (not shown).
  • a silicon etch solution located in a temperature controlled bath (not shown).
  • Commercially available equipment for this purpose includes a Chemkleen bath and a WHRV circulator both of which are manufactured by Wafab Inc. of the U.S.A.
  • a suitable wet etching conventional silicon etching solution is Isoform Silicon etch, which is commercially available from Micro- Image Technology Ltd. of England.
  • the packaged wafer is conventionally rinsed after etching and photoresist stripping is performed.
  • the resulting etched wafer is shown in Fig. 9C.
  • the etched channels 552 in packaging layer plate 542 are then coated with insulation layer 518, as seen in step 590 and shown in Fig. 9D. Openings are formed in the insulation layer 518, preferably by using conventional photolithography techniques, to expose pads 516, as seen in step 592 and shown in Fig. 9E.
  • anti-corrosion treatment may be provided as seen in step 594.
  • Conductive layer deposition apparatus 596 which operates by vacuum deposition techniques, such as a sputtering machine manufactured by Balzers AG of Liechtenstein, is employed to produce a conductive layer 558 (Fig. 9F) over the chip scale packaging layer plate 542.
  • Configuration of conductors is carried out preferably by using conventional electro-deposited photoresist, which is commercially available from
  • the photoresist is applied to the wafers in a photoresist bath assembly 598, which is commercially available from DuPont or Shipley.
  • the photoresist is preferably light configured by a LJV exposure system 600, using a mask 602 to define suitable etching patterns.
  • the photoresist is then developed in a development bath 604, and then etched in a metal etch solution 606 located in an etching bath 608, thus providing a conductor configuration such as that shown in Figs. 7A, 7B and 1C.
  • the exposed conductive strips shown in Fig. 9G are then plated, preferably by an electroless plating apparatus 610, which is commercially available from Okuno of Japan.
  • the wafer is then coated with a solder mask as indicated at reference numeral 612 to define the locations 560 (Fig. 9H) of bumps 528, which are then formed in a conventional manner (Fig. 91). Alternatively, the bumps 528 may not be required.
  • the wafer is then separated into individual pre-packaged integrated circuit devices by a dicing blade 614, as shown in Fig. 9 J.
  • dicing blade 614 is a diamond resinoid blade of thickness 2 - 12 mils.
  • the wafer could be separated into individual circuit devices using any other conventional method such as scribing, etching, laser and water jet.
  • the resulting packaged dies appear as illustrated generally in Figs. 7A, 7B and 7C.
  • the integrated circuit device includes a relatively thin and compact, environmentally protected and mechanically strengthened, integrated circuit package 710, having a multiplicity of electrical conductors 712.
  • conductors 712 are electrically connected to pads 716, and are preferably formed directly over an insulation layer 718 overlying an integrated circuit die 722 having an active surface 724, without there being an intervening packaging layer, such as a glass layer.
  • insulation layer 718 may be partially or entirely obviated.
  • Insulation layer 718 may be any suitable insulation layer, such as a dielectric layer or a passivation layer.
  • Pads 716 are connected to circuitry on the active surface 724.
  • conductors 712 extend over edge surfaces 725 onto a planar surface 726 of the insulation layer 718.
  • This contact arrangement permits flat surface mounting of package 710 onto a circuit board.
  • integrated circuit package 710 may also include contact bumps, such as solder bumps 728 formed on electrical conductors 712, at apertures formed in a solder mask 730 formed over insulation layer 718.
  • the conductors 712 do not extend beyond edge surfaces 725 onto planar surface 726 or extend onto planar surface 726 only to a limited extent, thereby defining peripheral contacts.
  • the integrated circuit device preferably includes a chip scale packaging layer 720, which is formed of a crystalline material, most preferably silicon.
  • the chip scale packaging layer 720 is formed of at least one of metal, plastic, thermoplastic, thermosetting and ceramic.
  • the integrated circuit package 710 shown in Figs. 13A and 13B, also includes a bonding layer 732, used to attach packaging layer 720 to integrated circuit die 722, as described hereinbelow.
  • the methods described hereinbelow provide integrated circuit packages 710 that are in the range defined as chip scale packages, typically no more than 20% larger in area than the size of the chip. It is also appreciated that the methods described hereinbelow provide integrated circuit packages 710 in which the packaging process is carried out at wafer level up to separating of a wafer-wise package into separate packaged dies.
  • Figs. 14A and 14B are simplified pictorial illustrations of the attachment of a protective insulating chip scale packaging layer plate to a wafer, preferably formed of silicon and containing a plurality of integrated circuit dies in accordance with the present invention.
  • a silicon wafer 740 has a plurality of finished dies 722 formed thereon by conventional techniques, and is bonded at active surfaces 724 of dies 722 onto a chip scale packaging layer plate 742.
  • wafer 740 having a plurality of finished dies 722 formed thereon by conventional techniques, is bonded at active surfaces 724 to plate 742 by bonding layer
  • Bonding layer 732 may include one or more of an adhesive such as epoxy or polyurethane, intermetallic bonding such as solder and anodic bonding. Alternatively, bonding layer 732 may include any other suitable bonding material. As seen in Fig.
  • electrical pads 716 are formed on the active surfaces 724 defined on wafer 740.
  • chip scale packaging layer plate 742 is preferably thinned from an original thickness Ll, typically in the range of 400 to 1000 microns, to a decreased thickness L2, typically in the range of 10-250 microns, as shown in Fig. 15B. Thinning of chip scale packaging layer plate 742 may be achieved by grinding, lapping, etching or any other suitable method. The reduction in thickness of the packaging layer need not necessarily take place at this stage, but may take place at any suitable later stage.
  • the silicon wafer 740 is preferably thinned from an original thickness L3, typically in the range of 400 to 1000 microns, to a decreased thickness L4, typically in the range of 10-150 microns, as shown in Fig. 15B.
  • wafer 740 when employing a silicon on isolator process, wafer 740 may be thinned to a decreased thickness approximating 0 microns, leaving only the circuitry and pads on the active surface 724 bonded to the packaging layer plate 742. Thinning of wafer 740 may be achieved by grinding, lapping, etching or any other suitable method. As seen in Fig. 15B, wafer 740 is preferably thinned on a planar surface opposite active surface 724. This reduction in wafer thickness is enabled by the additional mechanical strength provided by the bonding thereto of plate 742.
  • the wafer 740 is etched, using a photolithography process, along its top surface 746 along predetermined dice lines that separate the individual dies. Etched channels 752 are thus produced, which extend entirely through the thickness of the wafer 740, typically in the range of 10-250 microns, thereby exposing pads 716.
  • the aforementioned etching typically is achieved by a dry etching process using SF ⁇ , C 4 F 8 or other suitable dry etching gasses.
  • the etching takes place in conventional silicon etching solution, such as a combination of 2.5% hydrofluoric acid, 50% nitric acid, 10% acetic acid and 37.5% water, so as to etch the wafer 740 down to pads 716, as shown in Fig. 15C.
  • the result of the silicon etching is a plurality of integrated circuit dies 722, each of which includes silicon of thickness in the range of 10-250 microns.
  • etched channels 752 are preferably coated with a dielectric material, such as epoxy, silicon oxide, solder mask, or any other suitable dielectric material, such as silicon nitride, silicon oxinitride, polyimide, BCBTM, parylene, polynaphthalenes, fluorocarbons or accrylates.
  • the resulting insulation layer 718 is preferably formed by spin coating, or may be formed by any suitable method, such as spray coating, curtain coating, liquid phase deposition, physical vapor deposition, chemical vapor deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, rapid thermal chemical vapor deposition or atmospheric pressure chemical vapor deposition.
  • an opening 756 is formed in the insulation layer 718 between each pair of adjacent dies, by any suitable method. Openings 756 extend through insulation layer 718, thereby exposing pads 716.
  • Fig. 15F shows the formation of a conductive layer 758, which covers insulation layer 718 and extends into openings 756.
  • Conductive layer 758 is preferably formed of aluminum, or may be formed of any suitable conductive material or combination of materials, such as aluminum, copper, titanium, titanium tungsten, or chrome.
  • Fig. 15G shows patterning of the conductive layer 758, typically by conventional photolithographic techniques, to define the plurality of conductors 712 which electrically contact edges of one or more pads 716 on dies 722 and are appropriately plated.
  • Fig. 15H shows the wafer being coated with a protective material, preferably solder mask 730 or other protective material such as parylene, BCBTM, or polyamide, which is patterned to define apertures 760 therein, communicating with conductors 712.
  • a protective material preferably solder mask 730 or other protective material such as parylene, BCBTM, or polyamide
  • Fig. 151 shows the formation of contact bumps, such as solder bumps 728, at apertures 760 in electrical contact with conductors 712.
  • the packaging layer plate is then separated, as shown in Fig. 15 J, along lines 764, to provide individual integrated circuit packages, each including a single integrated circuit die 722 and a single chip scale packaging layer 720 and being similar to integrated circuit package 710 of Figs. 13 A and 13B .
  • Fig. 16 is a partially cut away, detailed, pictorial illustration of an integrally packaged integrated circuit device 710 produced from the wafer of Fig. 15 J.
  • the integrated circuit package 710 includes chip scale packaging layer 720, joined by bonding layer 732 to die 722. Surfaces of pads 716 are in electrical contact with conductors 712, which are directly formed over dielectric insulation layer 718, as described hereinabove.
  • a conventional wafer fabrication facility 880 provides wafers 740. Individual wafers 740 are bonded on their active surfaces to chip scale packaging layer plates 742, such as silicon substrates, using bonding layer 732, by bonding apparatus 882, preferably having facilities for rotation of the wafer 740, the chip scale packaging layer plates 742 and the bonding layer 732 so as to obtain even distribution of the bonding layer 732.
  • the chip scale packaging layer plate 742 and optionally the wafer 740 bonded thereto are thinned as by grinding apparatus 883, such as model BFG 841, which is commercially available from Disco Ltd. of Japan.
  • the wafer 740 is then etched in a pattern preferably defined by using conventional photolithography techniques, such as by using conventional spin-coated photoresist as indicated by reference numeral 884.
  • a suitable photoresist is commercially available from Hoechst, under the brand designation AZ 4562.
  • the photoresist is preferably mask exposed by a suitable UV exposure system 885, such as a Suss MicrTech AG, model MA200, through a lithography mask 886.
  • a suitable UV exposure system 885 such as a Suss MicrTech AG, model MA200
  • the photoresist is then developed in a development bath (not shown), baked and then the wafer is preferably etched by a dry etching process using SF 6 , C 4 F 8 or other suitable dry etching gasses.
  • Commercially available equipment for this purpose includes a dry etch machine 888 manufactured by Surface Technology Systems of England.
  • the etching is achieved using a silicon etch solution located in a temperature controlled bath (not shown).
  • Commercially available equipment for this purpose includes a Chemkleen bath and a WHRV circulator both of which are manufactured by Wafab Inc. of the U.S. A.
  • a suitable wet etching conventional silicon etching solution is Isoform Silicon etch, which is commercially available from Micro- Image Technology Ltd. of England.
  • the packaged wafer is conventionally rinsed after etching and photoresist stripping is performed.
  • the resulting etched wafer is shown in Fig. 15C.
  • the etched channels 752 in wafer 740 are then coated with insulation layer 718, as seen in step 890 and shown in Fig. 15D. Openings are formed in the insulation layer 718, preferably by using conventional photolithography techniques, to expose pads 716, as seen in step 892 and shown in Fig. 15E.
  • anti-corrosion treatment may be provided as seen in step 894.
  • Conductive layer deposition apparatus 896 which operates by vacuum deposition techniques, such as a sputtering machine manufactured by Balzers AG of Liechtenstein, is employed to produce a conductive layer 758 (Fig. 15F) over the wafer 740.
  • Configuration of conductors is carried out preferably by using conventional electro-deposited photoresist, which is commercially available from
  • the photoresist is applied to the wafers in a photoresist bath assembly 898, which is commercially available from DuPont or Shipley.
  • the photoresist is preferably light configured by a UV exposure system 900, using a mask 902 to define suitable etching patterns.
  • the photoresist is then developed in a development bath 904, and then etched in a metal etch solution 906 located in an etching bath 908, thus providing a conductor configuration such as that shown in Figs.
  • the exposed conductive strips shown in Fig. 15G are then plated, preferably by an electroless plating apparatus 910, which is commercially available from Okuno of Japan.
  • the wafer is then coated with a solder mask as indicated at reference numeral 912 to define the locations 760 (Fig. 15ET) of bumps 728, which are then formed in a conventional manner (Fig. 151).
  • the bumps 728 may not be required.
  • dicing blade 914 is a diamond resinoid blade of thickness 2 - 12 mils.
  • the wafer could be separated into individual circuit devices using any other conventional method such as scribing, etching, laser and water jet.
  • the resulting packaged dies appear as illustrated generally in Figs. 13 A and 13B.
  • each integrated circuit device includes a relatively thin and compact, environmentally protected and mechanically strengthened integrated circuit package having a multiplicity of electrical conductors plated directly over an insulation layer overlying circuit die.
  • Fig. 19A shows integrated circuit package 1010, having a multiplicity of electrical conductors 1012.
  • Conductors 1012 are electrically connected to pads 1016, and are preferably formed directly over an insulation layer 1018 overlying an integrated circuit die 1022 having an active surface 1024.
  • insulation layer 1018 may be partially or entirely obviated.
  • Insulation layer 1018 may be any suitable insulation layer, such as a dielectric layer or a passivation layer.
  • Pads 1016 are connected to circuitry on the active surface 1024.
  • Conductors 1012 extend over edge surfaces 1025 onto a planar surface 1026 of the insulation layer 1018. This contact arrangement permits flat surface mounting of package 1010 onto a circuit board.
  • Integrated circuit package 1010 may also include contact bumps, such as solder bumps 1028 formed on electrical conductors 1012, at apertures formed in a solder mask 1030 formed over insulation layer 1018.
  • the integrated circuit device preferably includes a chip scale packaging layer 1020, which is formed of a crystalline material, most preferably silicon.
  • the chip scale packaging layer 1020 is formed of at least one of metal, plastic, thermoplastic, thermosetting and ceramic.
  • the integrated circuit package 1010 also preferably includes a bonding layer 1032, used to attach packaging layer 1020 to integrated circuit die 1022.
  • Bonding layer 1032 may include one or more of an adhesive such as epoxy or polyurethane, intermetallic bonding such as solder and anodic bonding.
  • Fig. 19A The embodiment of Fig. 19A is particularly characterized in that chip scale packaging layer 1020 is formed with a recess 1034 overlying the active surface 1024 of the die 1022.
  • Fig. 19B shows integrated circuit package 1050, having a multiplicity of electrical conductors 1052.
  • Conductors 1052 are electrically connected to pads 1056, and are preferably formed directly over an insulation layer 1058 overlying an integrated circuit die 1062 having an active surface 1064.
  • insulation layer 1058 may be partially or entirely obviated.
  • Insulation layer 1058 may be any suitable insulation layer, such as a dielectric layer or a passivation layer.
  • Pads 1056 are connected to circuitry on the active surface 1064.
  • Conductors 1052 extend over edge surfaces 1065 onto a planar surface 1066 of the insulation layer 1058. This contact arrangement permits flat surface mounting of package 1050 onto a circuit board.
  • Integrated circuit package 1050 may also include contact bumps, such as solder bumps 1068 formed on electrical conductors 1052, at apertures formed in a solder mask 1070 formed over insulation layer 1058.
  • the integrated circuit device 1050 preferably includes a chip scale packaging layer 1060, which is formed of a crystalline material, most preferably silicon.
  • the chip scale packaging layer 1060 is formed of at least one of metal, plastic, thermoplastic, thermosetting and ceramic.
  • the integrated circuit package 1050 also preferably includes a bonding layer 1072, used to attach packaging layer 1060 to integrated circuit die 1062.
  • Bonding layer 1072 may include one or more of an adhesive such as epoxy or polyurethane, intermetallic bonding such as solder and anodic bonding.
  • Fig. 19B The embodiment of Fig. 19B is particularly characterized in that chip scale packaging layer 1060 is formed with multiple recesses 1074 overlying the active surface 1064 of the die 1062. It is appreciated that the methods described hereinbelow provide integrated circuit packages 1010 and 1050 that are in the range defined as chip scale packages, typically no more than 20% larger in area than the size of the chip. It is also appreciated that the methods described hereinbelow provide integrated circuit packages 1010 and 1050 in which the packaging process is carried out at wafer level up to separating of a wafer- wise package into separate packaged dies.
  • Figs. 2OA and 2OB are simplified pictorial illustrations of the attachment of a protective insulating chip scale packaging layer plate to a wafer, preferably formed of silicon and containing a plurality of integrated circuit dies in accordance with the present invention.
  • a silicon wafer 1040 has a plurality of finished dies 1022 formed thereon by conventional techniques, and is bonded at active surfaces 1024 of dies 1022 onto a chip scale packaging layer plate 1042.
  • wafer 1240 having a plurality of finished dies 1222 formed thereon by conventional techniques, is bonded at active surfaces 1224 to plate 1242 by bonding layer 1232.
  • plate 1242 includes multiple recesses 1234, which are aligned to dies 1222 before plate 1242 is bonded to wafer 1240.
  • Bonding layer 1232 may include one or more of an adhesive such as epoxy or polyurethane, intermetallic bonding such as solder and anodic bonding. Alternatively, bonding layer 1232 may include any other suitable bonding material.
  • electrical pads 1216 are formed on the active surfaces 1224 defined on wafer 1240. It is appreciated that certain steps in the conventional fabrication of silicon wafer
  • chip scale packaging layer plate 1242 is preferably thinned from an original thickness Ll, typically in the range of 400 to 1000 microns, to a decreased thickness L2, typically in the range of 10-250 microns, as shown in Fig. 2 IB. Thinning of chip scale packaging layer plate 1242 may be achieved by grinding, lapping, etching or any other suitable method. The reduction in thickness of the chip scale packaging layer need not necessarily take place at this stage, but may take place at any suitable later stage.
  • the silicon wafer 1240 is preferably thinned from an original thickness L3, typically in the range of 400 to 1000 microns, to a decreased thickness L4, typically in the range of 10-150 microns, as shown in Fig. 2 IB.
  • wafer 1240 may be thinned to a decreased thickness approximating 0 microns, leaving only the circuitry and pads on the active surface 1224 bonded to the packaging layer plate 1242. Thinning of wafer 1240 may be achieved by grinding, lapping, etching or any other suitable method.
  • wafer 1240 is preferably thinned on a planar surface opposite active surface 1224. This reduction in wafer thickness is enabled by the additional mechanical strength provided by the bonding thereto of plate 1242.
  • the wafer 1240 is etched, using a photolithography process, along its top surface 1246 along predetermined dice lines that separate the individual dies. Etched channels 1252 are thus produced, which extend entirely through the thickness of the wafer 1240, typically in the range of 10-250 microns, thereby exposing pads 1216.
  • the aforementioned etching typically is achieved by a dry etching process using
  • etching takes place in conventional silicon etching solution, such as a combination of 2.5% hydrofluoric acid,
  • the result of the silicon etching is a plurality of integrated circuit dies 1222, each of which includes silicon of thickness in the range of 10-250 microns.
  • etched channels 1252 are preferably coated with a dielectric material, such as epoxy, silicon oxide, solder mask, or any other suitable dielectric material, such as silicon nitride, silicon oxinitride, polyimide, BCBTM, parylene, polynaphthalenes, fluorocarbons or accrylates.
  • the resulting insulation layer 1218 is preferably formed by spin coating, or may be formed by any suitable method, such as spray coating, curtain coating, liquid phase deposition, physical vapor deposition, chemical vapor deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, rapid thermal chemical vapor deposition or atmospheric pressure chemical vapor deposition.
  • an opening 1256 is formed in the insulation layer 1218 between each pair of adjacent dies, by any suitable method. Openings 1256 extend through insulation layer 1218, thereby exposing pads 1216.
  • Fig. 2 IF shows the formation of a conductive layer 1258, which covers insulation layer 1218 and extends into openings 1256.
  • Conductive layer 1258 is preferably formed of aluminum, or may be formed of any suitable conductive material or combination of materials, such as aluminum, copper, titanium, titanium tungsten, or chrome.
  • Fig. 21G shows patterning of the conductive layer 1258, typically by conventional photolithographic techniques, to define the plurality of conductors 1212 which electrically contact edges of one or more pads 1216 on dies 1222 and are appropriately plated.
  • Fig. 2 IH shows the wafer being coated with a protective material, preferably solder mask 1230 or other protective material such as parylene, BCBTM, or polyamide, which is patterned to define apertures 1260 therein, communicating with conductors 1212.
  • a protective material preferably solder mask 1230 or other protective material such as parylene, BCBTM, or polyamide, which is patterned to define apertures 1260 therein, communicating with conductors 1212.
  • Fig. 211 shows the formation of contact bumps, such as solder bumps 1228, at apertures 1260 in electrical contact with conductors 1212.
  • the packaging layer plate is then separated, as shown in Fig. 21J, along lines 1264, to provide individual integrated circuit packages, each including a single integrated circuit die 1222 and at least one recess 1234, and being similar to one of integrated circuit packages 1010, 1050 and 1090 of Figs. 19A and 19B.
  • Fig. 22 is a partially cut away, detailed, pictorial illustration of an integrally packaged integrated circuit device 1210 produced from the wafer of Fig. 2 IJ. As seen in Fig.
  • the integrated circuit package 1210 includes chip scale packaging layer 1220 including at least one recess 1234, joined by bonding layer 1232 to die 1222. Surfaces of pads 1216 are in electrical contact with conductors 1212, which are directly formed over dielectric insulation layer 1218, as described hereinabove.
  • a conventional wafer fabrication facility 1280 provides wafers 1240. Individual wafers 1240 are aligned to chip scale packaging layers 1242 such as silicon substrates, and then bonded on their active surfaces to chip scale packaging layer plates 1242, using bonding layer 1232, by bonding apparatus 1282, preferably having facilities for rotation of the wafer 1240, the chip scale packaging layer plates 1242 and the bonding layer 1232 so as to obtain even distribution of the bonding layer 1232.
  • the chip scale packaging layer plate 1242 and optionally the wafer 1240 bonded thereto Fig.
  • the wafer 1240 is then etched in a pattern preferably defined by using conventional photolithography techniques, such as by using conventional spin-coated photoresist as indicated by reference numeral 1284.
  • a suitable photoresist is commercially available from Hoechst, under the brand designation AZ 4562.
  • the photoresist is preferably mask exposed by a suitable UV exposure system 1285, such as a Suss MicrTech AG, model MA200, through a lithography mask 1286.
  • a suitable UV exposure system 1285 such as a Suss MicrTech AG, model MA200
  • the photoresist is then developed in a development bath (not shown), baked and then the wafer is preferably etched by a dry etching process using SF 6 , C 4 Fg or other suitable dry etching gasses.
  • SF 6 , C 4 Fg or other suitable dry etching gasses Commercially available equipment for this purpose includes a dry etch machine 1288 manufactured by Surface Technology Systems of England.
  • the etching is achieved using a silicon etch solution located in a temperature controlled bath (not shown).
  • a silicon etch solution located in a temperature controlled bath (not shown).
  • Commercially available equipment for this purpose includes a Chemkleen bath and a WHRV circulator both of which are manufactured by Wafab Inc. of the U.S.A.
  • a suitable wet etching conventional silicon etching solution is Isoform Silicon etch, which is commercially available from Micro- Image Technology Ltd. of England.
  • the packaged wafer is conventionally rinsed after etching and photoresist stripping is performed.
  • the resulting etched wafer is shown in Fig. 21 C.
  • the etched channels 1252 in wafer 1240 are then coated with insulation layer 1218, as seen in step 1290 and shown in Fig. 21D. Openings are formed in the insulation layer 1218, preferably by using conventional photolithography techniques, to expose pads 1216, as seen in step 1292 and shown in Fig. 21E.
  • anti- corrosion treatment may be provided as seen in step 1294.
  • Conductive layer deposition apparatus 1296 which operates by vacuum deposition techniques, such as a sputtering machine manufactured by Balzers AG of Liechtenstein, is employed to produce a conductive layer 1258 (Fig. 21F) over the wafer 1240.
  • Configuration of conductors is carried out preferably by using conventional electro-deposited photoresist, which is commercially available from DuPont under the brand name Primecoat or from Shipley, under the brand name Eagle.
  • the photoresist is applied to the wafers in a photoresist bath assembly 1298, which is commercially available from DuPont or Shipley.
  • the photoresist is preferably light configured by a UV exposure system 1300, using a mask 1302 to define suitable etching patterns.
  • the photoresist is then developed in a development bath 1304, and then etched in a metal etch solution 1306 located in an etching bath 1308, thus providing a conductor configuration such as that shown in Figs.
  • the exposed conductive strips shown in Fig. 21G are then plated, preferably by an electroless plating apparatus 1310, which is commercially available from Okuno of Japan.
  • the wafer is then coated with a solder mask as indicated at reference numeral 1312 to define the locations 1260 (Fig. 21H) of bumps 1228, which are then formed in a conventional manner (Fig. 211). Alternatively, the bumps 1228 may not be required.
  • dicing blade 1314 is a diamond resinoid blade of thickness 2 - 12 mils.
  • the wafer could be separated into individual circuit devices using any other conventional method such as scribing, etching, laser and water jet.
  • the resulting packaged dies appear as illustrated generally in Figs. 19A and 19B.

Abstract

An integrally packaged integrated circuit device (10) including an integrated circuit die (22) including a crystalline substrate having first and second generally planar surfaces (26) and edge surfaces (25) and an active surface (24) formed on the first generally planar surface, at least one chip scale packaging layer (20) formed over the active surface and at least one electrical contact being connected to circuitry on the active surface by at least one pad (16) formed on the first generally planar surface.

Description

METHODS AND APPARATUS FOR PACKAGING INTEGRATED CIRCUIT
DEVICES
FIELD OF THE INVENTION
The present invention relates to methods and apparatus for producing integrated circuit devices and to integrated circuit devices produced thereby and more particularly to an integrally packaged die.
BACKGROUND OF THE INVENTION
An essential step in the manufacture of all integrated circuit devices is known as "packaging" and involves mechanical and environmental protection of a silicon chip which is at the heart of the integrated circuit as well as electrical interconnection between predetermined locations on the silicon chip and external electrical terminals.
At present three principal technologies are employed for packaging semiconductors: wire bonding, tape automatic bonding (TAB) and flip chip.
Wire bonding employs heat and ultrasonic energy to weld gold bonding wires between bond pads on the chip and contacts on the package. Tape automatic bonding (TAB) employs a copper foil tape instead of bonding wire. The copper foil tape is configured for each specific die and package combination and includes a pattern of copper traces suited thereto. The individual leads may be connected individually or as a group to the various bond pads on the chip.
Flip chips are integrated circuit dies which have solder bumps formed on top of the bonding pads, thus allowing the die to be "flipped" circuit side down and directly soldered to a substrate. Wire bonds are not required and considerable savings in package spacing may be realized.
The above-described technologies each have certain limitations. Both wire bonding and TAB bonding are prone to bad bond formation and subject the die to relatively high temperatures and mechanical pressures. Both wire bond and TAB technologies are problematic from a package size viewpoint, producing integrated circuit devices having a die-to-package area ratio ranging from about 10% to 60%. The flip-chip does not provide packaging but rather only interconnection. The interconnection encounters problems of uniformity in the solder bumps as well as in thermal expansion mismatching, which limits available substrates to silicon or to materials which have thermal expansion characteristics similar to those of silicon.
Conventional semiconductor packaging terminology has defined the term chip scale packaging to include any packaging process with a ratio of packaging, to die less than or equal to 1.2:1. Additionally, the packaging layer conventionally provides protection to the encased semiconductor or integrated circuit.
SUMMARY OF THE INVENTION
The present invention seeks to provide improved methods for producing integrated circuit devices. There is thus provided in accordance with a preferred embodiment of the present invention an integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.
There is also provided in accordance with another preferred embodiment of the present invention an integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over at least one edge surface of the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.
There is further provided in accordance with yet another preferred embodiment of the present invention an integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the second generally planar, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface. There is also provided in accordance with still another preferred embodiment of the present invention an integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one edge surface of the crystalline substrate, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.
Preferably, the at least one chip scale packaging layer is formed of a crystalline material. As a further preferred alternative, the at least one chip scale packaging layer is formed of at least one of metal, plastic, thermoplastic, thermosetting and ceramic. Additionally, the at least one chip scale packaging layer is formed of silicon. Alternatively, the crystalline substrate and the at least one chip scale packaging layer are both formed of silicon.
In accordance with another preferred embodiment of the present invention the integrally packaged integrated circuit device also includes an insulation layer formed over the at least one chip scale packaging layer and directly underlying the at least one electrical contact. Preferably, the insulation layer includes at least one of a passivation layer and a dielectric layer. Additionally, the insulation layer includes at least one of epoxy, silicon oxide, solder mask, silicon nitride, silicon oxinitride, polyimide, BCB™, parylene, polynaphthalenes, fluorocarbons and accrylates.
In accordance with yet another preferred embodiment of the present invention the integrally packaged integrated circuit device also includes at least one gap formed between the crystalline substrate and the at least one packaging layer. Additionally, the gap is formed as a recess in the at least one packaging layer.
In accordance with still another preferred embodiment of the present invention the integrally packaged integrated circuit device also includes at least one gap formed in the crystalline substrate.
In accordance with another preferred embodiment of the present invention the integrally packaged integrated circuit device also includes at least one gap formed in the crystalline substrate and at least one chip scale packaging layer formed underlying the crystalline substrate and sealing the gap formed in the crystalline substrate. There is also provided in accordance with another preferred embodiment of the present invention a method of producing integrally packaged integrated circuit devices including providing a plurality of integrated circuit dies formed on a wafer, each of the dies having first and second generally planar surfaces, and an active surface and at least one pad formed on the first generally planar surface, the active surface including circuitry, forming at least one chip scale packaging layer over the active surface, forming at least one electrical contact over the at least one chip scale packaging layer, the at least one electrical contact being connected to the circuitry by the at least one pad and subsequently separating the wafer into a plurality of packaged integrated circuit devices.
There is also provided in accordance with another preferred embodiment of the present invention a method of producing integrally packaged integrated circuit devices including providing a plurality of integrated circuit dies formed on a wafer, each of the dies having first and second generally planar surfaces, and an active surface and at least one pad formed on the first generally planar surface, the active surface including circuitry, forming at least one chip scale packaging layer over the active surface, forming at least one electrical contact over at least one edge surface of the at least one chip scale packaging layer, the at least one electrical contact being connected to the circuitry by the at least one pad and subsequently separating the wafer into a plurality of packaged integrated circuit devices.
There is also provided in accordance with another preferred embodiment of the present invention a method of producing integrally packaged integrated circuit devices including providing a plurality of integrated circuit dies formed on a wafer, each of the dies having first and second generally planar surfaces and edge surfaces, and an active surface and at least one pad formed on the first generally planar surface, the active surface including circuitry, forming at least one chip scale packaging layer over the active surface, forming at least one electrical contact over the second generally planar surface, the at least one electrical contact being connected to the circuitry by the at least one pad and subsequently separating the wafer into a plurality of packaged integrated circuit devices.
There is also provided in accordance with another preferred embodiment of the present invention a method of producing integrally packaged integrated circuit devices including providing a plurality of integrated circuit dies formed on a wafer, each of the dies having first and second generally planar surfaces and edge surfaces, and an active surface and at least one pad formed on the first generally planar surface, the active surface including circuitry, forming at least one chip scale packaging layer over the active surface, forming at least one electrical contact over the edge surfaces of the integrated circuit dies, the at least one electrical contact being connected to the circuitry by the at least one pad and subsequently separating the wafer into a plurality of packaged integrated circuit devices.
In accordance with another preferred embodiment of the present invention the forming at least one chip scale packaging layer includes forming at least one crystalline material chip scale packaging layer. As a further alternative, the forming at least one chip scale packaging layer includes forming a chip scale packaging layer of at least one of metal, plastic, thermoplastic, thermosetting and ceramic. Alternatively, the forming at least one chip scale packaging layer includes forming at least one silicon chip scale packaging layer. Additionally or alternatively, the forming at least one chip scale packaging layer includes forming at least one silicon chip scale packaging layer and the providing a plurality of integrated circuit dies formed on a wafer includes providing a plurality of integrated circuit dies formed on a silicon wafer.
In accordance with yet another preferred embodiment of the present invention the method also includes forming an insulation layer over the at least one chip scale packaging layer and wherein the forming at least one electrical contact includes forming the at least one electrical contact directly over the insulation layer. In accordance with still another preferred embodiment of the present invention the method also includes forming at least one gap between the plurality of dies and the at least one packaging layer. Additionally, the forming at least one gap includes forming a recess in the at least one packaging layer. Alternatively, the forming at least one gap includes forming at least one gap in the plurality of dies. Alternatively, the method also includes forming at least one gap in the plurality of dies.
In accordance with another preferred embodiment of the present invention the method also includes forming at least one gap in. the plurality of dies and forming at least one chip scale packaging layer over the second generally planar surface, thereby sealing the gap. In accordance with yet another preferred embodiment of the present invention the forming at least one chip scale packaging layer includes bonding the chip scale packaging layer to the plurality of dies using a bonding layer. Preferably, the bonding layer includes at least one of an adhesive, intermetallic bonding and anodic bonding.
In accordance with still another preferred embodiment of the present invention the forming at least one chip scale packaging layer also includes thinning the packaging layer from an original thickness to a decreased thickness. Preferably, the thinning includes at least one of grinding, lapping and etching. Additionally, the decreased thickness is approximately between 50 - 250 microns.
In accordance with still another preferred embodiment of the present invention the method also includes thinning the plurality of dies from an original thickness to a decreased thickness, subsequent to the forming at least one chip scale packaging layer and prior to the separating. Preferably, the thinning includes at least one of grinding, lapping and etching. Additionally, the decreased thickness is approximately between 10 - 150 microns. Additionally, the thinning includes thinning the second planar surface.
In accordance with another preferred embodiment of the present invention the method also includes forming at least one first gap in the plurality of dies and forming at least one second gap in the at least one chip scale packaging layer, the second gap communicating with the first gap. Additionally, the method also includes forming at least one chip scale packaging layer over the second generally planar surface, thereby sealing the first gap.
In accordance with yet another preferred embodiment of the present invention the at least one chip scale packaging layer over the second generally planar surface includes at least one of silicon, glass, metal, plastic, thermoplastic, thermosetting and ceramic.
Preferably* the forming at least one chip scale packaging layer over the second generally planar surface includes bonding the chip scale packaging layer over the second generally planar surface to the plurality of dies using a bonding layer. Additionally, the bonding layer includes at least one of an adhesive, intermetallic bonding and anodic bonding.
In accordance with still another preferred embodiment of the present invention the forming at least one chip scale packaging layer over the second generally planar surface also includes thinning the packaging layer from an original thickness to a decreased thickness. Preferably, the thinning includes at least one of grinding, lapping and etching. Additionally, the decreased thickness is approximately between 50 - 250 microns. BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will be understood and appreciated more fully from the following detailed description, taken in conjunction with the drawings in which: Figs. IA and IB are, respectively, a simplified pictorial illustration and a simplified sectional illustration of an integrally packaged integrated circuit device constructed and operative in accordance with a preferred embodiment of the present invention, the sectional illustration being taken along lines IB - IB in Fig. IA;
Figs. 1C and ID are, respectively, a simplified pictorial illustration and a simplified sectional illustration of an integrally packaged integrated circuit device constructed and operative in accordance with another preferred embodiment of the present invention, the sectional illustration being taken along lines ID - ID in Fig. 1C;
Figs. 2A and 2B are simplified pictorial illustrations of the attachment of a protective insulating cover plate to a wafer containing a plurality of integrated circuit dies in accordance with a preferred embodiment of the present invention;
Figs. 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 31 and 3J are sectional illustrations of various stages in the manufacture of integrally packaged integrated circuit devices in accordance with a preferred embodiment of the present invention;
Fig. 4 is a partially cut away detailed pictorial illustration of an integrally packaged integrated circuit device produced from the wafer of Fig. 3J;
Figs. 5 and 6 together provide a simplified block diagram illustration of apparatus for carrying out the method of the present invention; and
Figs. 7A, 7B and 7C are simplified pictorial illustrations of three alternative embodiments of an integrally packaged integrated circuit device constructed and operative in accordance with yet another preferred embodiment of the present invention. Figs. 8A and 8B are simplified pictorial illustrations of the attachment of a protective insulating cover plate to a wafer containing a plurality of integrated circuit dies in accordance with another preferred embodiment of the present invention;
Figs. 9A, 9B, 9C, 9D, 9E, 9F, 9G, 9H, 91 and 9J are sectional illustrations of various stages in the manufacture of integrally packaged integrated circuit devices in accordance with another preferred embodiment of the present invention;
Fig. 10 is a partially cut away detailed pictorial illustration of an integrally packaged integrated circuit device produced from the wafer of Fig. 9 J;
Figs. 11 and 12 together provide a simplified block diagram illustration of apparatus for carrying out the method of the present invention;
Figs. 13 A and 13B are, respectively, a simplified pictorial illustration and a simplified sectional illustration of an integrally packaged integrated circuit device constructed and operative in accordance with a preferred embodiment of the present invention, the sectional illustration being taken along lines XlULB - XIIIB in Fig. IA;
Figs. 13C and 13D are, respectively, a simplified pictorial illustration and a simplified sectional illustration of an integrally packaged integrated circuit device constructed and operative in accordance with another preferred embodiment of the present invention, the sectional illustration being taken along lines XiIlD - XIHD in
Fig. 13C;
Figs. 14A and 14B are simplified pictorial illustrations of the attachment of a protective insulating cover plate to a wafer containing a plurality of integrated circuit dies in accordance with a preferred embodiment of the present invention;
Figs. 15A, 15B, 15C, 15D, 15E, 15F, 15G, 15H, 151 and 15J are sectional illustrations of various stages in the manufacture of integrally packaged integrated circuit devices in accordance with a preferred embodiment of the present invention;
Fig. 16 is a partially cut away detailed pictorial illustration of an integrally packaged integrated circuit device produced from the wafer of Fig. 15 J;
Figs. 17 and 18 together provide a simplified block diagram illustration of apparatus for carrying out the method of the present invention; and
Figs. 19A and 19B are simplified pictorial illustrations of three alternative embodiments of an integrally packaged integrated circuit device constructed and operative in accordance with yet another preferred embodiment of the present invention. Figs. 2OA and 2OB are simplified pictorial illustrations of the attachment of a protective insulating cover plate to a wafer containing a plurality of integrated circuit dies in accordance with another preferred embodiment of the present invention;
Figs. 21A, 21B, 21C, 21D, 21E, 21F, 21G, 21H, 211 and 21J are sectional illustrations of various stages in the manufacture of integrally packaged integrated circuit devices in accordance with another preferred embodiment of the present invention; FIg. 22 is a partially cut away detailed pictorial illustration of an integrally packaged integrated circuit device produced from the wafer of Fig. 2 IJ; and
Figs. 23 and 24 together provide a simplified block diagram illustration of apparatus for carrying out the method of the present invention;
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
Reference is now made to Figs. IA - 3J, which illustrate integrated circuit devices, and the production thereof, in accordance with a preferred embodiment of the present invention. As seen in Figs. IA and IB, the integrated circuit device includes a relatively thin and compact, environmentally protected and mechanically strengthened, integrated circuit package 10, having a multiplicity of electrical conductors 12.
It is a particular feature of the present invention that conductors 12 are electrically connected to pads 16, and are preferably formed directly over an insulation layer 18 overlying at least one chip scale packaging layer 20 overlying an integrated circuit die
22 having an active surface 24. Alternatively insulation layer 18 may be partially or entirely obviated. Insulation layer 18 may be any suitable insulation layer, such as a dielectric layer or a passivation layer. Pads 16 are connected to circuitry on the active surface 24. Preferably the chip scale packaging layer 20 is formed of a crystalline material, most preferably silicon. As a further alternative, the chip scale packaging layer
20 is formed of at least one of metal, plastic, thermoplastic, thermosetting and ceramic.
In accordance with a preferred embodiment of the invention, conductors 12 extend over edge surfaces 25 onto a planar surface 26 of the insulation layer 18. This contact arrangement permits flat surface mounting of package 10 onto a circuit board. As seen in Figs. IA and IB, integrated circuit package 10 may also include contact bumps, such as solder bumps 28 formed on electrical conductors 12, at apertures formed in a solder mask 30 formed over insulation layer 18 and packaging layer 20.
As a further alternative, as shown in Figs 1C and ID, the conductors 12 do not extend beyond edge surfaces 25 onto planar surface 26 or extend onto planar surface 26 only to a limited extent, thereby defining peripheral contacts.
The integrated circuit package 10, shown in Figs. IA and IB, also includes a bonding layer 32, used to attach packaging layer 20 to integrated circuit die 22, as described hereinbelow.
It is appreciated that the methods described hereinbelow provide integrated circuit packages 10 that are in the range defined as chip scale packages, typically no more than
20% larger in area than the size of the chip. It is also appreciated that the methods described hereinbelow provide integrated circuit packages 10 in which the packaging process is carried out at wafer level up to separating of a wafer-wise package into separate packaged dies.
Figs. 2A and 2B are simplified pictorial illustrations of the attachment of a protective insulating chip scale packaging layer plate to a wafer, preferably formed of silicon and containing a plurality of integrated circuit dies in accordance with the present invention. As seen in Figs. 2A and 2B, typically a silicon wafer 40 has a plurality of finished dies 22 formed thereon by conventional techniques, and is bonded at active surfaces 24 of dies 22 onto a chip scale packaging layer plate 42.
In accordance with a preferred embodiment of the present invention, as illustrated in Fig. 3 A, wafer 40, having a plurality of finished dies 22 formed thereon by conventional techniques, is bonded at active surfaces 24 to plate 42 by bonding layer
32. Bonding layer 32 may include one or more of an adhesive such as epoxy or polyurethane, intermetallic bonding such as solder and anodic bonding. Alternatively, bonding layer 32 may include any other suitable bonding material. As seen in Fig. 3A, electrical pads 16 are formed on the active surfaces 24 defined on wafer 40.
It is appreciated that certain steps in the conventional fabrication of silicon wafer 40 may be eliminated when the wafer is used in accordance with the present invention. These steps include the provision of via openings above pads, wafer back grinding and wafer back metal coating. Following the bonding step described hereinabove, chip scale packaging layer plate 42 is preferably thinned from an original thickness Ll, typically in the range of 400 to 1000 microns, to a decreased thickness L2, typically in the range of 10-250 microns, as shown in Fig. 3B. Thinning of chip scale packaging layer plate 42 may be achieved by grinding, lapping, etching or any other suitable method. Similarly, the silicon wafer 40 is preferably thinned from an original thickness
L3, typically in the range of 400 to 1000 microns, to a decreased thickness L4, typically in the range of 10-150 microns, as shown in Fig. 3B. Alternatively, when employing a silicon on isolator process, wafer 40 may be thinned to a decreased thickness approximating 0 microns, leaving only the circuitry and pads on the active surface 24 bonded to the packaging layer plate 42. Thinning of wafer 40 may be achieved by grinding, lapping, etching or any other suitable method. As seen in Fig. 3B, wafer 40 is preferably thinned on a planar surface opposite active surface 24. This reduction in wafer thickness is enabled by the additional mechanical strength provided by the bonding thereto of plate 42. The reduction in thickness of the silicon wafer need not necessarily take place at this stage, but may take place at any suitable later stage.
Following the reduction in thickness of the chip scale packaging layer plate 42, which is optional, the chip scale packaging layer plate 42, preferably formed of silicon, is etched, using a photolithography process, along its top surface 46 along predetermined dice lines that separate the individual dies. Etched channels 52 are thus produced, which extend entirely through the thickness of the chip scale packaging layer plate 42, typically in the range of 10-250 microns, and through the bonding layer 32 as well as any other layers, such as insulation layers which may be present, thereby exposing pads 16. The etched packaged wafer, including a plurality of chip scale packaging layers 20 and a corresponding plurality of integrated circuit dies 22 bonded thereto, is shown in Fig. 3C.
The aforementioned etching typically is achieved by a dry etching process using SFO, C4F8 or other suitable dry etching gasses. Alternatively, the etching takes place in conventional silicon etching solution, such as a combination of 2.5% hydrofluoric acid,
50% nitric acid, 10% acetic acid and 37.5% water, so as to etch the chip scale packaging layer plate 42 down to the pads 16, as shown in Fig. 3C.
The result of the silicon etching is a plurality of chip scale packaging layers 20, each of which includes silicon of thickness in the range of 10-250 microns.
As seen in Fig. 3D, etched channels 52 are preferably coated with a dielectric material, such as epoxy, silicon oxide, solder mask, or any other suitable dielectric material, such as silicon nitride, silicon oxinitride, polyimide, BCB™, parylene, polynaphthalenes, fluorocarbons or accrylates. The resulting insulation layer 18 is preferably formed by spin coating, or may be formed by any suitable method, such as spray coating, curtain coating, liquid phase deposition, physical vapor deposition, chemical vapor deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, rapid thermal chemical vapor deposition or atmospheric pressure chemical vapor deposition. Following the formation of insulation layer 18, as seen in Fig. 3E, an opening 56 is formed in the insulation layer 18 between each pair of adjacent dies, by any suitable method. Openings 56 extend through insulation layer 18, thereby exposing pads 16. Fig. 3F shows the formation of a conductive layer 58, which covers insulation layer 18 and extends into openings 56. Conductive layer 58 is preferably formed of aluminum, or may be formed of any suitable conductive material or combination of materials, such as aluminum, copper, titanium, titanium tungsten, or chrome. Fig. 3G shows patterning of the conductive layer 58, typically by conventional photolithographic techniques, to define the plurality of conductors 12 which electrically contact edges of one or more pads 16 on dies 22 and are appropriately plated.
Fig. 3H shows the wafer being coated with a protective material, preferably solder mask 30 or other protective material such as parylene, BCB™, or polyamide, which is patterned to define apertures 60 therein, communicating with conductors 12.
Fig. 31 shows the formation of contact bumps, such as solder bumps 28, at apertures 60 in electrical contact with conductors 12.
In accordance with a preferred embodiment of the present invention, the wafer is then separated, as shown in Fig. 3 J, along lines 64, to provide individual integrated circuit packages, each including a single integrated circuit die 22 and being similar to integrated circuit package 10 of Figs. IA and IB.
Reference is now made to Fig. 4, which is a partially cut away, detailed, pictorial illustration of an integrally packaged integrated circuit device 10 produced from the wafer of Fig. 3 J. As seen in Fig. 4, the integrated circuit package 10 includes chip scale packaging layer 20, joined by bonding layer 32 to die 22. Surfaces of pads 16 are in electrical contact with conductors 12, which are directly formed over dielectric insulation layer 18, as described hereinabove.
Reference is now made to Figs. 5 and 6, which together illustrate apparatus for producing integrated circuit devices in accordance with a preferred embodiment of the present invention. A conventional wafer fabrication facility 180 provides wafers 40.
Individual wafers 40 are bonded on their active surfaces to chip scale packaging layer plates 42, such as silicon substrates, using bonding layer 32, by bonding apparatus 182, preferably having facilities for rotation of the wafer 40, the chip scale packaging layer plates 42 and the bonding layer 32 so as to obtain even distribution of the bonding layer 32.
The chip scale packaging layer plate 42 and optionally the wafer 40 bonded thereto (Fig. 2B) are thinned as by grinding apparatus 183, such as model BFG 841, which is commercially available from Disco Ltd. of Japan. The chip scale packaging layer plate 42 is then etched in a pattern preferably defined by using conventional photolithography techniques, such as by using conventional spin-coated photoresist as indicated by reference numeral 184. A suitable photoresist is commercially available from Hoechst, under the brand designation AZ 4562.
The photoresist is preferably mask exposed by a suitable UV exposure system 185, such as a Suss MicrTech AG, model MA200, through a lithography mask 186.
The photoresist is then developed in a development bath (not shown), baked and then the chip scale packaging layer plate is preferably etched by a dry etching process using CFe, C4Fg or other suitable dry etching gasses. Commercially available equipment for this purpose includes a dry etch machine 188 manufactured by Surface Technology
Systems of England.
Alternatively, the etching is achieved using a silicon etch solution located in a temperature . controlled bath (not shown). Commercially available equipment for this purpose includes a Chemkleen bath and a WHRV circulator both of which are manufactured by Wafab Inc. of the U.S.A. A suitable wet etching conventional silicon etching solution is Isoform Silicon etch, which is commercially available from Micro- Image Technology Ltd. of England.
The packaged wafer is conventionally rinsed after etching and photoresist stripping is performed. The resulting etched wafer is shown in Fig. 3C.
The etched channels 52 in packaging layer plate 42 are then coated with insulation layer 18, as seen in step 190 and shown in Fig. 3D. Openings are formed in the insulation layer 18, preferably by using conventional photolithography techniques, to expose pads 16, as seen in step 192 and shown in Fig. 3E. Optionally, anti-corrosion treatment may be provided as seen in step 194.
Conductive layer deposition apparatus 196, which operates by vacuum deposition techniques, such as a sputtering machine manufactured by Balzers AG of Liechtenstein, is employed to produce a conductive layer 58 (Fig. 3F) over the chip scale packaging layer plate 42. Configuration of conductors, as shown in Fig. 3 G, is carried out preferably by using conventional electro-deposited photoresist, which is commercially available from DuPont under the brand name Primecoat or from Shipley, under the brand name Eagle. The photoresist is applied to the wafers in a photoresist bath assembly 198, which is commercially available from DuPont or Shipley.
The photoresist is preferably light configured by a UV exposure system 200, using a mask 202 to define suitable etching patterns. The photoresist is then developed in a development bath 204, and then etched in a metal etch solution 206 located in an etching bath 208, thus providing a conductor configuration such as that shown in Figs.
IA and IB.
The exposed conductive strips shown in Fig. 3 G are then plated, preferably by an electroless plating apparatus 210, which is commercially available from Okuno of Japan.
Following plating of the conductive strips, the wafer is then coated with a solder mask as indicated at reference numeral 212 to define the locations 60 (Fig. 3H) of bumps 28, which are then formed in a conventional manner (Fig. 31). Alternatively, the bumps 28 may not be required. The wafer is then separated into individual pre-packaged integrated circuit devices by a dicing blade 214, as shown in Fig. 3 J. Preferably, dicing blade 214 is a diamond resinoid blade of thickness 2 - 12 mils. As a further alternative, the wafer could be separated into individual circuit devices using any other conventional method such as scribing, etching, laser and water jet. The resulting packaged dies appear as illustrated generally in Figs. IA and IB.
Reference is now made to Figs. 7A-9J, which illustrate integrated circuit devices, and the production thereof, in accordance with another preferred embodiment of the present invention. As seen in figures 7A, 7B and 1C, each integrated circuit device includes a relatively thin and compact, environmentally protected and mechanically strengthened integrated circuit package having a multiplicity of electrical conductors plated directly over an insulation layer overlying a chip scale packaging layer.
Fig. 7A shows integrated circuit package 310, having a multiplicity of electrical conductors 312. Conductors 312 are electrically connected to pads 316, and are preferably formed directly over an insulation layer 318 overlying at least one chip scale packaging layer 320 overlying an integrated circuit die 322 having an active surface 324. Alternatively insulation layer 318 may be partially or entirely obviated. Insulation layer 318 may be any suitable insulation layer, such as a dielectric layer or a passivation layer. Pads 316 are connected to circuitry on the active surface 324. Preferably the chip scale packaging layer 320 is formed of a crystalline material, most preferably silicon. As a further alternative, the chip scale packaging layer 320 is formed of at least one of metal, plastic, thermoplastic, thermosetting and ceramic. Conductors 312 extend over edge surfaces 325 onto a planar surface 326 of the insulation layer 318. This contact arrangement permits flat surface mounting of package 310 onto a circuit board. Integrated circuit package 310 may also include contact bumps, such as solder bumps 328 formed on electrical conductors 312, at apertures formed in a solder mask 330 formed over insulation layer 318 and packaging layer 320. The integrated circuit package 310 also preferably includes a bonding layer 332, used to attach packaging layer 320 to integrated circuit die 322. Bonding layer 332 may include one or more of an adhesive such as epoxy or polyurethane, intermetallic bonding such as solder and anodic bonding.
The embodiment of Fig. 7A is particularly characterized in that chip scale packaging layer 320 is formed with a recess 334 overlying the active surface 324 of the die 322.
Fig. 7B shows integrated circuit package 350, having a multiplicity of electrical conductors 352. Conductors 352 are electrically connected to pads 356, and are preferably formed directly over an insulation layer 358 overlying at least one chip scale packaging layer 360 overlying an integrated circuit die 362 having an active surface 364. Alternatively insulation layer 358 may be partially or entirely obviated. Insulation layer 358 may be any suitable insulation layer, such as a dielectric layer or a passivation layer. Pads 356 are connected to circuitry on the active surface 364. Preferably the chip scale packaging layer 360 is formed of a crystalline material, most preferably silicon. As a further alternative, the chip scale packaging layer 360 is formed of at least one of metal, plastic, thermoplastic, thermosetting and ceramic.
Conductors 352 extend over edge surfaces 365 onto a planar surface 366 of the package 350. This contact arrangement permits flat surface mounting of package 350 onto a circuit board. Integrated circuit package 350 may also include contact bumps, such as solder bumps 368 formed on electrical conductors 352, at apertures formed in a solder mask 370 formed over insulation layer 358 and packaging layer 360. The integrated circuit package 350 also preferably includes a bonding layer 372, used to attach packaging layer 360 to integrated circuit die 362. Bonding layer 372 may be one or more of an adhesive such as epoxy or polyurethane, intermetallic bonding such as solder and anodic bonding.
The embodiment of Fig. 7B is particularly characterized in that chip scale packaging layer 360 is formed with a recess 374 overlying the active surface 364 of the die 362 and that die 362 is formed with an opening 376 communicating with recess 374. An additional protective layer 378, typically formed of glass, is preferably attached to the underside of die 362, preferably in a waferwise manner prior to separating. Protective layer 378 may be formed of silicon, glass, metal, plastic, thermoplastic, thermosetting, ceramic, any combination thereof, or any other suitable material. Preferably, integrated circuit package 350 also includes a bonding layer 380, used to attach additional protective layer 378 to die 362. Bonding layer 380 may be one or more of an adhesive such as epoxy or polyurethane, intermetallic bonding such as solder and anodic bonding. In another preferred embodiment of the present invention, protective layer 378 is preferably thinned from an original thickness, typically in the range of 400 to 1000 microns, to a decreased thickness, typically in the range of 10-250 microns. Thinning of protective layer 378 may be achieved by grinding, lapping, etching or any other suitable method. Fig. 7C shows integrated circuit package 390, having a multiplicity of electrical conductors 392. Conductors 392 are electrically connected to pads 396, and are preferably formed directly over an insulation layer 398 overlying at least one chip scale packaging layer 400 overlying an integrated circuit die 402 having an active surface 404. Alternatively insulation layer 398 may be partially or entirely obviated. Insulation layer 398 may be any suitable insulation layer, such as a dielectric layer or a passivation layer. Pads 396 are connected to circuitry on the active surface 404. Preferably the chip scale packaging layer 400 is formed of a crystalline material, most preferably silicon. As a further alternative, the chip scale packaging layer 400 is formed of at least one of metal, plastic, thermoplastic, thermosetting and ceramic. Conductors 392 extend over edge surfaces 405 onto a planar surface 406 of the insulation layer 398. This contact arrangement permits flat surface mounting of package 390 onto a circuit board. Integrated circuit package 390 may also include contact bumps, such as solder bumps 408 formed on electrical conductors 392, at apertures formed in a solder mask 410 formed over insulation layer 398 and packaging layer 400. The integrated circuit package 390 also preferably includes a bonding layer 412, used to attach packaging layer 400 to integrated circuit die 402. Bonding layer 412 may include one or more of an adhesive such as epoxy or polyurethane, intermetallic bonding such as solder and anodic bonding.
The embodiment of Fig. 7C is particularly characterized in that chip scale packaging layer 400 is formed with multiple recesses 414 overlying the active surface 404 of the die 402. It is appreciated that the methods described hereinbelow provide integrated circuit packages 310, 350 and 390 that are in the range defined as chip scale packages, typically no more than 20% larger in area than the size of the chip. It is also appreciated that the methods described hereinbelow provide integrated circuit packages 310, 350 and 390 in which the packaging process is carried out at wafer level up to separating of a wafer-wise package into separate packaged dies.
Figs. 8A and 8B are simplified pictorial illustrations of the attachment of a protective insulating chip scale packaging layer plate to a wafer, preferably formed of silicon and containing a plurality of integrated circuit dies in accordance with the present invention. As seen in Figs. 8A and 8B, typically a silicon wafer 340 has a plurality of finished dies 322 formed thereon by conventional techniques, and is bonded at active surfaces 324 of dies 322 onto a chip scale packaging layer plate 342.
In accordance with a preferred embodiment of the present invention, as illustrated in Fig. 9A, wafer 540 having a plurality of finished dies 522 formed thereon by conventional techniques, is bonded at active surfaces 524 to plate 542 by bonding layer 532. Preferably, plate 542 includes multiple recesses 534, which are aligned to dies 522 before plate 542 is bonded to wafer 540. Bonding layer 532 may include one or more of an adhesive such as epoxy or polyurethane, intermetallic bonding such as solder and anodic bonding. Alternatively, bonding layer 532 may include any other suitable bonding material. As seen in Fig. 9A, electrical pads 516 are formed on the active surfaces 524 defined on wafer 540.
It is appreciated that certain steps in the conventional fabrication of silicon wafer 540 may be eliminated when the wafer is used in accordance with the present invention. These steps include the provision of via openings above pads, wafer back grinding and wafer back metal coating.
Following the bonding step described hereinabove, chip scale packaging layer plate 542 is preferably thinned from an original thickness Ll, typically in the range of 400 to 1000 microns, to a decreased thickness L2, typically in the range of 10-250 microns, as shown in Fig. 9B. Thinning of chip scale packaging layer plate 542 may be achieved by grinding, lapping, etching or any other suitable method.
Similarly, the silicon wafer 540 is preferably thinned from an original thickness L3, typically in the range of 400 to 1000 microns, to a decreased thickness L4, typically in the range of 10-150 microns, as shown in Fig. 9B. Alternatively, when employing a silicon on isolator process, wafer 540 may be thinned to a decreased thickness approximating 0 microns, leaving only the circuitry and pads on the active surface 524 bonded to the packaging layer plate 542. Thinning of wafer 540 may be achieved by grinding, lapping, etching or any other suitable method. As seen in Fig. 9B, wafer 540 is preferably thinned on a planar surface opposite active surface 524. This reduction in wafer thickness is enabled by the additional mechanical strength provided by the bonding thereto of plate 542. The reduction in thickness of the silicon wafer need not necessarily take place at this stage, but may take place at any suitable later stage.
Following the reduction in thickness of the chip scale packaging layer plate 542, which is optional, the chip scale packaging layer plate 542, preferably formed of silicon, is etched, using a photolithography process, along its top surface 546 along predetermined dice lines that separate the individual dies. Etched channels 552 are thus produced, which extend entirely through the thickness of the chip scale packaging layer plate 542, typically in the range of 10-250 microns, and through the bonding layer 532 as well as any other layers, such as insulation layers which may be present, thereby exposing pads 516. The etched packaged wafer, including a plurality of chip scale packaging layers 520 each including at least one recess 534, and a corresponding plurality of integrated circuit dies 522 bonded thereto, is shown in Fig. 9C.
The aforementioned etching typically is achieved by a dry etching process using SF6, C4Fg or other suitable dry etching gasses. Alternatively, the etching takes place in conventional silicon etching solution, such as a combination of 2.5% hydrofluoric acid, 50% nitric acid, 10% acetic acid and 37.5% water, so as to etch the chip scale packaging layer plate 542 down to the pads 516, as shown in Fig. 9C.
The result of the silicon etching is a plurality of chip scale packaging layers 520, each of which includes silicon of thickness in the range of 10-250 microns.
As seen in Fig. 9D, etched channels 552 are preferably coated with a dielectric material, such as epoxy, silicon oxide, solder mask, or any other suitable dielectric material, such as silicon nitride, silicon oxinitride, polyimide, BCB™, parylene, polynaphthalenes, fluorocarbons or accrylates. The resulting insulation layer 518 is preferably formed by spin coating, or may be formed by any suitable method, such as spray coating, curtain coating, liquid phase deposition, physical vapor deposition, chemical vapor deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, rapid thermal chemical vapor deposition or atmospheric pressure chemical vapor deposition.
Following the formation of insulation layer 518, as seen in Fig. 9E, an opening 556 is formed in the insulation layer 518 between each pair of adjacent dies, by any suitable method. Openings 556 extend through insulation layer 518, thereby exposing pads 516.
Fig. 9F shows the formation of a conductive layer 558, which covers insulation layer 518 and extends into openings 556. Conductive layer 558 is preferably formed of aluminum, or may be formed of any suitable conductive material or combination of materials, such as aluminum, copper, titanium, titanium tungsten, or chrome.
Fig. 9G shows patterning of the conductive layer 558, typically by conventional photolithographic techniques, to define the plurality of conductors 512 which electrically contact edges of one or more pads 516 on dies 522 and are appropriately plated. Fig. 9H shows the wafer being coated with a protective material, preferably solder mask 530 or other protective material such as parylene, BCB™, or polyamide, which is patterned to define apertures 560 therein, communicating with conductors 512.
Fig. 91 shows the formation of contact bumps, such as solder bumps 528, at apertures 560 in electrical contact with conductors 512. In accordance with a preferred embodiment of the present invention, the wafer is then separated, as shown in Fig. 9 J, along lines 564, to provide individual integrated circuit packages, each including a single integrated circuit die 522 and at least one recess 534, and being similar to one of integrated circuit packages 310, 350 and 390 of Figs. 7A, 7B and 7C.
Reference is now made to Fig. 10, which is a partially cut away, detailed, pictorial illustration of an integrally packaged integrated circuit device 510 produced from the wafer of Fig. 9 J. As seen in Fig. 10, the integrated circuit package 510 includes chip scale packaging layer 520 including at least one recess 534, joined by bonding layer 532 to die 522. Surfaces of pads 516 are in electrical contact with conductors 512, which are directly formed over dielectric insulation layer 518, as described hereinabove.
Reference is now made to Figs. 11 and 12, which together illustrate apparatus for producing integrated circuit devices in accordance with a preferred embodiment of the present invention. A conventional wafer fabrication facility 580 provides wafers 540.
Individual wafers 540 are aligned to chip scale packaging layers 542 such as silicon substrates, and then bonded on their active surfaces to chip scale packaging layer plates
542, using bonding layer 532, by bonding apparatus 582, preferably having facilities for rotation of the wafer 540, the chip scale packaging layer plates 542 and the bonding layer 532 so as to obtain even distribution of the bonding layer 532.
The chip scale packaging layer plate 542 and optionally the wafer 540 bonded thereto (Fig. 8B) are thinned as by grinding apparatus 583, such as model BFG 841, which is commercially available from Disco Ltd. of Japan. The chip scale packaging layer plate 542 is then etched in a pattern preferably defined by using conventional photolithography techniques, such as by using conventional spin-coated photoresist as indicated by reference numeral 584. A suitable photoresist is commercially available from Hoechst, under the brand designation AZ 4562.
The photoresist is preferably mask exposed by a suitable UV exposure system 585, such as a Suss MicrTech AG, model MA200, through a lithography mask 586.
The photoresist is then developed in a development bath (not shown), baked and then the chip scale packaging layer plate is preferably etched by a dry etching process using SFO, C4Fs or other suitable dry etching gasses. Commercially available equipment for this purpose includes a dry etch machine 588 manufactured by Surface Technology Systems of England.
Alternatively, the etching is achieved using a silicon etch solution located in a temperature controlled bath (not shown). Commercially available equipment for this purpose includes a Chemkleen bath and a WHRV circulator both of which are manufactured by Wafab Inc. of the U.S.A. A suitable wet etching conventional silicon etching solution is Isoform Silicon etch, which is commercially available from Micro- Image Technology Ltd. of England. The packaged wafer is conventionally rinsed after etching and photoresist stripping is performed. The resulting etched wafer is shown in Fig. 9C.
The etched channels 552 in packaging layer plate 542 are then coated with insulation layer 518, as seen in step 590 and shown in Fig. 9D. Openings are formed in the insulation layer 518, preferably by using conventional photolithography techniques, to expose pads 516, as seen in step 592 and shown in Fig. 9E. Optionally, anti-corrosion treatment may be provided as seen in step 594.
Conductive layer deposition apparatus 596, which operates by vacuum deposition techniques, such as a sputtering machine manufactured by Balzers AG of Liechtenstein, is employed to produce a conductive layer 558 (Fig. 9F) over the chip scale packaging layer plate 542.
Configuration of conductors, as shown in Fig. 9G, is carried out preferably by using conventional electro-deposited photoresist, which is commercially available from
DuPont under the brand name Primecoat or from Shipley, under the brand name Eagle.
The photoresist is applied to the wafers in a photoresist bath assembly 598, which is commercially available from DuPont or Shipley.
The photoresist is preferably light configured by a LJV exposure system 600, using a mask 602 to define suitable etching patterns. The photoresist is then developed in a development bath 604, and then etched in a metal etch solution 606 located in an etching bath 608, thus providing a conductor configuration such as that shown in Figs. 7A, 7B and 1C.
The exposed conductive strips shown in Fig. 9G are then plated, preferably by an electroless plating apparatus 610, which is commercially available from Okuno of Japan.
Following plating of the conductive strips, the wafer is then coated with a solder mask as indicated at reference numeral 612 to define the locations 560 (Fig. 9H) of bumps 528, which are then formed in a conventional manner (Fig. 91). Alternatively, the bumps 528 may not be required. The wafer is then separated into individual pre-packaged integrated circuit devices by a dicing blade 614, as shown in Fig. 9 J. Preferably, dicing blade 614 is a diamond resinoid blade of thickness 2 - 12 mils. As a further alternative, the wafer could be separated into individual circuit devices using any other conventional method such as scribing, etching, laser and water jet. The resulting packaged dies appear as illustrated generally in Figs. 7A, 7B and 7C.
Reference is now made to Figs. 13A - 15 J, which illustrate integrated circuit devices, and the production thereof, in accordance with a preferred embodiment of the present invention. As seen in Figs. 13A and 13B, the integrated circuit device includes a relatively thin and compact, environmentally protected and mechanically strengthened, integrated circuit package 710, having a multiplicity of electrical conductors 712.
It is a particular feature of the present invention that conductors 712 are electrically connected to pads 716, and are preferably formed directly over an insulation layer 718 overlying an integrated circuit die 722 having an active surface 724, without there being an intervening packaging layer, such as a glass layer. Alternatively insulation layer 718 may be partially or entirely obviated. Insulation layer 718 may be any suitable insulation layer, such as a dielectric layer or a passivation layer. Pads 716 are connected to circuitry on the active surface 724.
In accordance with a preferred embodiment of the invention, conductors 712 extend over edge surfaces 725 onto a planar surface 726 of the insulation layer 718. This contact arrangement permits flat surface mounting of package 710 onto a circuit board. As seen in Figs. 13A and 13B, integrated circuit package 710 may also include contact bumps, such as solder bumps 728 formed on electrical conductors 712, at apertures formed in a solder mask 730 formed over insulation layer 718. As a further alternative, as shown in Figs 13C and 13D, the conductors 712 do not extend beyond edge surfaces 725 onto planar surface 726 or extend onto planar surface 726 only to a limited extent, thereby defining peripheral contacts.
The integrated circuit device preferably includes a chip scale packaging layer 720, which is formed of a crystalline material, most preferably silicon. As a further alternative, the chip scale packaging layer 720 is formed of at least one of metal, plastic, thermoplastic, thermosetting and ceramic.
The integrated circuit package 710, shown in Figs. 13A and 13B, also includes a bonding layer 732, used to attach packaging layer 720 to integrated circuit die 722, as described hereinbelow.
It is appreciated that the methods described hereinbelow provide integrated circuit packages 710 that are in the range defined as chip scale packages, typically no more than 20% larger in area than the size of the chip. It is also appreciated that the methods described hereinbelow provide integrated circuit packages 710 in which the packaging process is carried out at wafer level up to separating of a wafer-wise package into separate packaged dies.
Figs. 14A and 14B are simplified pictorial illustrations of the attachment of a protective insulating chip scale packaging layer plate to a wafer, preferably formed of silicon and containing a plurality of integrated circuit dies in accordance with the present invention. As seen in Figs. 14A and 14B, typically a silicon wafer 740 has a plurality of finished dies 722 formed thereon by conventional techniques, and is bonded at active surfaces 724 of dies 722 onto a chip scale packaging layer plate 742. In accordance with a preferred embodiment of the present invention, as illustrated in Fig. 15 A, wafer 740, having a plurality of finished dies 722 formed thereon by conventional techniques, is bonded at active surfaces 724 to plate 742 by bonding layer
732. Bonding layer 732 may include one or more of an adhesive such as epoxy or polyurethane, intermetallic bonding such as solder and anodic bonding. Alternatively, bonding layer 732 may include any other suitable bonding material. As seen in Fig.
15A, electrical pads 716 are formed on the active surfaces 724 defined on wafer 740.
It is appreciated that certain steps in the conventional fabrication of silicon wafer 740 may be eliminated when the wafer is used in accordance with the present invention. These steps include the provision of via openings above pads, wafer back grinding and wafer back metal coating.
Following the bonding step described hereinabove, chip scale packaging layer plate 742 is preferably thinned from an original thickness Ll, typically in the range of 400 to 1000 microns, to a decreased thickness L2, typically in the range of 10-250 microns, as shown in Fig. 15B. Thinning of chip scale packaging layer plate 742 may be achieved by grinding, lapping, etching or any other suitable method. The reduction in thickness of the packaging layer need not necessarily take place at this stage, but may take place at any suitable later stage. Similarly, the silicon wafer 740 is preferably thinned from an original thickness L3, typically in the range of 400 to 1000 microns, to a decreased thickness L4, typically in the range of 10-150 microns, as shown in Fig. 15B. Alternatively, when employing a silicon on isolator process, wafer 740 may be thinned to a decreased thickness approximating 0 microns, leaving only the circuitry and pads on the active surface 724 bonded to the packaging layer plate 742. Thinning of wafer 740 may be achieved by grinding, lapping, etching or any other suitable method. As seen in Fig. 15B, wafer 740 is preferably thinned on a planar surface opposite active surface 724. This reduction in wafer thickness is enabled by the additional mechanical strength provided by the bonding thereto of plate 742.
Following the reduction in thickness of the wafer 740, which is optional, the wafer 740, is etched, using a photolithography process, along its top surface 746 along predetermined dice lines that separate the individual dies. Etched channels 752 are thus produced, which extend entirely through the thickness of the wafer 740, typically in the range of 10-250 microns, thereby exposing pads 716. The etched packaged wafer, including packaging layer plate 742 which will be separated into a plurality of chip scale packaging layers, and a corresponding plurality of integrated circuit dies 722 bonded thereto, is shown in Fig. 15C.
The aforementioned etching typically is achieved by a dry etching process using SFβ, C4F8 or other suitable dry etching gasses. Alternatively, the etching takes place in conventional silicon etching solution, such as a combination of 2.5% hydrofluoric acid, 50% nitric acid, 10% acetic acid and 37.5% water, so as to etch the wafer 740 down to pads 716, as shown in Fig. 15C.
The result of the silicon etching is a plurality of integrated circuit dies 722, each of which includes silicon of thickness in the range of 10-250 microns.
As seen in Fig. 15D, etched channels 752 are preferably coated with a dielectric material, such as epoxy, silicon oxide, solder mask, or any other suitable dielectric material, such as silicon nitride, silicon oxinitride, polyimide, BCB™, parylene, polynaphthalenes, fluorocarbons or accrylates. The resulting insulation layer 718 is preferably formed by spin coating, or may be formed by any suitable method, such as spray coating, curtain coating, liquid phase deposition, physical vapor deposition, chemical vapor deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, rapid thermal chemical vapor deposition or atmospheric pressure chemical vapor deposition.
Following the formation of insulation layer 718, as seen in Fig. 15E, an opening 756 is formed in the insulation layer 718 between each pair of adjacent dies, by any suitable method. Openings 756 extend through insulation layer 718, thereby exposing pads 716.
Fig. 15F shows the formation of a conductive layer 758, which covers insulation layer 718 and extends into openings 756. Conductive layer 758 is preferably formed of aluminum, or may be formed of any suitable conductive material or combination of materials, such as aluminum, copper, titanium, titanium tungsten, or chrome.
Fig. 15G shows patterning of the conductive layer 758, typically by conventional photolithographic techniques, to define the plurality of conductors 712 which electrically contact edges of one or more pads 716 on dies 722 and are appropriately plated. Fig. 15H shows the wafer being coated with a protective material, preferably solder mask 730 or other protective material such as parylene, BCB™, or polyamide, which is patterned to define apertures 760 therein, communicating with conductors 712.
Fig. 151 shows the formation of contact bumps, such as solder bumps 728, at apertures 760 in electrical contact with conductors 712. In accordance with a preferred embodiment of the present invention, the packaging layer plate is then separated, as shown in Fig. 15 J, along lines 764, to provide individual integrated circuit packages, each including a single integrated circuit die 722 and a single chip scale packaging layer 720 and being similar to integrated circuit package 710 of Figs. 13 A and 13B . Reference is now made to Fig. 16, which is a partially cut away, detailed, pictorial illustration of an integrally packaged integrated circuit device 710 produced from the wafer of Fig. 15 J. As seen in Fig. 16, the integrated circuit package 710 includes chip scale packaging layer 720, joined by bonding layer 732 to die 722. Surfaces of pads 716 are in electrical contact with conductors 712, which are directly formed over dielectric insulation layer 718, as described hereinabove.
Reference is now made to Figs. 17 and 18, which together illustrate apparatus for producing integrated circuit devices in accordance with a preferred embodiment of the present invention. A conventional wafer fabrication facility 880 provides wafers 740. Individual wafers 740 are bonded on their active surfaces to chip scale packaging layer plates 742, such as silicon substrates, using bonding layer 732, by bonding apparatus 882, preferably having facilities for rotation of the wafer 740, the chip scale packaging layer plates 742 and the bonding layer 732 so as to obtain even distribution of the bonding layer 732.
The chip scale packaging layer plate 742 and optionally the wafer 740 bonded thereto (Fig. 14B) are thinned as by grinding apparatus 883, such as model BFG 841, which is commercially available from Disco Ltd. of Japan. The wafer 740 is then etched in a pattern preferably defined by using conventional photolithography techniques, such as by using conventional spin-coated photoresist as indicated by reference numeral 884. A suitable photoresist is commercially available from Hoechst, under the brand designation AZ 4562.
The photoresist is preferably mask exposed by a suitable UV exposure system 885, such as a Suss MicrTech AG, model MA200, through a lithography mask 886.
The photoresist is then developed in a development bath (not shown), baked and then the wafer is preferably etched by a dry etching process using SF6, C4F8 or other suitable dry etching gasses. Commercially available equipment for this purpose includes a dry etch machine 888 manufactured by Surface Technology Systems of England. Alternatively, the etching is achieved using a silicon etch solution located in a temperature controlled bath (not shown). Commercially available equipment for this purpose includes a Chemkleen bath and a WHRV circulator both of which are manufactured by Wafab Inc. of the U.S. A. A suitable wet etching conventional silicon etching solution is Isoform Silicon etch, which is commercially available from Micro- Image Technology Ltd. of England.
The packaged wafer is conventionally rinsed after etching and photoresist stripping is performed. The resulting etched wafer is shown in Fig. 15C.
The etched channels 752 in wafer 740 are then coated with insulation layer 718, as seen in step 890 and shown in Fig. 15D. Openings are formed in the insulation layer 718, preferably by using conventional photolithography techniques, to expose pads 716, as seen in step 892 and shown in Fig. 15E. Optionally, anti-corrosion treatment may be provided as seen in step 894. Conductive layer deposition apparatus 896, which operates by vacuum deposition techniques, such as a sputtering machine manufactured by Balzers AG of Liechtenstein, is employed to produce a conductive layer 758 (Fig. 15F) over the wafer 740.
Configuration of conductors, as shown in Fig. 15G, is carried out preferably by using conventional electro-deposited photoresist, which is commercially available from
DuPont under the brand name Primecoat or from Shipley, under the brand name Eagle.
The photoresist is applied to the wafers in a photoresist bath assembly 898, which is commercially available from DuPont or Shipley.
The photoresist is preferably light configured by a UV exposure system 900, using a mask 902 to define suitable etching patterns. The photoresist is then developed in a development bath 904, and then etched in a metal etch solution 906 located in an etching bath 908, thus providing a conductor configuration such as that shown in Figs.
13A and 13B.
The exposed conductive strips shown in Fig. 15G are then plated, preferably by an electroless plating apparatus 910, which is commercially available from Okuno of Japan.
Following plating of the conductive strips, the wafer is then coated with a solder mask as indicated at reference numeral 912 to define the locations 760 (Fig. 15ET) of bumps 728, which are then formed in a conventional manner (Fig. 151). Alternatively, the bumps 728 may not be required.
The wafer is then separated into individual pre-packaged integrated circuit devices by a dicing blade 914, as shown in Fig. 15J. Preferably, dicing blade 914 is a diamond resinoid blade of thickness 2 - 12 mils. As a further alternative, the wafer could be separated into individual circuit devices using any other conventional method such as scribing, etching, laser and water jet. The resulting packaged dies appear as illustrated generally in Figs. 13 A and 13B.
Reference is now made to Figs. 19A-21J, which illustrate integrated circuit devices, and the production thereof, in accordance with another preferred embodiment of the present invention. As seen in figures 19A and 19B, each integrated circuit device includes a relatively thin and compact, environmentally protected and mechanically strengthened integrated circuit package having a multiplicity of electrical conductors plated directly over an insulation layer overlying circuit die. Fig. 19A shows integrated circuit package 1010, having a multiplicity of electrical conductors 1012. Conductors 1012 are electrically connected to pads 1016, and are preferably formed directly over an insulation layer 1018 overlying an integrated circuit die 1022 having an active surface 1024. Alternatively insulation layer 1018 may be partially or entirely obviated. Insulation layer 1018 may be any suitable insulation layer, such as a dielectric layer or a passivation layer. Pads 1016 are connected to circuitry on the active surface 1024.
Conductors 1012 extend over edge surfaces 1025 onto a planar surface 1026 of the insulation layer 1018. This contact arrangement permits flat surface mounting of package 1010 onto a circuit board. Integrated circuit package 1010 may also include contact bumps, such as solder bumps 1028 formed on electrical conductors 1012, at apertures formed in a solder mask 1030 formed over insulation layer 1018.
The integrated circuit device preferably includes a chip scale packaging layer 1020, which is formed of a crystalline material, most preferably silicon. As a further alternative, the chip scale packaging layer 1020 is formed of at least one of metal, plastic, thermoplastic, thermosetting and ceramic.
The integrated circuit package 1010 also preferably includes a bonding layer 1032, used to attach packaging layer 1020 to integrated circuit die 1022. Bonding layer 1032 may include one or more of an adhesive such as epoxy or polyurethane, intermetallic bonding such as solder and anodic bonding.
The embodiment of Fig. 19A is particularly characterized in that chip scale packaging layer 1020 is formed with a recess 1034 overlying the active surface 1024 of the die 1022.
Fig. 19B shows integrated circuit package 1050, having a multiplicity of electrical conductors 1052. Conductors 1052 are electrically connected to pads 1056, and are preferably formed directly over an insulation layer 1058 overlying an integrated circuit die 1062 having an active surface 1064. Alternatively insulation layer 1058 may be partially or entirely obviated. Insulation layer 1058 may be any suitable insulation layer, such as a dielectric layer or a passivation layer. Pads 1056 are connected to circuitry on the active surface 1064.
Conductors 1052 extend over edge surfaces 1065 onto a planar surface 1066 of the insulation layer 1058. This contact arrangement permits flat surface mounting of package 1050 onto a circuit board. Integrated circuit package 1050 may also include contact bumps, such as solder bumps 1068 formed on electrical conductors 1052, at apertures formed in a solder mask 1070 formed over insulation layer 1058.
The integrated circuit device 1050 preferably includes a chip scale packaging layer 1060, which is formed of a crystalline material, most preferably silicon. As a further alternative, the chip scale packaging layer 1060 is formed of at least one of metal, plastic, thermoplastic, thermosetting and ceramic.
The integrated circuit package 1050 also preferably includes a bonding layer 1072, used to attach packaging layer 1060 to integrated circuit die 1062. Bonding layer 1072 may include one or more of an adhesive such as epoxy or polyurethane, intermetallic bonding such as solder and anodic bonding.
The embodiment of Fig. 19B is particularly characterized in that chip scale packaging layer 1060 is formed with multiple recesses 1074 overlying the active surface 1064 of the die 1062. It is appreciated that the methods described hereinbelow provide integrated circuit packages 1010 and 1050 that are in the range defined as chip scale packages, typically no more than 20% larger in area than the size of the chip. It is also appreciated that the methods described hereinbelow provide integrated circuit packages 1010 and 1050 in which the packaging process is carried out at wafer level up to separating of a wafer- wise package into separate packaged dies.
Figs. 2OA and 2OB are simplified pictorial illustrations of the attachment of a protective insulating chip scale packaging layer plate to a wafer, preferably formed of silicon and containing a plurality of integrated circuit dies in accordance with the present invention. As seen in Figs. 2OA and 2OB, typically a silicon wafer 1040 has a plurality of finished dies 1022 formed thereon by conventional techniques, and is bonded at active surfaces 1024 of dies 1022 onto a chip scale packaging layer plate 1042.
In accordance with a preferred embodiment of the present invention, as illustrated in Fig. 21A, wafer 1240, having a plurality of finished dies 1222 formed thereon by conventional techniques, is bonded at active surfaces 1224 to plate 1242 by bonding layer 1232. Preferably, plate 1242 includes multiple recesses 1234, which are aligned to dies 1222 before plate 1242 is bonded to wafer 1240. Bonding layer 1232 may include one or more of an adhesive such as epoxy or polyurethane, intermetallic bonding such as solder and anodic bonding. Alternatively, bonding layer 1232 may include any other suitable bonding material. As seen in Fig. 21A, electrical pads 1216 are formed on the active surfaces 1224 defined on wafer 1240. It is appreciated that certain steps in the conventional fabrication of silicon wafer
1240 may be eliminated when the wafer is used in accordance with the present invention. These steps include the provision of via openings above pads, wafer back grinding and wafer back metal coating.
Following the bonding step described hereinabove, chip scale packaging layer plate 1242 is preferably thinned from an original thickness Ll, typically in the range of 400 to 1000 microns, to a decreased thickness L2, typically in the range of 10-250 microns, as shown in Fig. 2 IB. Thinning of chip scale packaging layer plate 1242 may be achieved by grinding, lapping, etching or any other suitable method. The reduction in thickness of the chip scale packaging layer need not necessarily take place at this stage, but may take place at any suitable later stage.
Similarly, the silicon wafer 1240 is preferably thinned from an original thickness L3, typically in the range of 400 to 1000 microns, to a decreased thickness L4, typically in the range of 10-150 microns, as shown in Fig. 2 IB. Alternatively, when employing a silicon on isolator process, wafer 1240 may be thinned to a decreased thickness approximating 0 microns, leaving only the circuitry and pads on the active surface 1224 bonded to the packaging layer plate 1242. Thinning of wafer 1240 may be achieved by grinding, lapping, etching or any other suitable method. As seen in Fig. 2 IB, wafer 1240 is preferably thinned on a planar surface opposite active surface 1224. This reduction in wafer thickness is enabled by the additional mechanical strength provided by the bonding thereto of plate 1242.
Following the reduction in thickness of the wafer 1240, which is optional, the wafer 1240, is etched, using a photolithography process, along its top surface 1246 along predetermined dice lines that separate the individual dies. Etched channels 1252 are thus produced, which extend entirely through the thickness of the wafer 1240, typically in the range of 10-250 microns, thereby exposing pads 1216. The etched packaged wafer, including packaging layer plate 1242 which will be separated into a plurality of chip scale packaging layers 1220, each including at least one recess 1234, and a corresponding plurality of integrated circuit dies 1222 bonded thereto, is shown in Fig. 21C.
The aforementioned etching typically is achieved by a dry etching process using
SFΘ, C4Fg or other suitable dry etching gasses. Alternatively, the etching takes place in conventional silicon etching solution, such as a combination of 2.5% hydrofluoric acid,
50% nitric acid, 10% acetic acid and 37.5% water, so as to etch the wafer 1240 down to pads 1216, as shown in Fig. 21C.
The result of the silicon etching is a plurality of integrated circuit dies 1222, each of which includes silicon of thickness in the range of 10-250 microns. As seen in Fig. 21D, etched channels 1252 are preferably coated with a dielectric material, such as epoxy, silicon oxide, solder mask, or any other suitable dielectric material, such as silicon nitride, silicon oxinitride, polyimide, BCB™, parylene, polynaphthalenes, fluorocarbons or accrylates. The resulting insulation layer 1218 is preferably formed by spin coating, or may be formed by any suitable method, such as spray coating, curtain coating, liquid phase deposition, physical vapor deposition, chemical vapor deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, rapid thermal chemical vapor deposition or atmospheric pressure chemical vapor deposition.
Following the formation of insulation layer 1218, as seen in Fig. 21E, an opening 1256 is formed in the insulation layer 1218 between each pair of adjacent dies, by any suitable method. Openings 1256 extend through insulation layer 1218, thereby exposing pads 1216.
Fig. 2 IF shows the formation of a conductive layer 1258, which covers insulation layer 1218 and extends into openings 1256. Conductive layer 1258 is preferably formed of aluminum, or may be formed of any suitable conductive material or combination of materials, such as aluminum, copper, titanium, titanium tungsten, or chrome.
Fig. 21G shows patterning of the conductive layer 1258, typically by conventional photolithographic techniques, to define the plurality of conductors 1212 which electrically contact edges of one or more pads 1216 on dies 1222 and are appropriately plated.
Fig. 2 IH shows the wafer being coated with a protective material, preferably solder mask 1230 or other protective material such as parylene, BCB™, or polyamide, which is patterned to define apertures 1260 therein, communicating with conductors 1212.
Fig. 211 shows the formation of contact bumps, such as solder bumps 1228, at apertures 1260 in electrical contact with conductors 1212. In accordance with a preferred embodiment of the present invention, the packaging layer plate is then separated, as shown in Fig. 21J, along lines 1264, to provide individual integrated circuit packages, each including a single integrated circuit die 1222 and at least one recess 1234, and being similar to one of integrated circuit packages 1010, 1050 and 1090 of Figs. 19A and 19B. Reference is now made to Fig. 22, which is a partially cut away, detailed, pictorial illustration of an integrally packaged integrated circuit device 1210 produced from the wafer of Fig. 2 IJ. As seen in Fig. 22, the integrated circuit package 1210 includes chip scale packaging layer 1220 including at least one recess 1234, joined by bonding layer 1232 to die 1222. Surfaces of pads 1216 are in electrical contact with conductors 1212, which are directly formed over dielectric insulation layer 1218, as described hereinabove.
Reference is now made to Figs. 23 and 24, which together illustrate apparatus for producing integrated circuit devices in accordance with a preferred embodiment of the present invention. A conventional wafer fabrication facility 1280 provides wafers 1240. Individual wafers 1240 are aligned to chip scale packaging layers 1242 such as silicon substrates, and then bonded on their active surfaces to chip scale packaging layer plates 1242, using bonding layer 1232, by bonding apparatus 1282, preferably having facilities for rotation of the wafer 1240, the chip scale packaging layer plates 1242 and the bonding layer 1232 so as to obtain even distribution of the bonding layer 1232. The chip scale packaging layer plate 1242 and optionally the wafer 1240 bonded thereto (Fig. 20B) are thinned as by grinding apparatus 1283, such as model BFG 841, which is commercially available from Disco Ltd. of Japan. The wafer 1240 is then etched in a pattern preferably defined by using conventional photolithography techniques, such as by using conventional spin-coated photoresist as indicated by reference numeral 1284. A suitable photoresist is commercially available from Hoechst, under the brand designation AZ 4562.
The photoresist is preferably mask exposed by a suitable UV exposure system 1285, such as a Suss MicrTech AG, model MA200, through a lithography mask 1286.
The photoresist is then developed in a development bath (not shown), baked and then the wafer is preferably etched by a dry etching process using SF6, C4Fg or other suitable dry etching gasses. Commercially available equipment for this purpose includes a dry etch machine 1288 manufactured by Surface Technology Systems of England.
Alternatively, the etching is achieved using a silicon etch solution located in a temperature controlled bath (not shown). Commercially available equipment for this purpose includes a Chemkleen bath and a WHRV circulator both of which are manufactured by Wafab Inc. of the U.S.A. A suitable wet etching conventional silicon etching solution is Isoform Silicon etch, which is commercially available from Micro- Image Technology Ltd. of England.
The packaged wafer is conventionally rinsed after etching and photoresist stripping is performed. The resulting etched wafer is shown in Fig. 21 C.
The etched channels 1252 in wafer 1240 are then coated with insulation layer 1218, as seen in step 1290 and shown in Fig. 21D. Openings are formed in the insulation layer 1218, preferably by using conventional photolithography techniques, to expose pads 1216, as seen in step 1292 and shown in Fig. 21E. Optionally, anti- corrosion treatment may be provided as seen in step 1294.
Conductive layer deposition apparatus 1296, which operates by vacuum deposition techniques, such as a sputtering machine manufactured by Balzers AG of Liechtenstein, is employed to produce a conductive layer 1258 (Fig. 21F) over the wafer 1240.
Configuration of conductors, as shown in Fig. 2 IG, is carried out preferably by using conventional electro-deposited photoresist, which is commercially available from DuPont under the brand name Primecoat or from Shipley, under the brand name Eagle.
The photoresist is applied to the wafers in a photoresist bath assembly 1298, which is commercially available from DuPont or Shipley.
The photoresist is preferably light configured by a UV exposure system 1300, using a mask 1302 to define suitable etching patterns. The photoresist is then developed in a development bath 1304, and then etched in a metal etch solution 1306 located in an etching bath 1308, thus providing a conductor configuration such as that shown in Figs.
19A and l9B. The exposed conductive strips shown in Fig. 21G are then plated, preferably by an electroless plating apparatus 1310, which is commercially available from Okuno of Japan.
Following plating of the conductive strips, the wafer is then coated with a solder mask as indicated at reference numeral 1312 to define the locations 1260 (Fig. 21H) of bumps 1228, which are then formed in a conventional manner (Fig. 211). Alternatively, the bumps 1228 may not be required.
The wafer is then separated into individual pre-packaged integrated circuit devices by a dicing blade 1314, as shown in Fig. 2 IJ. Preferably, dicing blade 1314 is a diamond resinoid blade of thickness 2 - 12 mils. As a further alternative, the wafer could be separated into individual circuit devices using any other conventional method such as scribing, etching, laser and water jet. The resulting packaged dies appear as illustrated generally in Figs. 19A and 19B.
It will be appreciated by persons skilled in the art that the present invention is not limited to what has been particularly shown and described hereinabove. Rather the scope of the present invention includes both combinations and subcombinations of the various features described hereinabove as well as modifications and variations thereof as would occur to a person of skill in the art upon reading the foregoing specification and which are not in the prior art.

Claims

C L A I M S
1. An integrally packaged integrated circuit device comprising: an integrated circuit die comprising: a crystalline substrate having first and second generally planar surfaces and edge surfaces; and an active surface formed on said first generally planar surface; at least one chip scale packaging layer formed over said active surface; and at least one electrical contact formed over said at least one chip scale packaging layer, said at least one electrical contact being connected to circuitry on said active surface by at least one pad formed on said first generally planar surface.
2. An integrally packaged integrated circuit device comprising: an integrated circuit die comprising: a crystalline substrate having first and second generally planar surfaces and edge surfaces; and an active surface formed on said first generally planar surface; at least one chip scale packaging layer formed over said active surface; and at least one electrical contact formed over at least one edge surface of said at least one chip scale packaging layer, said at least one electrical contact being connected to circuitry on said active surface by at least one pad formed on said first generally planar surface.
3. An integrally packaged integrated circuit device comprising: an integrated circuit die comprising: a crystalline substrate having first and second generally planar surfaces and edge surfaces; and an active surface formed on said first generally planar surface; at least one chip scale packaging layer formed over said active surface; and at least one electrical contact formed over said second generally planar surface, said at least one electrical contact being connected to circuitry on said active surface by at least one pad formed on said first generally planar surface.
4. An integrally packaged integrated circuit device comprising: an integrated circuit die comprising: a crystalline substrate having first and second generally planar surfaces and edge surfaces; and - an active surface formed on said first generally planar surface; at least one chip scale packaging layer formed over said active surface; and at least one electrical contact formed over at least one of said edge surfaces of said crystalline substrate, said at least one electrical contact being connected to circuitry on said active surface by at least one pad formed on said first generally planar surface.
5. An integrally packaged integrated circuit device according to any of claims 1-4 and wherein said at least one chip scale packaging layer is formed of a crystalline material.
6. An integrally packaged integrated circuit device according to any of claims 1-4 and wherein said crystalline substrate and said at least one chip scale packaging layer are both formed of silicon.
7. An integrally packaged integrated circuit device according to any of claims 1-4 and wherein said at least one chip scale packaging layer is formed of at least one of metal, plastic, thermoplastic, thermosetting and ceramic.
8. An integrally packaged integrated circuit device according to claim 1 or claim 2 and also comprising an insulation layer formed over said at least one chip scale packaging layer and directly underlying said at least one electrical contact.
9. An integrally packaged integrated circuit device according to claim 3 or claim 4 and also comprising an insulation layer formed over said second generally planar surface and directly underlying said at least one electrical contact.
10. An integrally packaged integrated circuit device according to claim 8 or claim 9 and wherein said insulation layer comprises at least one of a passivation layer and a dielectric layer.
11. An integrally packaged integrated circuit device according to claim 8 or claim 9 and wherein said insulation layer comprises at least one of epoxy, silicon oxide, solder mask, silicon nitride, silicon oxinitride, polyimide, BCB™, parylene, polynaphthalenes, fluorocarbons and accrylates.
12. An integrally packaged integrated circuit device according to any of claims 1-4 and wherein said at least one chip scale packaging layer is formed of silicon.
13. An integrally packaged integrated circuit device according to claim 1 or claim 2 and also including at least one gap formed between said crystalline substrate and said at least one packaging layer.
14. An integrally packaged integrated circuit device according to claim 3 or claim 4 and also including at least one gap formed between said crystalline substrate and said at least one packaging layer.
15. An integrally packaged integrated circuit device according to claim 13 or claim 14 and wherein said at least one gap is formed as at least one recess in said at least one packaging layer.
16.. An integrally packaged integrated circuit device according to claim 13 and also including at least one gap formed in said crystalline substrate.
17. An integrally packaged integrated circuit device according to claim 1 or claim 2 and also including at least one gap formed in said crystalline substrate.
18. An integrally packaged integrated circuit device according to claim 1 or claim 2 and also including at least one gap formed in said crystalline substrate and at least one chip scale packaging layer formed underlying said crystalline substrate and sealing said gap formed in said crystalline substrate.
19. A method of producing integrally packaged integrated circuit devices comprising: providing a plurality of integrated circuit dies formed on a wafer, each of said dies having first and second generally planar surfaces, and an active surface and at least one pad formed on said first generally planar surface, said active surface including circuitry; forming at least one chip scale packaging layer over said active surface; forming at least one electrical contact over said at least one chip scale packaging layer, said at least one electrical contact being connected to said circuitry by said at least one pad; and subsequently separating said wafer into a plurality of packaged integrated circuit devices.
20. A method of producing integrally packaged integrated circuit devices comprising: providing a plurality of integrated circuit dies formed on a wafer, each of said dies having first and second generally planar surfaces, edge surfaces, and an active surface and at least one pad formed on said first generally planar surface, said active surface including circuitry; forming at least one chip scale packaging layer over said active surface; forming at least one electrical contact over at least one edge surface of said at least one chip scale packaging layer, said at least one electrical contact being connected to said circuitry by said at least one pad; and subsequently separating said wafer into a plurality of packaged integrated circuit devices.
21. A method of producing integrally packaged integrated circuit devices comprising: providing a plurality of integrated circuit dies formed on a wafer, each of said dies having first and second generally planar surfaces, edge surfaces, and an active surface and at least one pad formed on said first generally planar surface, said active surface including circuitry; forming at least one chip scale packaging layer over said active surface; forming at least one electrical contact over said second generally planar surface, said at least one electrical contact being connected to said circuitry by said at least one pad; and subsequently separating said wafer into a plurality of packaged integrated circuit devices.
22. A method of producing integrally packaged integrated circuit devices comprising: providing a plurality of integrated circuit dies formed on a wafer, each of said dies having first and second generally planar surfaces, and an active surface and at least one pad formed on said first generally planar surface, said active surface including circuitry; forming at least one chip scale packaging layer over said active surface; forming at least one electrical contact over at least one of said edge surfaces of said integrated circuit die, said at least one electrical contact being connected to said circuitry by said at least one pad; and subsequently separating said wafer into a plurality of packaged integrated circuit devices.
23. A method according to any of claims 19-22 and wherein said forming at least one chip scale packaging layer comprises forming at least one crystalline material chip scale packaging layer.
24. A method according to any of claims 19-22 and wherein said forming at least one chip scale packaging layer comprises forming at least one silicon chip scale packaging layer and said providing a plurality of integrated circuit dies formed on a wafer comprises providing a plurality of integrated circuit dies formed on a silicon wafer.
25. A method according to any of claims 19-22 and wherein said forming at least one chip scale packaging layer comprises forming at least one chip scale packaging layer including at least one of metal, plastic, thermoplastic, thermosetting and ceramic.
26. A method according to claim 19 or claim 20 and also comprising forming an insulation layer over said at least one chip scale packaging layer and wherein said forming at least one electrical contact comprises forming said at least one electrical contact directly over said insulation layer.
27. A method according to claim 21 or 22 and also comprising forming an insulation layer over said second generally planar surface and said edge surfaces and wherein said forming at least one electrical contact comprises forming said at least one electrical contact directly over said insulation layer.
28. A method according to any of claims 19-22 and wherein said forming at least one chip scale packaging layer comprises forming at least one silicon chip scale packaging layer.
29. A method according to claim 19 or 20 and also including forming at least one gap between said plurality of dies and said at least one packaging layer.
30. A method according to claim 21 or 22 and also including forming at least one gap between said plurality of dies and said at least one packaging layer.
31. A method according to claim 29 or 30 and wherein said forming at least one gap comprises forming at least one recess in said at least one packaging layer.
32. A method according to claim 29 and wherein said forming at least one gap comprises forming at least one gap in said plurality of dies.
33. A method according to claim 19 or claim 20 and also including forming at least one gap in said plurality of dies.
34. A method according to claim 19 or claim 20 and also comprising: forming at least one gap in said plurality of dies; and forming at least one chip scale packaging layer over said second generally planar surface, thereby sealing said gap.
35. A method according to any of claims 29-34, wherein said forming at least one chip scale packaging layer over said active surface also comprises aligning said at least one chip scale packaging layer to said active surface.
36. A method according to any of claims 19-22 and wherein said forming at least one chip scale packaging layer comprises bonding said chip scale packaging layer to said plurality of dies using a bonding layer.
37. A method according to claim 36 and wherein said bonding layer comprises at least one of an adhesive, intermetallic bonding and anodic bonding.
38. A method according to any of claims 19-22 and wherein said forming at least one chip scale packaging layer also comprises thinning said packaging layer from an original thickness to a decreased thickness.
39. A method according to claim 38 and wherein said thinning comprises at least one of grinding, lapping and etching.
40. A method according to any of claim 19-22 and also comprising thinning said plurality of dies from an original thickness to a decreased thickness, subsequent to said forming at least one chip scale packaging layer and prior to said separating.
41. A method according to claim 40 and wherein said thinning comprises at least one of grinding, lapping and etching.
42. A method according to claim 40 and wherein said thinning comprises thinning said second planar surface.
43. A method according to claim 19 or 20 and also comprising: forming at least one first gap in said plurality of dies; and forming at least one second gap in said at least one chip scale packaging layer, said second gap communicating with said first gap.
44. A method according to claim 43 and also comprising forming at least one chip scale packaging layer over said second generally planar surface, thereby sealing said first gap.
45. A method according to claim 44 and wherein said forming at least one chip scale packaging layer over said second generally planar surface comprises forming at least one crystalline material chip scale packaging layer.
46. A method according to claim 45 and wherein said at least one crystalline material chip scale packaging layer is formed of silicon.
47. A method according to claim 44 and wherein said forming at least one chip scale packaging layer over said second generally planar surface comprises forming at least one chip scale packaging layer including at least one of metal, plastic, thermoplastic, thermosetting and ceramic.
48. A method according to claim 44 and wherein said forming at least one chip scale packaging layer over said second generally planar surface comprises bonding said chip scale packaging layer over said second generally planar surface to said plurality of dies using a bonding layer.
49. A method according to claim 48 and wherein said bonding layer comprises at least one of an adhesive, intermetallic bonding and anodic bonding.
50. A method according to claim 44 and wherein said forming at least one chip scale packaging layer over said second generally planar surface also comprises thinning said packaging layer from an original thickness to a decreased thickness.
51. A method according to claim 50 and wherein said thinning comprises at least one of grinding, lapping and etching.
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US20040251525A1 (en) 2004-12-16

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