WO2004112128A3 - Low profile stacking system and method - Google Patents

Low profile stacking system and method Download PDF

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Publication number
WO2004112128A3
WO2004112128A3 PCT/US2004/016347 US2004016347W WO2004112128A3 WO 2004112128 A3 WO2004112128 A3 WO 2004112128A3 US 2004016347 W US2004016347 W US 2004016347W WO 2004112128 A3 WO2004112128 A3 WO 2004112128A3
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WO
WIPO (PCT)
Prior art keywords
integrated circuit
substrate
circuit device
joints
contacts
Prior art date
Application number
PCT/US2004/016347
Other languages
French (fr)
Other versions
WO2004112128A2 (en
Inventor
James Cady
Julian Partridge
James Wehrly Jr
David Roper
Jeff Buchle
Original Assignee
Staktek Group Lp
James Cady
Julian Partridge
James Wehrly Jr
David Roper
Jeff Buchle
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/457,608 external-priority patent/US20030234443A1/en
Application filed by Staktek Group Lp, James Cady, Julian Partridge, James Wehrly Jr, David Roper, Jeff Buchle filed Critical Staktek Group Lp
Publication of WO2004112128A2 publication Critical patent/WO2004112128A2/en
Publication of WO2004112128A3 publication Critical patent/WO2004112128A3/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion

Abstract

The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing such mounted devices for stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is applied to a substrate or to the integrated circuit device to be mounted. The integrated circuit device is positioned to contact the contacts of the substrate. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.
PCT/US2004/016347 2003-06-09 2004-05-25 Low profile stacking system and method WO2004112128A2 (en)

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US10/457,608 2003-06-09
US10/457,608 US20030234443A1 (en) 2001-10-26 2003-06-09 Low profile stacking system and method
US10/631,886 2003-07-11
US10/631,886 US7026708B2 (en) 2001-10-26 2003-07-14 Low profile chip scale stacking system and method

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US20090273069A1 (en) 2009-11-05
US7026708B2 (en) 2006-04-11
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US20080211077A1 (en) 2008-09-04
US20040052060A1 (en) 2004-03-18
US7094632B2 (en) 2006-08-22

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