WO2005013326A3 - Epitaxial growth of relaxed silicon germanium layers - Google Patents

Epitaxial growth of relaxed silicon germanium layers Download PDF

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Publication number
WO2005013326A3
WO2005013326A3 PCT/US2004/023503 US2004023503W WO2005013326A3 WO 2005013326 A3 WO2005013326 A3 WO 2005013326A3 US 2004023503 W US2004023503 W US 2004023503W WO 2005013326 A3 WO2005013326 A3 WO 2005013326A3
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WO
WIPO (PCT)
Prior art keywords
silicon germanium
relaxed silicon
epitaxial growth
germanium layers
relaxed
Prior art date
Application number
PCT/US2004/023503
Other languages
French (fr)
Other versions
WO2005013326A2 (en
Inventor
Chantal J Arena
Pierre Tomasini
Nyles Cody
Matthias Bauer
Original Assignee
Asm Inc
Chantal J Arena
Pierre Tomasini
Nyles Cody
Matthias Bauer
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asm Inc, Chantal J Arena, Pierre Tomasini, Nyles Cody, Matthias Bauer filed Critical Asm Inc
Priority to EP04778830A priority Critical patent/EP1649495A2/en
Priority to JP2006521913A priority patent/JP2007511892A/en
Publication of WO2005013326A2 publication Critical patent/WO2005013326A2/en
Publication of WO2005013326A3 publication Critical patent/WO2005013326A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/52—Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD

Abstract

A relaxed silicon germanium structure (54) compries a silicon buffer layer (52) produced using a chemical vapor deposition process with an operational pressureing greater than approximately 1 torr. The relaxed silicon germanium structure (54) further comprises a silicon germanium layer (54) has less than about 10. sub.7 threading dislocations per square centimeters. By depositing the silicon buffer layer at a reduced deposition rate, the overlying silicon germanium layer can be provided with a 'Crosshatch free' surface.
PCT/US2004/023503 2003-07-30 2004-07-21 Epitaxial growth of relaxed silicon germanium layers WO2005013326A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP04778830A EP1649495A2 (en) 2003-07-30 2004-07-21 Epitaxial growth of relaxed silicon germanium layers
JP2006521913A JP2007511892A (en) 2003-07-30 2004-07-21 Epitaxial growth of relaxed silicon germanium layers.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US49102903P 2003-07-30 2003-07-30
US60/491,029 2003-07-30

Publications (2)

Publication Number Publication Date
WO2005013326A2 WO2005013326A2 (en) 2005-02-10
WO2005013326A3 true WO2005013326A3 (en) 2008-07-10

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/023503 WO2005013326A2 (en) 2003-07-30 2004-07-21 Epitaxial growth of relaxed silicon germanium layers

Country Status (6)

Country Link
US (2) US7514372B2 (en)
EP (1) EP1649495A2 (en)
JP (1) JP2007511892A (en)
KR (1) KR20060039915A (en)
TW (1) TWI382456B (en)
WO (1) WO2005013326A2 (en)

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US7598515B2 (en) * 2003-06-26 2009-10-06 Mears Technologies, Inc. Semiconductor device including a strained superlattice and overlying stress layer and related methods
US20070015344A1 (en) * 2003-06-26 2007-01-18 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions
US20070010040A1 (en) * 2003-06-26 2007-01-11 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Layer Above a Stress Layer
US7612366B2 (en) * 2003-06-26 2009-11-03 Mears Technologies, Inc. Semiconductor device including a strained superlattice layer above a stress layer
US20070020860A1 (en) * 2003-06-26 2007-01-25 Rj Mears, Llc Method for Making Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods
US7901968B2 (en) * 2006-03-23 2011-03-08 Asm America, Inc. Heteroepitaxial deposition over an oxidized surface
US7785995B2 (en) * 2006-05-09 2010-08-31 Asm America, Inc. Semiconductor buffer structures
CA2661047A1 (en) * 2006-05-15 2007-11-22 Arise Technologies Corporation Low-temperature doping processes for silicon wafer devices
US7608526B2 (en) * 2006-07-24 2009-10-27 Asm America, Inc. Strained layers within semiconductor buffer structures
US8765508B2 (en) * 2008-08-27 2014-07-01 Soitec Methods of fabricating semiconductor structures or devices using layers of semiconductor material having selected or controlled lattice parameters
US8039371B2 (en) * 2009-07-01 2011-10-18 International Business Machines Corporation Reduced defect semiconductor-on-insulator hetero-structures
EP2502266B1 (en) 2009-11-18 2020-03-04 Soitec Methods of fabricating semiconductor structures and devices using glass bonding layers, and semiconductor structures and devices formed by such methods
US9023721B2 (en) 2010-11-23 2015-05-05 Soitec Methods of forming bulk III-nitride materials on metal-nitride growth template layers, and structures formed by such methods
FR2968678B1 (en) 2010-12-08 2015-11-20 Soitec Silicon On Insulator METHODS OF FORMING GROUP III NITRIDE MATERIALS AND STRUCTURES FORMED THEREFROM
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Also Published As

Publication number Publication date
TWI382456B (en) 2013-01-11
US20090189185A1 (en) 2009-07-30
JP2007511892A (en) 2007-05-10
KR20060039915A (en) 2006-05-09
WO2005013326A2 (en) 2005-02-10
US7514372B2 (en) 2009-04-07
US20050051795A1 (en) 2005-03-10
EP1649495A2 (en) 2006-04-26
TW200509226A (en) 2005-03-01
US7666799B2 (en) 2010-02-23

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