WO2005020297A3 - Technique for evaluating a fabrication of a semiconductor component and wafer - Google Patents

Technique for evaluating a fabrication of a semiconductor component and wafer Download PDF

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Publication number
WO2005020297A3
WO2005020297A3 PCT/US2004/027770 US2004027770W WO2005020297A3 WO 2005020297 A3 WO2005020297 A3 WO 2005020297A3 US 2004027770 W US2004027770 W US 2004027770W WO 2005020297 A3 WO2005020297 A3 WO 2005020297A3
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
fabrication
performance parameter
evaluating
technique
Prior art date
Application number
PCT/US2004/027770
Other languages
French (fr)
Other versions
WO2005020297A2 (en
Inventor
Majid Aghababazadeh
Jose J Estabil
Nadar Pakdaman
Gary L Steinbrueck
James S Vickers
Original Assignee
Tau Metrix Inc
Majid Aghababazadeh
Jose J Estabil
Nadar Pakdaman
Gary L Steinbrueck
James S Vickers
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tau Metrix Inc, Majid Aghababazadeh, Jose J Estabil, Nadar Pakdaman, Gary L Steinbrueck, James S Vickers filed Critical Tau Metrix Inc
Priority to JP2006524855A priority Critical patent/JP5340538B2/en
Priority to EP04786586A priority patent/EP1665362A2/en
Publication of WO2005020297A2 publication Critical patent/WO2005020297A2/en
Publication of WO2005020297A3 publication Critical patent/WO2005020297A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing
    • G01R31/3025—Wireless interface with the DUT
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31707—Test strategies
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31718—Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G01R31/318511—Wafer Test
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.
PCT/US2004/027770 2003-08-25 2004-08-25 Technique for evaluating a fabrication of a semiconductor component and wafer WO2005020297A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2006524855A JP5340538B2 (en) 2003-08-25 2004-08-25 Techniques for evaluating semiconductor component and wafer manufacturing.
EP04786586A EP1665362A2 (en) 2003-08-25 2004-08-25 Technique for evaluating a fabrication of a semiconductor component and wafer

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US49794503P 2003-08-25 2003-08-25
US60/497,945 2003-08-25
US56316804P 2004-04-15 2004-04-15
US60/563,168 2004-04-15

Publications (2)

Publication Number Publication Date
WO2005020297A2 WO2005020297A2 (en) 2005-03-03
WO2005020297A3 true WO2005020297A3 (en) 2006-04-13

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/027770 WO2005020297A2 (en) 2003-08-25 2004-08-25 Technique for evaluating a fabrication of a semiconductor component and wafer

Country Status (5)

Country Link
US (11) US7220990B2 (en)
EP (1) EP1665362A2 (en)
JP (4) JP5340538B2 (en)
TW (1) TWI276147B (en)
WO (1) WO2005020297A2 (en)

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