WO2005034214A2 - Protective layer during scribing - Google Patents

Protective layer during scribing Download PDF

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Publication number
WO2005034214A2
WO2005034214A2 PCT/US2004/032458 US2004032458W WO2005034214A2 WO 2005034214 A2 WO2005034214 A2 WO 2005034214A2 US 2004032458 W US2004032458 W US 2004032458W WO 2005034214 A2 WO2005034214 A2 WO 2005034214A2
Authority
WO
WIPO (PCT)
Prior art keywords
coating
scribing
substrate
scribe
sawing
Prior art date
Application number
PCT/US2004/032458
Other languages
French (fr)
Other versions
WO2005034214A3 (en
Inventor
Sujit Sharan
Thomas Debonis
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to DE112004001787T priority Critical patent/DE112004001787T5/en
Publication of WO2005034214A2 publication Critical patent/WO2005034214A2/en
Publication of WO2005034214A3 publication Critical patent/WO2005034214A3/en

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0029—Etching of the substrate by chemical or physical means by laser ablation of inorganic insulating material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0756—Uses of liquids, e.g. rinsing, coating, dissolving
    • H05K2203/0769—Dissolving insulating materials, e.g. coatings, not used for developing resist after exposure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1377—Protective layers
    • H05K2203/1383—Temporary protective insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards

Definitions

  • the scribe process is used to scribe a circuit substrate (e.g., wafer) prior to sawing the substrate into individual chip or die.
  • a scribe process often uses an ultraviolet laser (typically a yttrium aluminum garnet (YAG) laser) to scribe the substrate prior to a sawing operation.
  • YAG yttrium aluminum garnet
  • a saw process that saws or cuts through the scribe area to divide or singulate the substrate can generally do so without damaging films (typically dielectric films) on the substrate.
  • the scribe is created in designated areas or streets by ablating any metal layers or dielectric layers (e.g., low dielectric constant dielectric layers) to the substrate (e.g., a silicon substrate).
  • a laser scribe process typically generates ablated material (mostly silicon with some carbon) as debris. This debris tends to fall on the surface of the substrate.
  • the surface of a substrate generally has a number of exposed contacts (e.g., bump contacts) on its surface. Thus, the debris tends to fall on the contacts and can adhere to the contact surface. This contamination of the contact surface inhibits the contacts from joining subsequent contacts during packaging leading to a characterization referred to as non-wet defects.
  • Figure 1 shows a top side view of a portion of a wafer having a number of discrete circuit structures formed thereon separated by scribe streets.
  • Figure 2 shows a cross-sectional side portion of the structure of Figure 1 through line A-A'.
  • Figure 3 A shows the structure of Figure 2 following the introduction of a chemically soluble coating on a surface of the structure according to one embodiment.
  • Figure 3B shows the structure of Figure 2 following the introduction of a chemically soluble coating on a surface of the structure according to another embodiment.
  • Figure 4 shows the structure of Figure 3 A and a scribe process.
  • Figure 5 shows the structure of Figure 4 during a wet sawing process.
  • Figure 6 shows the structure of Figure 5 following the wet sawing process.
  • Figure 7 shows a side view of a die or chip connected to a package.
  • Figure 1 is a schematic top side view of a portion of a substrate such as a wafer with number of discrete circuit structures formed therein and thereon.
  • Figure 2 is a cross-sectional side view of the structure of Figure 1 through line A-A'.
  • structure 100 includes substrate 105 of, for example, a semiconductor material such as silicon or a semiconductor layer on an insulator such as glass.
  • Structure 100 is a portion of a structure at a wafer level with a number of circuit structures (dies or chips) discreetly represented and connected at this point.
  • Each circuit structure e.g., die or chip 110A, . . .
  • each circuit structure (e.g., die or chip 110A, . . . 1101) may have a number of circuit devices formed in and on substrate 105 and one or more interconnection layers formed above substrate 105 and connecting with the devices on a respective die or chip.
  • a top surface of each circuit structure may have a number of contact points including, in this example, solder or similar conductive material bumps to send or receive signals external to the die or chip.
  • Bumps 115 protrude from a surface of a respective die or chip and, as viewed in Figure 2, are exposed on the surface of the respective die or chip. As shown in Figure 2, each bump protrudes from a surface of the substrate, a height, Ti of, on the order of 75 microns. Each bump 115 may be surrounded by a dielectric material that otherwise covers the surface of substrate 100.
  • Figure 3 A shows the structure of Figure 2 following the introduction of a chemically soluble coating on a surface of structure 100.
  • Chemically soluble coating 130 is deposited, in one embodiment, to a thickness, T 2 , that is greater than a height, T 1 ⁇ of protrusion of bumps 115 from a surface of the substrate. In this manner, chemically soluble coating 130 overlies (as viewed) bumps 115.
  • chemically soluble coating 130 is deposited as a relatively conformal coating, conforming to the surface of structure 100 and overlying bumps 115.
  • a representative thickness of chemically soluble coating 130 is on the order of five to 35 microns ( ⁇ m) and, in this embodiment, is thick enough to overly bumps 115 but not too thick that chemically soluble coating 130 may be not be subsequently removed in a reasonable time.
  • Chemically soluble coating 130 as viewed, overlies each circuit structure of structure 110 as well as scribe streets 120.
  • a material of chemically soluble coating 130 is a material that may be subsequently removed from the substrate surface.
  • a material for chemically soluble coating 130 should also be transparent to ultraviolet light so that it does not inhibit a subsequent scribe process (e.g., a YAG laser scribe process).
  • a material for chemically soluble coating 130 is environmentally non-toxic or harmful so that additional cautionary measures need not be taken during removal.
  • Suitable materials for chemically soluble coating 130 include organic coatings, including hydrophillic coatings, such as methyl cellulose, polyvinyl alcohol, and resin flux. These materials are transparent to ultraviolet light, may be removed with water, and are environmentally non-toxic or harmful.
  • chemically soluble coating 130 of a material such as methyl cellulose, polyvinyl alcohol, or resin flux may be applied to the substrate surface by various coating techniques, including, but not limited to, spinning, electrostatic spraying, or other techniques.
  • Figure 4 shows the structure of Figure 3 A and illustrates a scribe process in scribe streets 120.
  • a laser scribe process is utilized in which a YAG laser is used to scribe substrate 105. The scribing process tends to generate debris, mostly silicon and carbon, that, as the substrate is ablated, falls on chemically soluble coating 130.
  • Figure 5 shows the structure of Figure 4 and illustrates a sawing process.
  • the sawing process utilizes saw 140 and water 145 (a wet sawing process).
  • Saw 140 cuts through substrate 105 to singulate circuit structures (e.g., dies or chips 110A, . . . 1101).
  • circuit structures e.g., dies or chips 110A, . . . 1101).
  • the water utilized during the sawing process may serve also to remove the material of chemically soluble coating 130.
  • chemically soluble coating 130 may be removed, such as by rinsing with water or other solvent, prior to or after the sawing process.
  • Figure 6 shows the structure of Figure 5 following the singulation of individual circuit structures. Illustrated in Figure 6 are die or chip 110 A, die or chip
  • FIG. 6 also shows each circuit structure after the removal of chemically soluble coating 130. In this manner, contacts (bumps) 115 are exposed. Any debris that was generated process, during the scribing process, has been removed with the removal of chemical soluble coating 130.
  • Figure 7 shows die or chip 110A mounted on package 150.
  • the mounting method includes contacting bumps 115 of die or chip 110A with corresponding contact points or bumps 155 of package 150. Once the contact between the contact points is made, a reflow process may be used to join die or chip 110A to package 150.
  • a reflow process may be used to join die or chip 110A to package 150.
  • chemically soluble coating 130 during the scribing process, the ability of ablated material to land on contact points or bumps 115 is minimized. Accordingly, the possibility of defects occurring when a die or chip is connected, for example, to a package, is minimized (e.g., the number of non-wets is minimized).

Abstract

A method including forming a chemically soluble coating on a plurality exposed contacts on a surface of a circuit substrate; scribing the surface of the substrate along scribe areas; and after scribing, removing a portion of the coating. A method including forming a circuit structure comprises a plurality of exposed contacts on a surface, a location of the exposed contacts defined by a plurality of scribe streets; forming a coating comprising a chemically soluble material on the exposed contacts; scribing the surface of the substrate along the scribe streets; and after scribing, removing the coating. A method including coating a surface of a circuit substrate comprising a plurality of exposed contacts with a chemically soluble material; scribing the surface of the substrate along scribe areas; removing the coating; and sawing the substrate in the scribe areas.

Description

PROTECTIVE LAYER DURING SCRIBING
BACKGROUND
FIELD
[0001] Circuit fabrication.
BACKGROUND
[0002] The scribe process is used to scribe a circuit substrate (e.g., wafer) prior to sawing the substrate into individual chip or die. According to current technology, a scribe process often uses an ultraviolet laser (typically a yttrium aluminum garnet (YAG) laser) to scribe the substrate prior to a sawing operation. By scribing the substrate prior to sawing, a saw process that saws or cuts through the scribe area to divide or singulate the substrate can generally do so without damaging films (typically dielectric films) on the substrate. During a scribe process, the scribe is created in designated areas or streets by ablating any metal layers or dielectric layers (e.g., low dielectric constant dielectric layers) to the substrate (e.g., a silicon substrate). A laser scribe process typically generates ablated material (mostly silicon with some carbon) as debris. This debris tends to fall on the surface of the substrate. The surface of a substrate generally has a number of exposed contacts (e.g., bump contacts) on its surface. Thus, the debris tends to fall on the contacts and can adhere to the contact surface. This contamination of the contact surface inhibits the contacts from joining subsequent contacts during packaging leading to a characterization referred to as non-wet defects.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] Features, aspects, and advantages of embodiments will become more thoroughly apparent from the following detailed description, appended claims, and accompanying drawings in which:
[0004] Figure 1 shows a top side view of a portion of a wafer having a number of discrete circuit structures formed thereon separated by scribe streets. [0005] Figure 2 shows a cross-sectional side portion of the structure of Figure 1 through line A-A'.
[0006] Figure 3 A shows the structure of Figure 2 following the introduction of a chemically soluble coating on a surface of the structure according to one embodiment.
[0007] Figure 3B shows the structure of Figure 2 following the introduction of a chemically soluble coating on a surface of the structure according to another embodiment.
[0008] Figure 4 shows the structure of Figure 3 A and a scribe process.
[0009] Figure 5 shows the structure of Figure 4 during a wet sawing process.
[0010] Figure 6 shows the structure of Figure 5 following the wet sawing process.
[0011] Figure 7 shows a side view of a die or chip connected to a package.
DETAILED DESCRIPTION
[0012] Figure 1 is a schematic top side view of a portion of a substrate such as a wafer with number of discrete circuit structures formed therein and thereon. Figure 2 is a cross-sectional side view of the structure of Figure 1 through line A-A'. Referring to Figure 1 and Figure 2, structure 100 includes substrate 105 of, for example, a semiconductor material such as silicon or a semiconductor layer on an insulator such as glass. Structure 100 is a portion of a structure at a wafer level with a number of circuit structures (dies or chips) discreetly represented and connected at this point. Each circuit structure (e.g., die or chip 110A, . . . 1101) is separated on substrate 105 by scribe streets 120 that are used as a singulation area to separate the circuit structures from the substrate into a discrete die or chip. Figure 1 shows dies or chips 110A, HOB, HOC, HOD, HOE, 110F, 110G, 110H, and 1101 (see Figure 1). Each circuit structure (e.g., die or chip 110A, . . . 1101) may have a number of circuit devices formed in and on substrate 105 and one or more interconnection layers formed above substrate 105 and connecting with the devices on a respective die or chip. A top surface of each circuit structure may have a number of contact points including, in this example, solder or similar conductive material bumps to send or receive signals external to the die or chip. Bumps 115 protrude from a surface of a respective die or chip and, as viewed in Figure 2, are exposed on the surface of the respective die or chip. As shown in Figure 2, each bump protrudes from a surface of the substrate, a height, Ti of, on the order of 75 microns. Each bump 115 may be surrounded by a dielectric material that otherwise covers the surface of substrate 100.
[0013] Figure 3 A shows the structure of Figure 2 following the introduction of a chemically soluble coating on a surface of structure 100. Chemically soluble coating 130 is deposited, in one embodiment, to a thickness, T2, that is greater than a height, T1} of protrusion of bumps 115 from a surface of the substrate. In this manner, chemically soluble coating 130 overlies (as viewed) bumps 115. In another embodiment, shown in Figure 3B, chemically soluble coating 130 is deposited as a relatively conformal coating, conforming to the surface of structure 100 and overlying bumps 115. A representative thickness of chemically soluble coating 130 is on the order of five to 35 microns (μm) and, in this embodiment, is thick enough to overly bumps 115 but not too thick that chemically soluble coating 130 may be not be subsequently removed in a reasonable time.
Chemically soluble coating 130, as viewed, overlies each circuit structure of structure 110 as well as scribe streets 120.
[0014] In one embodiment, a material of chemically soluble coating 130 is a material that may be subsequently removed from the substrate surface. Where an ultraviolet laser scribe process will be used to scribe structure 100, a material for chemically soluble coating 130 should also be transparent to ultraviolet light so that it does not inhibit a subsequent scribe process (e.g., a YAG laser scribe process). Finally, in one embodiment, a material for chemically soluble coating 130 is environmentally non-toxic or harmful so that additional cautionary measures need not be taken during removal. Suitable materials for chemically soluble coating 130 include organic coatings, including hydrophillic coatings, such as methyl cellulose, polyvinyl alcohol, and resin flux. These materials are transparent to ultraviolet light, may be removed with water, and are environmentally non-toxic or harmful. In one embodiment, chemically soluble coating 130 of a material such as methyl cellulose, polyvinyl alcohol, or resin flux may be applied to the substrate surface by various coating techniques, including, but not limited to, spinning, electrostatic spraying, or other techniques. [0015] Figure 4 shows the structure of Figure 3 A and illustrates a scribe process in scribe streets 120. In one embodiment, a laser scribe process is utilized in which a YAG laser is used to scribe substrate 105. The scribing process tends to generate debris, mostly silicon and carbon, that, as the substrate is ablated, falls on chemically soluble coating 130.
[0016] Figure 5 shows the structure of Figure 4 and illustrates a sawing process.
In one embodiment, the sawing process utilizes saw 140 and water 145 (a wet sawing process). Saw 140 cuts through substrate 105 to singulate circuit structures (e.g., dies or chips 110A, . . . 1101). Where chemically soluble coating is water soluble, in one embodiment, the water utilized during the sawing process may serve also to remove the material of chemically soluble coating 130. Alternatively, chemically soluble coating 130 may be removed, such as by rinsing with water or other solvent, prior to or after the sawing process.
[0017] Figure 6 shows the structure of Figure 5 following the singulation of individual circuit structures. Illustrated in Figure 6 are die or chip 110 A, die or chip
HOB, and die or chip 1 IOC. Figure 6 also shows each circuit structure after the removal of chemically soluble coating 130. In this manner, contacts (bumps) 115 are exposed. Any debris that was generated process, during the scribing process, has been removed with the removal of chemical soluble coating 130.
[0018] Figure 7 shows die or chip 110A mounted on package 150. In this embodiment, the mounting method includes contacting bumps 115 of die or chip 110A with corresponding contact points or bumps 155 of package 150. Once the contact between the contact points is made, a reflow process may be used to join die or chip 110A to package 150. By utilizing chemically soluble coating 130 during the scribing process, the ability of ablated material to land on contact points or bumps 115 is minimized. Accordingly, the possibility of defects occurring when a die or chip is connected, for example, to a package, is minimized (e.g., the number of non-wets is minimized).
[0019] In the preceding paragraphs, specific embodiments are described. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

CLAIMS What is claimed is:
1. A method comprising: forming a chemically soluble coating on a plurality exposed contacts on a surface of a circuit substrate; scribing the surface of the substrate along scribe areas; and after scribing, removing a portion of the coating.
2. The method of claim 1 , wherein each of a portion of the plurality of contacts comprise protruding bumps on the surface and forming the coating comprises forming the coating to a thickness greater than a distance of surface protrusion of the portion of the plurality of contacts.
3. The method of claim 2, wherein the coating has a thickness of 5 to 35 microns.
4. The method of claim 2, further comprising sawing the substrate along the scribed areas.
5. The method of claim 4, wherein sawing and removing a portion of the coating are done simultaneously.
6. The method of claim 1, wherein removing a portion of the coating comprises exposing the plurality of contacts.
7. The method of claim 6, wherein removing a portion of the coating comprises removing the entire portion.
8. The method of claim 1, wherein a material of the chemically soluble coating is selected from the group consisting of methyl cellulose, polyvinyl alcohol, and resin flux.
9. A method comprising: forming a circuit structure comprises a plurality of exposed contacts on a surface, a location of the exposed contacts defined by a plurality of scribe streets; forming a coating comprising a chemically soluble material on the exposed contacts; scribing the surface of the substrate along the scribe streets; and after scribing, removing the coating.
10. The method of claim 9, further comprising, after scribing, sawing the substrate along the scribe streets.
11. The method of claim 10, wherein sawing and removing the coating are done simultaneously.
12. The method of claim 10, wherein removing the coating comprises removing the entire coating.
13. The method of claim 10, wherein the material of the coating is selected from the group consisting of methyl cellulose, polyvinyl alcohol, and resin flux.
14. A method comprising: coating a surface of a circuit substrate comprising a plurality of exposed contacts with a chemically soluble material; scribing the surface of the substrate along scribe areas; removing the coating; and sawing the substrate in the scribe areas.
15. The method of claim 14, wherein sawing and removing the coating are done simultaneously.
16. The method of claim 15, wherein the material of the coating is selected from the group consisting of methyl cellulose, polyvinyl alcohol, and resin flux.
PCT/US2004/032458 2003-09-30 2004-09-29 Protective layer during scribing WO2005034214A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE112004001787T DE112004001787T5 (en) 2003-09-30 2004-09-29 Protective layer during scoring

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/676,303 US7265032B2 (en) 2003-09-30 2003-09-30 Protective layer during scribing
US10/676,303 2003-09-30

Publications (2)

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WO2005034214A2 true WO2005034214A2 (en) 2005-04-14
WO2005034214A3 WO2005034214A3 (en) 2005-06-16

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US (1) US7265032B2 (en)
KR (1) KR100847933B1 (en)
CN (1) CN100468644C (en)
DE (1) DE112004001787T5 (en)
TW (1) TWI277374B (en)
WO (1) WO2005034214A2 (en)

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