WO2005034592A1 - 積層セラミックス基板及びその製造方法 - Google Patents
積層セラミックス基板及びその製造方法 Download PDFInfo
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- WO2005034592A1 WO2005034592A1 PCT/JP2004/014551 JP2004014551W WO2005034592A1 WO 2005034592 A1 WO2005034592 A1 WO 2005034592A1 JP 2004014551 W JP2004014551 W JP 2004014551W WO 2005034592 A1 WO2005034592 A1 WO 2005034592A1
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- ceramic substrate
- side electrode
- green sheet
- hole
- multilayer ceramic
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09145—Edge details
- H05K2201/0919—Exposing inner circuit layers or metal planes at the side edge of the PCB or at the walls of large holes
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4061—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24777—Edge feature
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24926—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including ceramic, glass, porcelain or quartz layer
Definitions
- the present invention relates to a laminated ceramic substrate for forming various electronic circuits mounted on an electronic device such as a mobile phone, and a method for manufacturing the same.
- Patent Document 1 a small electronic device such as a mobile phone, a plurality of circuit elements constituting the device have been integrated into a one-layer laminated ceramic component, and the laminated ceramic component has been mounted on a main substrate.
- Patent Document 1 a plurality of circuit elements constituting the device have been integrated into a one-layer laminated ceramic component, and the laminated ceramic component has been mounted on a main substrate.
- FIG. 11 shows a laminated structure of the laminated ceramic component 1, in which a plurality of ceramic layers 2 are laminated to constitute a laminated ceramic substrate 20.
- a plurality of circuit element patterns 3 constituting an inductor capacitor are formed. These circuit element patterns 3 are connected to each other by a vertical conductive path (hereinafter, referred to as a via hole) 31 formed through the ceramic layer 2.
- a side surface electrode 47 is provided on a side surface of the multilayer ceramic substrate 20 and is connected to the circuit element pattern 3.
- a cavity 21 is recessed on the surface of the multilayer ceramic substrate 20, and an electronic component 4 such as a surface acoustic wave filter is mounted on the bottom surface of the cavity 21.
- the electronic component 4 is connected via a bonding wire 32.
- a lid 5 is provided on the surface of the multilayer ceramic substrate 20 so as to cover the cavity 21, thereby forming a packaged multilayer ceramic component 1.
- the laminated ceramic substrate 20 is manufactured by the steps shown in FIG. First, as shown in FIG. 10A, a green sheet 25 made of a ceramics mixed material is prepared. Next, as shown in FIG. 3B, through holes 22 for cavities, through holes for via holes (T shown in the drawing), and through holes 23 for side electrodes having a circular shape are formed in necessary portions of the green sheet 25, and then, as shown in FIG. As shown in C), the conductive material 24 is filled in the through hole for via hole and the through hole 23 for side electrode. Further, a conductive material 24 is printed on the surface of the green sheet 25 as shown in FIG.
- the green sheet laminate 26 is divided into cavities 21 to obtain a plurality of green sheet laminate chips 27.
- each green sheet laminate chip 27 is baked to obtain a laminated ceramic substrate 20.
- the electronic component 4 is mounted on the bottom surface of the cavity 21 of the multilayer ceramic substrate 20 obtained in this manner, as shown in FIG. 11, wire-bonded, and the lid 5 is installed, whereby the multilayer ceramic component 1 is formed. Is completed.
- Patent Document 1 Patent No. 3 3 3 6 9 13 Figure 6 (b)
- FIG. 4A is a partial top view of the vicinity of the circular side electrode through hole 23 of the conventional green sheet laminate 26.
- the side electrode through holes 23a, 23b, and 23c have the same shape.
- the green sheet 25a is disposed on the design center in the side electrode width direction and on the design center in the side electrode depth direction, and the green sheet 25b is penetrated for the side electrode with respect to the design center in the side electrode width direction.
- the green sheet 25c is larger than the radius of the hole and deviates by XI to the left of the paper, and the green sheet 25c is larger than the radius of the through-hole for the side electrode and X2 to the right of the paper to the center of design in the width direction of the side electrode.
- XI to the left of the paper
- the green sheet 25c is larger than the radius of the through-hole for the side electrode and X2 to the right of the paper to the center of design in the width direction of the side electrode.
- the width direction center of the side electrode through hole 23a of the green sheet 25a is the same as the design center 43 in the side electrode width direction.
- the width direction center 42b of the side electrode through hole 23b of the green sheet 25b is shifted to the left on the paper by the stacking deviation amount XI with respect to the design center 43 in the side electrode width direction.
- the center 42c in the width direction of the side electrode through hole 23c of the green sheet 25c is shifted to the right on the paper by the stacking deviation amount X2 with respect to the design center 43 in the side electrode width direction.
- FIG. 4B shows a green sheet laminate chip 27 obtained by dividing the green sheet laminate 26 along a line 45a-45a (the same as the design center 45 in the side electrode depth direction).
- FIG. 4 is a partial side view in the vicinity of the side electrode of FIG.
- the side edge electrode layers 41a, 41b, and 41c which should be electrically connected, are on the side of the adjacent green sheet 25b.
- 25 The side edge electrodes of the electrode layer 41b and the green sheet 25c. It is cut off at the boundary of layer 41c. Therefore, the multilayer ceramic substrate has a disconnection failure.
- FIG. 6A is a partial top view of the vicinity of the circular side electrode through hole 23 of the conventional green sheet laminate 26.
- the side electrode through holes 23d, 23e, and 23f have the same shape.
- the green sheet 25d is disposed on the design center in the lateral electrode width direction and on the design center in the lateral electrode depth direction
- the green sheet 25e is positioned on the side electrode through-hole with respect to the design center in the lateral electrode depth direction.
- the green sheet is smaller than the radius and displaced in the downward direction of the paper by Y3, and is displaced by X3 to the left of the paper and smaller than the radius of the through-hole for the side electrode with respect to the design center in the lateral electrode width direction.
- the 25f is smaller than the radius of the side-electrode through-hole with respect to the design center in the side-electrode depth direction. It is assumed that the stacking shift is smaller than the radius by X4 to the right of the paper.
- the center in the depth direction of the side electrode through hole 23d of the green sheet 25d is the same as the design center 45 in the side electrode depth direction, and the center in the width direction is the same as the design center 43 in the side electrode width direction.
- the center 44e in the depth direction of the through-hole 23e for the side electrode of the green sheet 25e is shifted downward in the drawing by the stacking deviation amount Y3 with respect to the design center 45 in the depth direction of the side electrode.
- the center 42e in the width direction of the through hole 23e is shifted to the left side of the paper by the stacking deviation amount X3 with respect to the design center 43 in the width direction of the side electrode.
- the center 44f in the depth direction of the side electrode through hole 23f of the green sheet 25f is displaced upward in the plane of the paper by the stacking deviation amount Y4 with respect to the design center 45 in the side electrode depth direction, and the side electrode through hole for the green sheet 25f.
- the center 42f in the width direction of 23f is shifted to the right on the paper by the stacking deviation amount X4 with respect to the design center 43 in the width direction of the side electrode.
- FIG. 6 (b) shows the side of the green sheet laminate chip 27 obtained by dividing the green sheet laminate 26 along the line 45b-45b (same as the design center 45 in the side electrode depth direction). It is a partial side view near an electrode.
- the stacking deviations Y3 and ⁇ 4 in the depth direction of the green sheets 25e and 25f and the stacking deviations ⁇ 3 and ⁇ 4 in the width direction are both smaller than the radius of the
- the side electrode layers 41d, 41e, and 41f that must be electrically connected are cut off at the boundary between the side electrode layer 41e of the adjacent green sheet 25e and the side electrode layer 41f of the green sheet 25f. Therefore, multilayer ceramic
- the circuit board has a disconnection failure.
- FIG. 8 (a) is a partial top view of the vicinity of the circular side electrode through hole 23 of the conventional green sheet laminate 26.
- the side electrode through holes 23m, 23 ⁇ , and 23 ⁇ have the same shape.
- the green sheets 25m and 25 ⁇ are displaced from the design center in the depth direction of the side electrodes by ⁇ 5, which is smaller than the radius of the through-holes for the side electrodes, and shifted upward by ⁇ 5, and the green sheet 25 ⁇ is shifted in the depth direction of the side electrodes. It is assumed that the stacking displacement is larger than the design center by a radius of the through-hole for the side-surface electrode by ⁇ 6 in the downward direction on the paper.
- green sheets 25m, 25n, and 25 ⁇ are arranged at the design center in the lateral electrode width direction.
- Green sheet 25m, 25 ⁇ side electrode through-holes 23m, 23 ⁇ depth center 44m, 44 ⁇ are offset from the design center 45 toward the back of the side electrode by a stacking deviation of ⁇ 5 upward in the paper.
- the center 44 ⁇ in the depth direction of the side electrode through hole 23 ⁇ of the green sheet 25 ⁇ is shifted downward in the paper plane by the stacking deviation amount ⁇ 6 with respect to the design center 45 in the side electrode depth direction.
- FIG. 8B is a partial cross-sectional view of the vicinity of the side electrode obtained by dividing the green sheet laminate 26 along line 43c-43c (the same as the design center 43 in the side electrode width direction).
- the through-holes 23m, 23n, 23 ⁇ for the side electrode which must be electrically connected, are located between the through-hole 23m for the side electrode on the adjacent green sheet 25m and the green sheet 25 ⁇ . It is cut off at the boundary between the side electrode through hole 23 ⁇ and the boundary between the side electrode through hole 23 ⁇ of the adjacent green sheet 25 ⁇ and the side electrode through hole 23 ⁇ of the green sheet 25 ⁇ .
- the side electrodes of the green sheet laminate chip 27 obtained by dividing the green sheet laminate 26 along the line 45c-45c (same as the design center 45 in the side electrode depth direction) are cut off. Therefore, the multilayer ceramic substrate has a disconnection failure.
- an object of the present invention is to provide a multilayer ceramic substrate that reduces a disconnection failure of the multilayer ceramic substrate 20 caused by a misalignment of the green sheets, and a method of manufacturing the same. Disclosure of the invention
- the side edge electrode layer has a parallel wall substantially parallel to and not exposed to a side surface of the multilayer ceramic substrate, and a vertical wall substantially perpendicular to a side surface of the multilayer ceramic substrate;
- the length L a has a relationship of L a> L b with respect to the depth L b of the parallel wall from the side surface of the multilayer ceramic substrate.
- FIG. 3 (a) is a partial top view of the vicinity of the side-electrode through hole 23 of the green sheet laminate 26 of the present invention.
- the side electrode through-holes 23g, 23h, and 23i have the same shape, and the depth dimension (dimension between 46a and 46a) is equal to the diameter of the circular side electrode through-hole shown in Fig. 4.
- the length of the two opposing flat walls 46a of the side-electrode through-hole is larger than the length between the flat walls 46a-46a.
- the stacking deviation amounts of the three green sheets with respect to the design center in the lateral electrode width direction and the design center in the lateral electrode depth direction are also exactly the same as in FIG.
- the green sheet 25g is disposed on the design center in the lateral electrode width direction and on the design center in the lateral electrode depth direction, and the green sheet 25h is penetrated for the lateral electrode with respect to the design center in the lateral electrode width direction.
- the stacking displacement is larger than 1/2 the depth of the hole by XI to the left of the paper, and the green sheet 25i is 1/1/2 of the depth of the through hole for the side electrode with respect to the design center in the width direction of the side electrode. It is assumed that the stacking shift is larger than 2 and X2 is shifted to the right of the paper. Also, it is assumed that both the green sheets 25h and 25i are arranged on the design center in the side electrode depth direction.
- the center in the width direction of the side electrode through hole 23g of the green sheet 25e is the same as the design center 43 in the side electrode width direction.
- the width direction center 42h of the side electrode through hole 23h of the green sheet 25h is shifted to the left on the paper by the stacking deviation amount XI with respect to the design center 43 in the side electrode width direction.
- the center 42i in the width direction of the side electrode through hole 23i of the green sheet 25i is shifted rightward on the paper by the stacking deviation amount X2 with respect to the design center 43 in the side electrode width direction.
- FIG. 3B shows the vicinity of the side electrode of the green sheet laminate chip 27 obtained by dividing the green sheet laminate 26 along the line 45a-45a (same as the design center 45 in the side electrode depth direction). It is a partial side view. As can be seen from the figure, there is a portion overlapping the side edge electrode layer 41h of the adjacent green sheet 25h and the side edge electrode layer 41i of the green sheet 25i. No shredding occurred and no disconnection failure.
- FIG. 5 (a) shows a portion of the green sheet laminate 26 of the present invention in the vicinity of the through hole 23 for the side electrode.
- the side electrode through holes 23j, 23k, and 231 have the same shape, and the depth dimension (dimension between 46b and 46b) is equal to the diameter of the circular side electrode through hole in FIG.
- the length of the two opposing flat walls 46 b of the side-electrode through hole is larger than 12 which is the dimension between the flat walls 46 b-46 b.
- the stacking deviation amounts of the three green sheets with respect to the design center in the side electrode width direction and the design center in the side electrode depth direction are also exactly the same as in FIG.
- the green sheet 25j is disposed on the design center in the side electrode width direction and on the design center in the side electrode depth direction, and the green sheet 25k is positioned at a depth dimension of the side electrode through hole with respect to the design center in the side electrode depth direction.
- the green sheet 251 is shifted from the design center in the depth direction of the side electrode by less than 1/2 of the depth dimension of the through hole for the side electrode, and the green sheet 251 is shifted by Y4 in the upward direction on the paper surface, and the width of the side electrode is shifted. It is assumed that the depth of the through hole for the side electrode is smaller than 1 Z 2 with respect to the design center in the direction, and the stacking displacement is shifted by X4 to the right of the paper.
- the center in the depth direction of the through-hole for side electrode 23j of the green sheet 25j is the same as the design center 45 in the side electrode depth direction, and the center in the width direction is the same as the design center 43 in the side electrode width direction.
- the depth center 44k of the side electrode through hole 23k of the green sheet 25k is shifted from the design center 45 in the depth direction of the side electrode by a stacking shift amount Y3 downward in the paper plane, and the side of the green sheet 25k.
- the center 42k in the width direction of the electrode through hole 23k is shifted to the left on the paper by the stacking deviation amount X3 with respect to the design center 43 in the side electrode width direction.
- FIG. 5B shows the vicinity of the side electrode of the green sheet laminate chip 27 obtained by dividing the green sheet laminate 26 along a line 45b-45b (same as the design center 45 in the side electrode depth direction). It is a partial side view. As can be seen from the figure, there is a portion that overlaps the side electrode layer 41k of the adjacent green sheet 25k and the side electrode layer 411 of the green sheet 251. No breaks occurred and no disconnection failure occurred.
- FIG. 7 (a) shows a portion of the green sheet laminate 26 of the present invention in the vicinity of the through-hole 23 for the side electrode.
- the side electrode through holes 23p and 23r have the same shape, and the depth dimension (dimension between 46c and 46c) is equal to the diameter of the circular side electrode through hole in FIG.
- the dimension in the depth direction (dimension between 46 d and 46 d) of the hole 23q is larger than the diameter of the circular side electrode through hole shown in FIG.
- the length of the two plane walls 46 c that are opposed to both the through-holes 23 p and 23 r for the side electrode is larger than 12 which is the dimension between the plane walls 46 c — 46 c, and is opposed to the through-hole 23 q for the side electrode.
- the length of the two flat walls 46 d is greater than 1 Z 2, which is the dimension between the flat walls 46 d and 46 d. It is also assumed that the amount of stacking deviation of the three green sheets with respect to the design center in the lateral electrode width direction and the design center in the lateral electrode depth direction is exactly the same as in FIG.
- the green sheets 25p and 25r are displaced from the design center toward the back of the side electrode by Y5, which is smaller than the depth dimension of the through-hole for side electrode 23p, which is smaller than 1 ⁇ 2, by Y5, and the green sheet 25q Is larger than the depth dimension 1Z2 of the through-hole 23p for the side electrode from the design center in the depth direction of the side electrode, and the layer is shifted by Y6 in the downward direction on the paper surface.
- the green sheets 25p, 25q, and 25r are all arranged at the design center in the lateral electrode width direction.
- the center 44p, 44r in the depth direction of the side electrode through-holes 23p, 23r of the green sheets 25p, 25r is shifted upward in the paper by the stacking deviation amount Y5 with respect to the design center 45 in the side electrode depth direction. Further, the center 44q in the depth direction of the side electrode through hole 23q of the green sheet 25q is shifted downward in the paper plane by the stacking deviation amount Y6 with respect to the design center 45 in the side electrode depth direction.
- FIG. 7B is a partial cross-sectional view of the vicinity of the side electrode obtained by dividing the green sheet laminate 26 along a line 43c-43c (the same as the design center 43 in the side electrode width direction).
- Overlapping portions are formed at the boundary between the side electrode through hole 23r of the green sheet 25r and the green sheet 25r. Therefore, since the side electrodes of the green sheet laminate chip 27 obtained by dividing the green sheet laminate 26 along the line 45c-45c (same as the design center 45 in the side electrode depth direction) are not cut, the laminated ceramic The board will not be defective.
- the side edge electrode layer has the parallel wall substantially parallel to the side surface of the multilayer ceramic substrate and not exposed, and the vertical wall substantially perpendicular to the side surface of the multilayer ceramic substrate, and the length of the parallel wall is L a is the depth of the parallel wall from the side of the multilayer ceramic substrate.
- L a is the depth of the parallel wall from the side of the multilayer ceramic substrate.
- FIG. 9A is a front view of the multilayer ceramic substrate 20.
- 9 (b) to 9 (d) are schematic cross-sectional views of the ceramic substrate 20 taken along line 60-60, except for the side electrode layer 47 for simplification of the drawing.
- a side-surface electrode through-hole having only a larger depth dimension than the through-hole is opened, and even-numbered green sheets viewed from the top are alternately laminated to complete a laminated ceramic substrate. As shown in FIG.
- the cut surface has a shape in which the ceramic layer 2a having a small depth dimension of the electrode layer 41 and the ceramic layer 2b having a large depth are alternately formed from the uppermost layer to the lowermost layer, that is, the opposite side. ⁇
- the sum LL + LbR of the depth dimensions of the electrode layer 41 has a partially different shape in the laminating direction, but it is possible to further reduce the rate of occurrence of side electrode breakage due to laminating misalignment.
- a thin green sheet ⁇ A large depth dimension is applied only to the ceramic layer 2c formed of a green sheet that is prone to lamination misalignment such as a green sheet printed with a large area GND pattern.
- a side edge electrode layer 41 having a large depth dimension may be provided only on the layer directly above and above Z of the ceramic layer 2c as shown in FIG. 9 (d). Is also good.
- the number and position of the ceramic layers on which the side edge electrode layers 41 having a large depth dimension are arranged are not limited.However, if the depth dimension of the side edge electrode layers 41 is increased, the circuit element pattern 3 on the ceramic layer is arranged. Therefore, it is preferable that the number of ceramic layers provided with the side edge electrode layers 41 having a large depth dimension be minimized.
- FIG. 1 is a partial top view and a partial perspective view according to Embodiment 1 of the present invention
- FIG. 2 is a partial top view and a partial perspective view according to Embodiment 2 of the present invention.
- FIG. 3 is a process diagram of a multilayer ceramic substrate according to the present invention.
- FIG. 4 is a process diagram of a multilayer ceramic substrate according to a conventional example.
- FIG. 5 is a process diagram of a multilayer ceramic substrate according to the present invention.
- FIG. 6 is a process diagram of the laminated ceramic substrate according to the conventional example:
- FIG. 7 is a process diagram of the laminated ceramic substrate according to the present invention;
- FIG. 8 is a process diagram of the laminated ceramic substrate according to the conventional example.
- FIG. 9 is a front view and a schematic cross-sectional view of a multilayer ceramic substrate according to the present invention.
- FIG. 10 is a series of process diagrams of a multilayer ceramic substrate according to the present invention and a conventional example.
- FIG. FIG. 7 is a cross-sectional view of a multilayer ceramic component using a multilayer ceramic substrate according to a conventional example.
- the multilayer ceramic substrate 20 is configured by laminating a plurality of ceramic layers 2 as shown in FIG. On the surface of each ceramic layer 2, a plurality of circuit element patterns 3 constituting an inductor / capacitor are formed. These circuit element patterns 3 are connected to each other by via holes 31 formed through the ceramic layer 2.
- a side surface electrode 47 is provided on the side surface of the multilayer ceramic substrate 20, and is connected to the circuit element pattern 3.
- a cavity 21 is formed in the surface of the multilayer ceramic substrate 20.
- the multilayer ceramic component 1 using the multilayer ceramic substrate 20 has an electronic component 4 such as a surface acoustic wave filter mounted on the bottom surface of the cavity 21, and the electronic component 4 is connected via a bonding wire 32. Connected to the circuit element pattern 3. On the surface of the laminated ceramic substrate 20, a lid 5 is provided so as to cover the cavity 21, thereby forming a packaged laminated ceramic component 1.
- an electronic component 4 such as a surface acoustic wave filter mounted on the bottom surface of the cavity 21, and the electronic component 4 is connected via a bonding wire 32.
- a lid 5 is provided so as to cover the cavity 21, thereby forming a packaged laminated ceramic component 1.
- the laminated ceramic substrate 20 is manufactured by the steps shown in FIG. First, as shown in FIG. 10 (a), a green sheet 25 made of a ceramic mixed material is prepared. Next, as shown in FIG. 2B, through holes 22 for cavities, through holes for via holes, and through holes 23 for side electrodes are formed in necessary portions of the green sheet 25.
- a plurality of green sheets 25 obtained in this manner are provided with through holes for the throat holes and side holes.
- the conductive material 24 is filled in the through hole 23 for the surface electrode.
- a circuit element pattern 30 is printed on the surfaces of the plurality of green sheets 25 with the conductive material 24.
- the green sheets 25 thus obtained are laminated and integrated by hot pressing or the like to produce a green sheet laminate 26.
- the green sheet laminate 26 is divided into cavities 21 to obtain a plurality of green sheet laminate chips 27. Then, as shown in FIG. 3G, each green sheet laminate chip 27 is baked to obtain a laminated ceramic substrate 20.
- Fig. 1 (a) is a partial top view near a side electrode of a multilayer ceramic substrate according to the present invention
- Fig. 1 (b) is a partial perspective view near a side electrode of the ceramic substrate.
- the side edge electrode layer has a parallel wall substantially parallel to and not exposed to the side surface of the multilayer ceramic substrate, and a vertical wall substantially perpendicular to the side surface of the multilayer ceramic substrate, and a length of the parallel wall.
- La has a relationship of La> Lb with the depth Lb of the parallel wall from the side of the laminated ceramic substrate.
- the parallel wall and the vertical wall are connected by an R-shaped corner portion 46.
- the corner part 46 is not easily filled with the conductive material 24, so that the conductive material 24 is likely to be insufficiently filled. For this reason, the adhesion area between the side wall of the conductive material of the side electrode 47 of the laminated ceramic substrate 20 and the ceramic side wall after firing is reduced, and the peel strength of the side electrode 47 from the ceramic portion is reduced. Further, if it is attempted to completely fill the corner portion 46 with the conductive material 24, the management of the filling process becomes complicated and the productivity is reduced. Therefore, it is preferable to provide the corner portion 46 with an R shape as in this embodiment. It is sufficient for the range of R to be larger than 0.02 mm.
- FIG. 2 (a) is a partial top view near a side electrode of a multilayer ceramic substrate according to a second embodiment of the present invention
- FIG. 2 (b) is a view near a side electrode of the ceramic substrate. It is a partial perspective view.
- the side electrode on the side surface of the multilayer ceramic substrate 20 has no side electrode layer on the uppermost layer, but has a side edge electrode layer from the layer immediately below the uppermost layer to the lowermost layer.
- a structure in which the side electrode layer is not provided in the uppermost layer is shown.
- the present invention is not limited to the uppermost layer, and a structure in which the side electrode layer is not provided in another layer may be used.
- the side edge electrode layer is not provided in a plurality of layers It is good also as a structure.
- the firing is performed after the green sheet laminate 26 is divided.
- the same effect can be obtained by dividing the green sheet laminate 26 after firing.
- the filling of the conductive material 24 into the through hole for via hole and the through hole 23 for the side electrode, and the printing of the circuit element pattern 30 with the conductive material 24 on the surface of the green sheet 25 may be performed simultaneously.
- the occurrence rate of the disconnection of the side electrode caused by lamination displacement can be reduced, and therefore, the disconnection failure of the laminated ceramic substrate can be reduced and the production yield of the laminated ceramic substrate can be improved.
Abstract
Description
Claims
Priority Applications (1)
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US10/541,494 US7440256B2 (en) | 2003-10-06 | 2004-09-27 | Laminated ceramic substrate and manufacturing method therefor |
Applications Claiming Priority (2)
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JP2003347435A JP4131694B2 (ja) | 2003-10-06 | 2003-10-06 | 積層セラミックス基板及びその製造方法 |
JP2003-347435 | 2003-10-06 |
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WO2005034592A1 true WO2005034592A1 (ja) | 2005-04-14 |
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PCT/JP2004/014551 WO2005034592A1 (ja) | 2003-10-06 | 2004-09-27 | 積層セラミックス基板及びその製造方法 |
Country Status (5)
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US (1) | US7440256B2 (ja) |
JP (1) | JP4131694B2 (ja) |
KR (1) | KR20070000967A (ja) |
CN (1) | CN100542376C (ja) |
WO (1) | WO2005034592A1 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
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US9713258B2 (en) * | 2006-04-27 | 2017-07-18 | International Business Machines Corporation | Integrated circuit chip packaging |
US8232621B2 (en) * | 2006-07-28 | 2012-07-31 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US7838976B2 (en) * | 2006-07-28 | 2010-11-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a semiconductor chip enclosed by a body structure and a base |
US7714535B2 (en) | 2006-07-28 | 2010-05-11 | Semiconductor Energy Laboratory Co., Ltd. | Power storage device |
WO2009028289A1 (ja) | 2007-08-29 | 2009-03-05 | Murata Manufacturing Co., Ltd. | セラミック多層基板 |
DE102010018499A1 (de) * | 2010-04-22 | 2011-10-27 | Schweizer Electronic Ag | Leiterplatte mit Hohlraum |
KR102520038B1 (ko) | 2018-01-10 | 2023-04-12 | 삼성전자주식회사 | 가스 센서 패키지 및 이를 포함하는 센싱 장치 |
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JPH0385793A (ja) * | 1989-08-30 | 1991-04-10 | Murata Mfg Co Ltd | 厚膜配線板の外部端子形成方法 |
JPH0983090A (ja) * | 1995-09-19 | 1997-03-28 | Murata Mfg Co Ltd | 電子部品 |
JP2003017851A (ja) * | 2001-06-29 | 2003-01-17 | Murata Mfg Co Ltd | 多層セラミック基板の製造方法 |
JP2003258398A (ja) * | 2002-02-27 | 2003-09-12 | Murata Mfg Co Ltd | 積層セラミック電子部品およびその製造方法 |
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US3612963A (en) * | 1970-03-11 | 1971-10-12 | Union Carbide Corp | Multilayer ceramic capacitor and process |
US4821007A (en) * | 1987-02-06 | 1989-04-11 | Tektronix, Inc. | Strip line circuit component and method of manufacture |
US4907128A (en) * | 1988-12-15 | 1990-03-06 | Grumman Aerospace Corporation | Chip to multilevel circuit board bonding |
US5140745A (en) * | 1990-07-23 | 1992-08-25 | Mckenzie Jr Joseph A | Method for forming traces on side edges of printed circuit boards and devices formed thereby |
JPH04221888A (ja) * | 1990-12-21 | 1992-08-12 | Matsushita Electric Ind Co Ltd | セラミック配線基板とその製造方法 |
US5258648A (en) * | 1991-06-27 | 1993-11-02 | Motorola, Inc. | Composite flip chip semiconductor device with an interposer having test contacts formed along its periphery |
JP3223199B2 (ja) * | 1991-10-25 | 2001-10-29 | ティーディーケイ株式会社 | 多層セラミック部品の製造方法および多層セラミック部品 |
US5621193A (en) * | 1995-05-23 | 1997-04-15 | Northrop Grumman Corporation | Ceramic edge connect process |
JP3336913B2 (ja) | 1997-06-30 | 2002-10-21 | 株式会社村田製作所 | 電子部品のパッケージ構造 |
US6760227B2 (en) * | 2000-11-02 | 2004-07-06 | Murata Manufacturing Co., Ltd. | Multilayer ceramic electronic component and manufacturing method thereof |
JP2002232135A (ja) | 2001-01-30 | 2002-08-16 | Matsushita Electric Ind Co Ltd | 積層用両面回路基板とその製造方法及びそれを用いた多層プリント配線板 |
US6958899B2 (en) * | 2003-03-20 | 2005-10-25 | Tdk Corporation | Electronic device |
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2003
- 2003-10-06 JP JP2003347435A patent/JP4131694B2/ja not_active Expired - Fee Related
-
2004
- 2004-09-27 CN CNB2004800014600A patent/CN100542376C/zh not_active Expired - Fee Related
- 2004-09-27 WO PCT/JP2004/014551 patent/WO2005034592A1/ja active Application Filing
- 2004-09-27 US US10/541,494 patent/US7440256B2/en not_active Expired - Fee Related
- 2004-09-27 KR KR1020057017438A patent/KR20070000967A/ko active IP Right Grant
Patent Citations (4)
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JPH0385793A (ja) * | 1989-08-30 | 1991-04-10 | Murata Mfg Co Ltd | 厚膜配線板の外部端子形成方法 |
JPH0983090A (ja) * | 1995-09-19 | 1997-03-28 | Murata Mfg Co Ltd | 電子部品 |
JP2003017851A (ja) * | 2001-06-29 | 2003-01-17 | Murata Mfg Co Ltd | 多層セラミック基板の製造方法 |
JP2003258398A (ja) * | 2002-02-27 | 2003-09-12 | Murata Mfg Co Ltd | 積層セラミック電子部品およびその製造方法 |
Also Published As
Publication number | Publication date |
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KR20070000967A (ko) | 2007-01-03 |
JP4131694B2 (ja) | 2008-08-13 |
US7440256B2 (en) | 2008-10-21 |
CN100542376C (zh) | 2009-09-16 |
US20060115637A1 (en) | 2006-06-01 |
CN1717962A (zh) | 2006-01-04 |
JP2005116707A (ja) | 2005-04-28 |
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