WO2005038927A1

WO2005038927A1 - Trench insulated gate field effect transistor

Info

Publication number: WO2005038927A1
Application number: PCT/IB2004/052061
Authority: WO
Inventors: Raymond J. Grover; Steven T. Peake
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2003-10-17
Filing date: 2004-10-12
Publication date: 2005-04-28
Also published as: GB0324313D0

Abstract

A trench insulated gate field effect transistor having a reduced mesa width between adjacent trenches to obtain desirable performance characteristics, in particular low Rds(on), with a suitable channel length and/or gate trench depth. The transistor has a nominal one-dimensional maximum lateral depletion width w9 at the gate-body region interface at the threshold voltage, a nominal vertical depletion length wa in the body region (4) adjacent to the drain region (2) when the design breakdown voltage Vbdss is applied between source and drain, and a nominal vertical depletion length was in the body region (4) adjacent to the source region (14), wherein the channel length I is given by I<2(wa+ was) and the mesa width w is given by w<1 0(w9).

Description

DESCRIPTION

TRENCH INSULATED GATE FIELD EFFECT TRANSISTOR The invention relates to a trench insulated gate field effect transistor, and in particular a vertical trench field effect transistor.

A cell of a conventional low-voltage trench MOSFET is shown in Figure

1. An n-type layer 2 forms the drain, and a p-type layer 4 over the drain 2 forms the body. A plurality of insulated gates 6 are formed in vertical trenches

8 extending from a first major surface 12 through the body 4 into the drain 2. The gates have insulating gate dielectric 8 on their sidewalls and base and are filled with a n-type doped polysilicon gate conductor 10. Source regions 14 are implanted into the body at the first major surface adjacent to the gates 6, the source regions being doped n+. Source, gate and drain contacts 16, 18, 20 are formed connecting to the source 14, gate conductor 10 and drain 2 respectively. The source contact 16 also makes contact with the body 4 at the first major surface 12. In the fojlowing, the depth of the trench will be denoted d, the width of the body 4 between adjacent trenches, i.e. the mesa width, will be denoted w, and the length of the channel in the body region will be denoted I. Also, note that the term "vertical" will be used in this specification to refer to a direction perpendicular to the first major surface 12 and "lateral" for a direction parallel with the first major surface 12. A plurality of cells are formed laterally across the first major surface 12 to make up the conventional trench field effect transistor. In use, voltage is applied to the gate 6 through gate contact 18 to turn the transistor on and to control current passing from the source 14 to the drain

2. The voltage necessary to just turn the transistor on is known as the threshold voltage V_t. When the transistor is off, the region of the channel between source 14 and drain 2 is depleted, and the transistor does not conduct. Figure 2 shows the depletion region in this state, and in particular the edge of the depletion region is depicted as 21. It will be seen that the body 4 and drain 2 are depleted in the region of the body-drain interface 22, the body 4 is depleted adjacent to the gates and there is also a thin depletion layer in the source. A central region 24 of the body remains un-depleted. In this off state, a voltage can be supported between source and drain.

As the voltage between source and drain rises past a voltage known as the breakdown voltage, a current starts to flow between source and drain. The breakdown voltage is defined as the voltage when a particular current starts to flow - conveniently a current of 1μA is used. The sizes of the various layers will be described with reference to a particular example. In the example, the source doping will be 5x10¹⁹cm^"3 n- type, the body doping 1x10¹⁷cm^"3 p-type, the drain doping 1x10¹⁶ cm^"3 n-type, the gate dielectric is oxide 40nm thick, and the gate material polysilicon doped n-type at 1x10¹⁹ cm ^"3. The example will be assumed to be for a 30V breakdown device. In this device the threshold voltage V_t may be calculated to be 1.90 V. The maximum width of the depletion region w_g adjacent to the gate occurs at this voltage, as well as higher voltages, and in the example results in a width w_g of 0.10 μm. The depletion width at the junction between drain and body varies with the voltage across the junction. At 30V, the width w_a in the body is 0.19μm and the width W_d in the drain 1.90μm. The depletion in the body at the source-body interface w_as is 0.11 μm. Thus the total depletion length in the body in this case is w_a + w_as = 0.30μm. Short channel effects can occur in such devices, in particular when the channel length I is insufficiently thick. In general, the channel length I must be much thicker than the total depletion in the body, here w_a + w_as = 0.30μm. Thus, in general the channel length I needs to be greater than double this value, giving a minimum channel length I of 0.60 μm in the example. As will be appreciated, the body doping may be chosen for suitable values of minimum channel length I and mesa width w. However, there are tradeoffs. In general, the chosen body doping is a compromise between the threshold voltage and short channel effects. For a low body doping the depletion region in the body w_a is large, requiring a long channel length I, and this in turn results in a device with an undesirable high on-resistance Rds(on). To shorten the channel and reduce the on-resistance, the doping can be increased, but this also has the undesirable effect of increasing the threshold voltage and requiring more drive to be applied to the gate to turn the device on. Another constraint applies to doping levels in short channel devices. A form of punch-through known as short channel effect applies if too low a doping is used. There is a general desire to optimise devices, in particular the specific Rds(on) value, i.e. the on-resistance for unit area of device. Past attempts to optimise devices generally aim for a geometry that increases channel density. For example, US-A-6,413,822 (Williams et al) describes various geometries with this goal in mind. Another example is the particular geometry is the stripe geometry described by Sodhi et al, "High-Density Ultra-Low Rdson 30 Volt N-channel Trench FETs for DC-DC Converter Applications", Proceedings of the 1999 International Symposium on Power Semiconductor Devices, pages 307-310. In this approach, the source contacts are spaced away from the cells, which are arranged in stripes alternating with gate trenches. Devices using this principle are described in US-A-6,476,443 (Kinzer), from which it appears that the channel length I should be 1.1-1.2 μm and the mesa width at least 0.6 μm. Thus, these devices appear to follow the conventional design rules.

The inventors have realised that by reducing the width of the mesas it is possible to obtain devices that still function with desirable characteristics, in particular low Rds(on), with a suitable channel length and/or trench depth. Thus, in a first aspect of the inventbn, there is provided an insulated gate field effect transistor, having a predetermined design breakdown voltage Vbdss and design threshold voltage V_t and having opposed first and second major surfaces, comprising: a drain region of first conductivity type; a body region of second conductivity type opposite the first conductivity type over the drain region; source regions of first conductivity type extending into the body region from the first major surface, defining a vertical channel part of the body region of having a channel length I between the source region and the drain region; a plurality of insulated gate trenches spaced laterally across the first major surface extending vertically through the body region into the drain region, the insulated gate trenches defining semiconductor mesa regions of width w therebetween; a nominal one-dimensional maximum lateral depletion width w_g at the gate-body region interface at the threshold voltage; a nominal vertical depletion length w_a in the body region adjacent to the drain region when the design breakdown voltage Vbdss is applied between source and drain; and a nominal vertical depletion length w^ in the body region adjacent to the source region, wherein the channel length I is given by l<2(w_a + w_as) and the mesa width w is given by w < 10 (w_g). As will be shown below, the inventors have calculated that better breakdown performance is achieved with short channel lengths by ensuring that the width w of the mesa is suitable, and thus by having a mesa width within the range claimed the channel length can be reduced between conventionally obtained values. Thus, the invention does not simply require making smaller devices than previously, but making smaller devices having width and length values that would on previous understanding not be considered suitable. In particularly preferred embodiments, the trench extends at least 0.4 μm into the drain region. Thus, if the source region is 0.2 μm deep, and then channel length I 0.38 μm, for example, the trench should be at least 0.4+0.2+0.38=0.98μm deep. It is interesting to note that in the context of wider devices, US-A-6,476,443 teaches that the maximum extension into the drain region should be 0.25 μm. Calculations show that a particularly beneficial range of widths for reducing Rds (on) whilst maintaining breakdown voltage is from 2w_g to 10w_g, especially up to 5w_g. In this range of widths, the breakdown voltage of relatively short channel devices is significantly higher than it would be for a wider mesa. The value w_g may convienently be calculated using |2f,ε₀Φ(/«v) 4ε₄e_βΦ w (max): J-P qN_A y qN_A where ΦF_P is the fermi level for the p-type body given by

where N_a is the body dopant concentration; Nι is the intrinsic carrier concentration; q is the electronic charge; k is Boltzman's constant; T is the temperature; and ε_sε₀ is the permittivity of silicon. kT/q has a constant of value 0.0259V at room temperature. The value w of the total depletion width of a plane junction with doping of NA and No and a reverse voltage of V_r applied is given by

where N_A is the doping concentration in the p-type layer, N_D is the doping concentration in the n-type layer, Φ, = |Φ^|+|Φ^,| the sum of the Fermi levels on each side, Φ_P is given as above and ΦN is given by the same equation with ND substituting for NA; and VR is the applied voltage. The individual values of w_a and w_as can be obtained from charge balance and give w_a = W(N /(NA+ND)) with NA the doping of the body and N_D the doping of the drain, and w is calculated from the formula above with these values, and w_as = W(ND (NA+ND)) with NA the doping of the body and ND the doping of the source (not the drain), and w is calculated from the formula above with these different values. Note that since the body is shorted to the source the value of w needs to be calculated with VR equal to zero. These values of w_g, w_a and w_as are nominal one-dimensional calculated values but they make a useful size indication against which the useful size range of the device can be measured. Calculations show that particularly good results are obtained when the channel length I is given by (w_a + w_as) < I < 1.5 (w_a + w_as). In embodiments, the body doping may be in the range 0.5 to 8 x 10¹⁷ cm^"3 , the channel length I is in the range 0.2 to 0.6 μm, and the mesa width 0.1 to 0.5 μm.

For a better understanding of the invention, embodiments will now be described, purely by way of example, with reference to the accompanying drawings, in which: Figure 1 shows a prior art trench MOSFET; Figure 2 illustrates various widths and lengths used in the discussion both of the prior art and of devices according to the invention; Figure 3 illustrates a first embodiment of a trench MOSFET according to the invention; Figure 4 illustrates a graph of the breakdown voltage measured at a current of 1μA for a number of different channel lengths and widths; Figure 5 shows the specific on-resistance as a function of mesa width; Figure 6 shows the breakdown voltage as a function of mesa width; Figure 7 shows the threshold voltage as a function of mesa width; Figure 8 shows the specific on-resistance as a function of channel length; Figure 9 shows the threshold voltage as a function of channel length; and Figure 10 shows the breakdown voltage as a function of channel length. Referring to Figure 3, the general form of the device according to the first embodiment of the invention is similar to that of prior art devices. Thus, as in the prior art device of Figure 1 , an n-type layer 2 forms the drain, and a p- type layer 4 over the drain 2 forms the body. A plurality of insulated gates 6 are formed in trenches 8 extending from a first major surface 12 through the body 4 into the drain 2. The gates have insulating gate dielectric 8 on their sidewalls and base and are filled with a n-type doped polysilicon gate conductor 10. Source regions 14 are implanted into the body at the first major surface adjacent to the gates 6, the source regions being doped n+. Source, gate and drain contacts 16, 18, 20 are formed connecting to the source 14, gate conductor 10 and drain 2 respectively. The source contact 16 also makes contact with the body 4 at the first major surface 12. In this example, the source doping is 5x10¹⁹cm^"3 n-type, the body doping 1x10¹⁷cm^"3 p -type, the drain doping 1x10¹⁶ cm ^"3 n -type, the gate dielectric is oxide 40nm thick, and the gate material polysilicon doped n-type at 1x10¹⁹ cm^"3. The design breakdown voltage is 30V. However, it should not be thought that these values are limiting. The skilled person will be aware that a variety of different materials, doping levels etc. may be used for the various components. The value of the depletion in the body varies as a function of source- drain voltage. For example, using simple (one-dimensional calculations), the value of the depletion in the body adjacent to the drain w_a is given by 0.03 μm at 0V, O.Oδμm at 5V, 0.11 μm at 10V and 0.19 μm at 30V. The depletion in the body adjacent to the source is largely caused by the source-body junction potential of 0.98V. This results in a body depletion length at the source of w_as = 0.11 μm. The total depletion length is therefore (0.11 + 0.19) = 0.30μm. Thus, in this case conventional thinking would require the channel length to be more than twice this length, i.e. O.δμm. In the specific example according to the invention, the specific dimensions are different to those of the prior art using conventional thinking. The mesa width w of the device of Figure 3 is only 0.38 μm, the depth of the source diffusion 0.2μm, and the channel length 0.36 μm, around half the normal minimum length. The trench depth is 1.05 μm, leading to a trench extension into the drift region of 0.49 μm. Figure 4 shows the breakdown voltage measured for a current of 1 μA as the channel length and mesa width. Note that for wide devices of width 1 μm, the breakdown voltage in short channel devices is much lower than for long channel devices (13V at 0.31 μm channel length against 34V at 0.72μm channel length). This is the expected result, and is the reason for choosing longer channel lengths. Figure 4 also clearly shows an improvement in breakdown voltage for short channels at lower mesa widths. Thus, for a channel length of 0.38μm, the breakdown voltage of a 0.4μm wide device is about 27.5V, much better than the 17 V for a 1 μm wide mesa device. Some effect is seen for longer channel devices, though the effect is less. Thus, by selecting both a lower mesa width, preferably in the range 2 to 4 w_g and a lower channel length, less than double (w_a + w_as), at the same time, unexpectedly useful results may be achived. The inventors consider that the effect may be due, at least in part, to a reduced surface field (RESURF) effect caused by the gate trenches extending into the body layer. Alternatively, or additionally, the effect may be caused by a reduction in short channel effects caused by the gate having more control over the body in a narrow device. Instead of using the effect to reduce Rds(on) by reducing the channel length, it is also possible to use the improved breakdown characteristics by increasing the drain doping. This again reduces Rds(on), though it will not be possible to reduce the channel length as much, all other things being equal. The skilled person will appreciate that the approach can be modified to deal with different doping situations. The threshold voltage can be calculated using the approximate equation: The value w_g may conveniently be calculated using w ₍ι_mm_aa_χx₎= i l²^ —Φ - ^v) - ₌= ^4g*^£°^φ^ ^Λ< qN_A i qN_A where the constants are as above. As above, w_a and w_as can be obtained from charge balance and give w_a = W(ND/(NA+N_D)) with N_A the doping of the body and No the doping of the drain, and w is calculated from the formula above with these values, and w_as = W(ND (NA+ND)) with NA the doping of the body and No the doping of the source (not the drain), and w is calculated from the formula above with these different values. Note that since the body is shorted to the source the value of w needs to be calculated with VR equal to zero. Thus, for a given required threshold voltage, these equation give w_g (max), w_a and w_as. By increasing the dopant concentration it is possible to reduce the value of w_g and hence reduce the size of the device for which the value of the mesa width m is given by m < 10 w_g, preferably 2w_g < m < 8w_g. For example, for a 1x10¹³ cm^"2 body dose the minimum mesa width m might be 0.38 μm and the minimum mesa length 0.4 μm. If smaller values of width and length are required the body doping could be increased, say to 4x10¹³ cm^"2. The inventors have carried out further simulations to determine the best parameter ranges. The simulations were carried out for four body doses, specifically 1.0x10¹³ cm^"2' 1.5x10¹³ cm^'2, 1.8x10¹³ cm^'2 and 3.0x10¹³ cm^"2 and for a variety of mesa widths and channel lengths. First, the channel length was fixed at 0.38 μm and the mesa width varied from 0.25 μm to 1 μm. The calculated specific on-resistance is shown in Figure 5, the breakdown voltage in Figure 6 and the threshold voltage in Figure 7. Note that the threshold voltage is higher for higher body does but the breakdown voltage is also higher. The results show a good compromise body dose to be 1.8x10¹³ cm^"2. The breakdown voltage does not fall off as badly as for the 1x10¹³ cm^"2 body dose used in the example of Figure 4. The channel length was then varied for a 1.8x10¹³ cm^"2 body dose and a mesa width of 0.3 μm. Figure 8 shows the specific on-resistance, Figure 9 the threshold voltage and Figure 10 the breakdown voltage. The resistance decreases linearly as expected - the resistance change is not that big because for these parameter values the resistance is dominated by the resistance in the epilayer and the substrate. The threshold voltage falls with decreasing channel length but still within the specification for a 0.24 μm channel length. The breakdown voltage is stable for channel lengths above 0.3 μm but falls below this value. The simulations therefore suggest a cell structure with a 0.3 μ m mesa width and a 0.3 μm channel length with a body dose of 1.8x10¹³ cm^"2. Compared with a calculated nominal value of w_g for this case of 0.044 μm, this mesa width corresponds to about 8w_g. This is a good result. It was unexpected to the inventors that the effects of narrow mesa width are so prominent up to such a large multiple of w_g. The inventors note however that the value of w_g is essentially a one-dimensional value and the inventors hypothesize that the fact that the calculations were carried out for essentially square mesas in which the length corresponds to the width allows depletion from all sides of the mesa thus enhancing the effect. From reading the present disclosure, other variations and modifications will be apparent to persons skilled in the art. Such variations and modifications may involve equivalent and other features which are already known in the design, manufacture and use of semiconductor devices and which may be used in addition to or instead of features described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of disclosure also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to any such features and/or combinations of such features during the prosecution of the present application or of any further applications derived therefrom.

Claims

1. An insulated gate field effect transistor, having a predetermined design breakdown voltage Vbdss and design threshold voltage Vt and having opposed first and second major surfaces (12), comprising: a drain region (2) of first conductivity type; a body region (4) of second conductivity type opposite the first conductivity type over the drain region; a source region (14) of first conductivity type extending into the body region (4) from the first major surface (12), defining a vertical channel part of the body region of having a channel length I between the source region and the drain region; a plurality of insulated gate trenches (8) spaced laterally across the first major surface (12) extending vertically through the body region (4) into the drain region (2), the insulated gate trenches (8) defining semiconductor mesa regions of width w therebetween; a nominal one-dimensional maximum lateral depletion width w_g at the gate-body region interface; a nominal vertical depletion length w_a in the body region (4) adjacent to the drain region (2) when the design breakdown voltage Vbdss is applied between source and drain; and a nominal vertical depletion length w_as in the body region (4) adjacent to the source region (14), wherein the channel length I is given by l<2(w_a + w_as) and the mesa width w is given by w < 10 (w_g).

2. An insulated gate transistor according to claim 1 , wherein the trenches (8) extend at least 0.4 μm into the drain region.

3. An insulated gate transistor according to claim 1 or 2, wherein the mesa width w is in the range 2w_g to 8w_g inclusive.

4. An insulated gate transistor according to any preceding claim, wherein the nominal depletion width w_g is given by

where ΦFP is the fermi level for the p-type body given by

where N_a is the body dopant concentration; Nj is the intrinsic carrier concentration; q is the electronic charge; k is Boltzman's constant; T is the temperature; and ε_sε₀ is the permittivity of silicon.

5. An insulated gate transistor according to any preceding claim, wherein the channel length I is given by (w_a + w_as) < I < 1.5 (w_a + w_as).

6. An insulated gate transistor according to any preceding claim, wherein the body doping is in the range 0.5 to 10 x 10¹⁷ cm^"3 , the channel length I is in the range 0.2 to 0.6 μm, and the mesa width is in the range 0.1 to 0.5 μm.

7. An insulated gate transistor according to claim 6 wherein the body doping is in the range 4 to 8 x 10¹⁷ cm^"3, the channel length is in the range 0.35 to 0.45 μm, and the mesa width is in the range 0.25 to 0.35 μm.

8. An insulated gate field effect transistor, having a predetermined design breakdown voltage Vbdss and design threshold voltage V_t and having opposed first and second major surfaces (12), comprising: a drain region (2) of first conductivity type; a body region (4) of second conductivity type opposite the first conductivity type over the drain region; a source region (14) of first conductivity type extending into the body region (4) from the first major surface (12), defining a vertical channel part of the body region of having a channel length I between the source region and the drain region; and a plurality of insulated gate trenches (8) spaced laterally across the first major surface (12) extending vertically through the body region (4) into the drain region (2), the insulated gate trenches defining semiconductor mesa regions of width w therebetween, wherein the doping concentration in the body region is in the range 0.5 to 10 x 10¹⁷ cm^"3 , the channel length I is in the range 0.2 to 0.6 μm, and the mesa width w is in the range 0.1 to 0.5 μm.

9. An insulated gate transistor according to claim 6 wherein the doping concentration in the body region is in the range 4 to 8 x 10¹⁷ cm^"3, the channel length is in the range 0.35 to 0.45 μm, and the mesa width is in the range 0.25 to 0.35 μm.