WO2005043601A2 - Apparatus and method for forming compound integrated circuits - Google Patents

Abstract

The present invention provides for modularized circuits (500) and methods of manufacturing both modularized circuits ('master modules') (520, 522, 524, 526) and compound Ics (504). These master modules are designed to minimize waste and to evenly distribute power throughout its structure. Also, a number of master modules (520, 522, 524, 526) and a compound IC (504) composed of a group of these master modules are structured to minimize the effects of mechanically-induced stresses. In one embodiment, a substrate includes master modules (520, 522, 524, 526) distributed over a surface of the substrate, wherein each master module includes, for example, one or more logic circuits, a memory, an input interface and an output interface.

Description

APPARATUS AND METHOD FOR FORMING COMPOUND INTEGRATED CIRCUITS BRIEF DESCRIPTION OF THE INVENTION [0001] The present invention relates to electronic devices and methods of manufacturing such devices. More particularly, the present invention relates to a master module configured to, among other things, distribute power substantially equally over a compound integrated circuit ("IC") composed of such master modules. Exemplary master modules are homogeneous in structure and each provides modularized functionality.

BACKGROUND OF THE INVENTION [0002] Structured application-specific integrated circuit ("ASIC") technology is emerging as an alternative to using standard cell ASICs to create customized ICs. Typically, standard cell ASIC technology requires thirty or more masks to manufacture customized ICs. As such, the cost of manufacturing devices using standard cell ASIC technology is inextricably tied to the investments in tooling (i.e., mask set development). As product life cycles decrease and as more aggressive geometries continue to push mask costs higher, other technologies, such as structured ASIC, are becoming more promising. [0003] FIG. 1 illustrates a masterslice used to form ICs with conventional structured

ASIC techniques. Generally, masterslice 100 is replicated over a base wafer and has a customized top layer of metal for providing connections within and without masterslice 100. Masterslice 100 includes core circuitry composed of logic gates 102 and memory 104. Typically, logic gates 102 are topographically arranged in rows as shown in FIG. 1. Blocks of memory 104 each represent memory sized in accordance with storage requirements of the electronic device. The core circuitry is surrounded by ring circuitry 108, which includes input/output ("I/O") structures 106. These I/O structures 106 have bond pads 107 for connecting bond wires to a package containing a number of masterslices 100. [0004] In practice, masterslices 100 are manufactured as part of a family of masterslices. Each of the differing masterslices 100 of a particular family is distinguished from the other members by a fixed number of I/O bond pads, memory, and logic gates. Thus, each member provides rigid gradations of I/O, memory and logic gates from which a designer can choose. As an example, each member of a masterslice family is distinguishable from other members by its differentiated quantity of logic gates. Consider that a masterslice family contains members having 40,000 gates, 100,000 gates, 250,000 gates, 500,000 gates, 1,100,000 gates, etc. First, if a designer requires 600,000 gates, he or she has only two options: 500,000 or 1,100,000 gates. The former is not sufficient to meet the designer's requirements and the latter is wasteful (and costly). Second, a number of wafers for each of the family members is required for building inventory so as to provide quick turn-around manufacturing of a variety of customized ICs. But when pre-made wafers for producing these families remain idle (e.g., due to low demand), then this leads to a stale inventory of such wafers. [0005] A drawback of the arrangement of circuitry shown for masterslice 100 is that ring circuit 108 includes large power buses for powering I/O drivers within I/O structures 106 as well as a power grid (not shown) extending into the core of masterslice 100. These I/O drivers consume a large percentage of the power supplied to masterslice 100. Consequently, the power density across masterslice 100 as well as the IC composed of a number of masterslices 100 is not evenly distributed. For this reason, masterslice 100 has relatively large thermal gradients extending from the edge (i.e., hotter regions) toward the center (i.e., cooler regions), which typically impairs reliability. Moreover, the power grid typically requires complex routing to provide power from the periphery (e.g., ring circuit 108) to memory 104 and logic gates 102 in the core. [0006] FIG. 2 is a cross-sectional view of a traditional seal ring structure commonly used to manufacture masterslice 100 of FIG. 1. As shown in cross-section 200, seal ring 202 extends from surface 201 of the masterslice to substrate 206. Seal ring 202 is formed to prevent stress cracks from propagating from saw cut region 208 (e.g., demarcated by a saw street) to active logic 214 during and after a saw or dicing operation. [0007] Pad 204 enables signals to be exchanged between active logic 214 and an external source via a bond wire. Pad 204 is usually supported by a structure extending (not shown) to substrate 206 for providing support while a bonding wire is attached to pad 204. For this reason, region 210 does not include active logic. As saw cut region 208 and region 212 together do not support the functionality of the masterslice, masterslice 100 includes excessive amounts of material not contributing to the functionality of masterslice 100. [0008] In view of the foregoing, a master module designed to minimize waste and to evenly distribute power throughout its structure is desirable. Also, there is a need to develop and to adapt a compound IC composed of master modules for minimizing the deleterious effects from mechanical separation of such compound ICs.

SUMMARY OF THE INVENTION [0009] The present invention provides for modularized circuits and methods of manufacturing both modularized circuits and compound ICs. These modularized circuits are referred to herein as master modules and are designed to minimize waste and to evenly distribute power throughout a wafer. Also, each master module and a compound IC composed of a group of these master modules are structured to minimize the effects of mechanically-induced stresses. [0010] hi one embodiment of the invention, a substrate includes master modules distributed over a surface of the substrate, wherein each master module includes one or more logic circuits, a memory, an input interface and an output interface, wherein the functionality of the substrate is determined, for example, by physical connections established between and within the master modules. [0011] In another embodiment, an integrated circuit includes a first seal ring segment surrounding circuitry formed in a lower layer region; and a second seal ring segment surrounding circuitry formed in an upper layer region. As an example, the second seal ring can be vertically and horizontally offset from the first seal ring segment.

BRIEF DESCRIPTION OF THE FIGURES [0012] The invention is more fully appreciated in connection with the following detailed description taken in conjunction with the accompanying drawings, in which: [0013] FIG. 1 is a diagram of a conventional masterslice; [0014] FIG. 2 is a cross-sectional view of a pad and seal ring structure of the conventional masterslice of FIG. 1; [0015] FIG. 3 illustrates an exemplary master module in accordance with a specific embodiment of the present invention; [0016] FIGs. 4A, 4B and 4C show lines of demarcation giving rise to one or more exemplary compound integrated circuits according to a specific embodiment of the present invention; [0017] FIG. 5 represents a portion of a wafer on which an exemplary compound IC is formed, according to a specific embodiment the present invention; [0018] FIG. 6 is a detailed view of a peripheral master module and a master module as well as a pad according to one embodiment the present invention; and [0019] FIG. 7 is a cross-sectional view of an exemplary peripheral master module and master module of FIG. 6, according to an embodiment of the present invention. Like reference numerals refer to corresponding parts throughout the several views of the drawings. DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS [0020] The present invention provides a number of master modules for forming a compound integrated circuit ("IC") as a customized integrated circuit, and methods for manufacturing such master modules and compound ICs. An exemplary master module according to a specific embodiment can include various circuit elements, such as one or more logic circuits, a memory, an input interface and an output interface, and optionally, other like circuit elements. The one or more logic circuits can be configured to include any number of logic gates in accordance with the present invention. These logic circuits are building blocks for forming computation circuits, such as arithmetic logic units ("ALUs"), or the like. The input and output interfaces can each include one or more single inputs or outputs for communicating signals (e.g., power, data, or otherwise) among one or more master modules and external to the compound IC composed of master modules. According to the present invention, the master module is designed to couple with other master modules to form a compound IC having a combined functionality based on the interconnections of each of the constituent master modules and a size based on the number of those constituent master modules. These interconnections are programmable and are established in one or more upper fabrication layers. [0021] FIG. 3 depicts an exemplary master module according to one embodiment of the present invention. In this example, master module 300 can include memory 304, inputs 306, outputs 308, optional electrostatic discharge ("ESD") circuit 310 and logic gates 312. Master module 300 also includes an isolation ring 302. Memory 304 can include RAM (e.g., SRAM) and/or ROM memory and can be programmed as single-port, dual-port, first- in-first-out, or as other like memory configurations. Inputs 306 and outputs 308 can include one or more simple inputs and output, respectively, such as CMOS, TTL, or the like. Inputs 306 and outputs 308 can be configured to operate jointly to form bi-directional, high-input impedance I/Os. Further, inputs 306 and outputs 308 can also be configured as advanced inputs and outputs to accommodate various functions such as peripheral component interconnect ("PCI"), peripheral component interconnect extended ("PCI-X"), universal serial bus ("USB"), low voltage differential signaling ("LNDS"), and other like I/O functions. [0022] Logic gates 312 can include any number and/or type of logic gates to create various logical functions. For example, logic gates 312 can be configured to include subcircuit elements, such as simple logic gates (e.g., "AND," "OR," "NOR," or similar gates), and/or complex logic gates (e.g., a combinational logic unit composed of multiple simple logical gates to generate an output, such as "Z = (NOT A and NOT B) OR NOT C"). Logic gates 312 can also be configured to include circuits for providing multiplexer, arithmetic (e.g., summing with carry-over), flip-flop functions, and other like logical functions. [0023] In one embodiment, some or all of the above described subcircuit elements could be partially and/or totally pre-formed in one or more lower fabrication layers of master module 300, such as the first four metal layers, excluding any optional layers dedicated as power planes. Further, the formation of one or more upper fabrication layers upon the lower fabrication layers (e.g., an additional two or more metal layers) are used to program the functionality of master module 300, and therefore, can be used couple the subcircuit elements of master module 300 together as well as to other circuitry beyond master module 300, such as another master module. [0024] Master module 300 can also include an optional ESD circuit 310 for minimizing damage caused by electrostatic discharge into one or more I/Os. In some embodiments, master module 300 can also include other circuitry not shown in FIG. 2, such as counter circuits, phase-locked loop (PLL) circuits, divider circuits, and many other suitable circuits. [0025] Although FIG. 3 depicts memory 304, inputs 306, outputs 308, optional ESD circuit 310 and logic gates 312 as having contiguous subcircuit elements to form the specific circuit elements (i.e., FIG. 3 shows all subcircuit elements "lumped" as one circuit element), one ordinarily skilled in the art will appreciate that each of the subcircuit elements making up each circuit element are separable and can be distributed throughout master module 300. For example, memory 304 can be separated into 18k SRAM blocks and distributed throughout master module 300. Likewise, logic gates 312 and its constituent subcircuit elements can be distributed throughout master module 300 to, for example, evenly distribute power dissipation in so much as logic gates 312 (or subcircuit elements thereof) contribute to the power density. [0026] In another embodiment, the relative sizes of memory 304, inputs 306, outputs 308, optional ESD circuit 310 and logic gates 312 of FIG. 3 indicate the relative amounts of each within master module 300. As an example, memory 304 (or its subcircuit elements) can be an lδkbit SRAM block having an area 0.3mm x 0.4mm, inputs 306 can include 4 inputs each having an area 0.1mm x 0.1mm, outputs 308 can include 8 inputs each having an area 0.1mm x 0.1mm, and logic gates 312 can include 9,600 gates. One ordinarily skilled in the art will appreciate that these amounts are exemplary and that other proportions, amounts, etc. are within the spirit and the scope of the present invention. These amounts, however, are representative of the fine granularity of functionality with which to define how a compound ICs is to be produced. By adjusting the size of the compound IC over a range of relatively small increments of functionality, a resulting IC can be manufactured with minimal wastage. [0027] Exemplary isolation ring 302 of FIG. 3 surrounds master module 300 to shield memory 304, inputs 306, outputs 308, optional ESD circuit 310 and logic gates 312 from fractures propagating in, for example, a dielectric supporting one or more metal layers. In one embodiment, isolation ring 302 is formed in the lower layer of master module 300 as a bulwark of relatively closely-space vias formed in one or more lower, metal layers. An ordinarily skilled artisan will appreciate that isolation ring 302 can be manufactured, in some other embodiments, by using known seal ring formation techniques. In some embodiments, isolation ring 302 need not completely encircle the subcircuit elements of master module 300 and thus can be formed by two or more segments to produce isolation

[0028] FIGs. 4A, 4B and 4C show lines of demarcation giving rise to one or more exemplary compound ICs, each being formed from a collection of master modules according to a specific embodiment of the present invention. Each of these figures represents but a portion of a wafer from which compound ICs are produced. In one embodiment, each line 410 of FIGs. 4A, 4B and 4C defines a saw street (or any other line for dicing) for separating compound ICs. These figures depict how relatively small, medium, and large sized compound ICs are produced and separated. In one embodiment, two rows and two columns of master modules 450 define the periphery of each compound IC as well as the saw streets, or scribe lines for example, to guide compound IC separation. In particular, a row outlines either a top or a bottom of a compound IC, and a column outlines either a left or a right side of the compound IC. [0029] The overall functionality of a compound IC is determined, for example, by configuring (i.e., programming) connections among master modules. These connections are formed in one or more upper layers, such as one or more metal layers, to couple modularized functions (i.e., logic, memory, etc.) embodied in one or more lower layers. Hence, a designer can leverage the use of pre-formed base wafers containing modularized functions to quickly produce compound ICs by selecting an appropriate number of master modules and interconnecting those master modules to obtain the desired overall functionality. [0030] In FIG. 4A, each small chip 420 is a compound IC formed from, and includes, a 3 x 3 array of 9 contiguous master modules 450, where each master module 450 can be coupled to other master modules in small chip 420. Further, each master module 450 of small chip 420 has interconnections among its various circuit and subcircuit elements, such as described in connection with FIG. 3. Lines 410 are used to separate a specific "small chip" 420 from other "small chips" 420. Although not shown, isolation rings of master modules 450 located adjacent to lines 410 shield their respective circuits from propagating cracks. Similarly, an upper seal ring shields at least a portion of each compound IC 420 from cracks propagating in any of the one or more upper fabrication layers. In one embodiment, one or more segments of the upper seal ring can extend out tlirough the periphery or the boundaries of compound IC 420 and over a row and/or a column of master modules designated as part of a line 410. [0031] Similar to FIG. 4A, FIG. 4B and FIG. 4C show the separation of medium- sized chip 430 and large-sized chip 440, respectively, from other master modules 450. FIG. 4B shows an 8 x 8 array of 64 contiguous master modules 450 in compound IC 430 ("Mid Chip"). FIG. 4C depicts a 12 x 12 array of 144 contiguous master modules 450 in compound IC 440 ("Large Chip"). Although isolation rings of each master module 450 in FIGs. 4B and 4C are similar in structure (i.e., size) and functionality, an upper seal ring is formed to sufficiently shield the respective compound ICs 430 and 450 from cracks propagating in one or more of the upper fabrication layers. [0032] According to the present invention, compound IC technology facilitates the manufacture of ICs by using an appropriate base wafer containing a "sea of master modules" to form a die as a compound IC rather than using a select wafer (i.e., a member from a masterslice family) to the exclusion of other wafers, as is required by conventionally structured ASICs. Thus, the inherent nature of producing families of masterslices in conventionally structured ASIC technology limits the availability of base wafers. Among other things, the ability to size compound ICs (as defined by lines 410) and the ability to program interconnections in the one or more upper fabrications of the compound IC obviates the need to produce and to inventory families of masterslices. [0033] FIG. 5 represents a portion of a wafer on which an exemplary compound IC is formed, according to a specific embodiment. In this example, wafer portion 500 includes a compound IC 504 composed of a 2 x 2 array of master modules. In particular, compound IC 504 includes master modules 520, 522, 524 and 526, where each master module can be programmed by one or more upper fabrication (e.g., metal) layers to form interconnections among circuit elements within the master module, as well as interconnections among other master modules and external entities. [0034] As shown in FIG. 5, each of master modules 520, 522, 524 and 526 is surrounded by an isolation ring 506. Further, compound IC 504 includes an upper seal ring 502. In combination, upper seal ring 502 and isolation rings 506 are structured to minimize crack propagation through to the subcircuit elements of the master modules. Exemplary upper seal ring 502 is formed, as shown in FIG. 5, to surround compound IC 504 and to extend over and/or upon one or more master modules located at and/or near the periphery of compound IC 504, such as peripheral master module 530. In some embodiments, upper seal ring 502 need not completely encircle the group of master modules and thus can be formed by two or more segments to produce upper seal ring 502. [0035] Bond pad or like interconnections, such as pad 508, provide for interconnections external to compound IC 504. Although FIG. 5 shows pad 508 as one pad associated with master module 524, multiple pads 508 can be coupled to master module 524 as well as to the other master modules. In some cases, multiple pads 508 are distributed around all of the edges of compound IC 504. Alternatively, one or more pads 508 can be distributed over the surface of compound IC 504 to accommodate various external connections, such as in a flip chip configuration, a stacked die configuration (e.g., to mate with an analog chip), or the like. [0036] In one embodiment, one or more pads 508, and their respective pad support structures, are formed over certain master modules that are part of one or more saw streets 550. For example, peripheral master module 530 is part of a saw street, and although it will be sawed through (and rendered inoperative), it also includes pad 508 and its pad structure. [0037] FIG. 6 is a detailed view of peripheral master module 630 and master module

624, which includes pad 508 of FIG. 5. Letters A, B, C, D, E, and F are associated with the same letters in FIGs. 5, 6 and 7, and are used to describe respective features in a plan view (as shown in FIGs. 5 and 6) and a cross-sectional view (as shown in FIG. 7) of an exemplary compound IC. In FIG. 6, pad 608 is located on peripheral master module 630 and is coupled (e.g., by way of a metal trace) to master module 624 in compound IC 604. [0038] Also shown in FIG. 6, isolation rings 607 and 606 are associated with peripheral master module 630 and master module 624, respectively. In this instance, upper seal ring 602 is shown to overlap isolation ring 607. In one embodiment, the overlap by upper seal ring 602 defines an interconnect area 660 upon which any one or more pad 608 can reside. In a specific embodiment, pad 608 and its structure are formed over inoperative circuitry of peripheral master module 630. [0039] FIG. 7 is a cross-sectional view of peripheral master module 630 and master module 624 of FIG. 6, according to an embodiment of the present invention. In this instance, compound IC 704 is fabricated with six lower layers (i.e., metal layers Ml tlirough M6) and three upper layers (i.e., custom metal layers Cl through C3), where the upper layers program the interconnections for compound IC 704. In one embodiment, material 760 interstitial to the layers is a low-K dielectric and substrate 706 is a silicon substrate. But in other embodiments, either material 760 or substrate 706, or both, can be composed of any other type of suitable material or substrate. [0040] According to one embodiment of the present invention, isolation rings 706 and 707 combine to provide a lower seal ring in, for example, layers Ml through M6. Isolation rings 706 and 707 are isolation rings 606 and 607, respectively, of the plan view of FIG. 6 and combine to form lower seal ring 703. Note that lower seal ring 703 need not be composed of contiguous segments, but rather can be composed of separate segments of two or more isolation rings. Further, letters E and F denote lines of demarcation that distinguish peripheral master module 730 from master module 724, respectively, as similarly shown in FIG. 6. Further to this example, upper seal ring 702 is formed in the one or more upper layers and is located over and within peripheral master module 730. Upper seal ring 702 is shown delimited by letters A and B similar to those same letters in FIG. 6. Thus, upper seal ring 702 and lower seal ring 703 (i.e., isolation rings 707 and 706) together minimize crack propagations emanating from mechanically-induced stresses at saw cut region 710, which is located within peripheral master module 730. To some extent, inoperative logic of peripheral master module 730 also provides a barrier to prevent the propagation of fractures from reaching the operative logic of master module 724. In a specific embodiment, lower seal ring 703 and upper seal ring 702 need not be formed 90 degrees with the substrate and can each be formed by staggering constituent vias horizontally in each subsequent fabrication layer. [0041] Also shown in FIG. 7, pad 708 and its underlying pad support 732 are formed vertically over inoperative logic of peripheral master module 730. hi one case, upper seal ring 702 is formed at least a particular distance from one edge of inoperative logic so as to provide an interconnect area on the surface of peripheral master module 730. This area enables pad 708 to be placed beyond the usual seal ring barrier, which is typically defined as the location of lower seal ring 703. In one embodiment, the inoperative logic provides at least some support for pad support 732. Pad support 732 can be manufactured with more or fewer layers shown in FIG. 7. [0042] The various methods for manufacturing compound ICs described herein can be governed by software processes, for example, as part of a design tool kit. Generally, such a tool kit includes computer readable medium that enables electronic device designers to design, develop and manufacture ICs in accordance with the present invention. [0043] An embodiment of the present invention relates to a computer storage product with a computer-readable medium having computer code thereon for performing various computer-implemented operations. The media and computer code may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well known and available to those having skill in the computer software arts. Examples of computer-readable media include, but are not limited to: magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CD-ROMs and holographic devices; magneto-optical media such as floptical disks; and hardware devices that are specially configured to store and execute program code, such as application-specific integrated circuits ("ASICs"), programmable logic devices ("PLDs") and ROM and RAM devices. Examples of computer code include machine code, such as produced by a compiler, and files containing higher-level code that are executed by a computer using an interpreter. For example, an embodiment of the invention may be implemented using Java, C++, or other object-oriented programming language and development tools. Another embodiment of the invention may be implemented in hardwired circuitry in place of, or in combination with, machine-executable software instructions. [0044] The foregoing description, for purposes of explanation, used specific nomenclature to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that specific details are not required in order to practice the invention. Thus, the foregoing descriptions of specific embodiments of the invention are presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed; obviously, many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, they thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the following claims and their equivalents define the scope of the invention.

Claims

In the claims:

1. A substrate comprising: master modules distributed over a surface of said substrate, wherein each master module includes one or more logic circuits, an input interface and an output interface, wherein the functionality of said substrate is determined by physical connections established between and within said master modules.

2. The substrate of claim 1 operative to consume substantially uniform power over said surface of said substrate.

3. The substrate of claim 2 wherein operative master modules of said master modules consume substantially the same amount of power.

4. The substrate of claim 1 wherein at least two or more contiguous master modules define a line for separating said substrate.

5. The substrate of claim 1 wherein the functionality of said substrate is defined by the size of an integrated circuit formed from a subset of said master modules.

6. The substrate of claim 1 wherein each said master module further includes a memory.

7. An integrated circuit, comprising: a first seal ring segment surrounding circuitry formed in a lower layer region; and a second seal ring segment surrounding circuitry formed in an upper layer region, wherein said second seal ring is vertically and horizontally offset from said first seal ring segment.

8. The integrated circuit of claim 7 wherein said circuitry formed in said lower and said upper layer regions collectively form a compound integrated circuit.

9. The integrated circuit of claim 7 further comprising a pad formed in said upper layer region, wherein said pad is horizontally positioned between said first seal ring segment and said second seal ring segment.

10. The integrated circuit of claim 9 wherein said integrated circuit is adjacent circuitry positioned vertically and horizontally between said first seal ring segment and said second seal ring segment.

11. The integrated circuit of claim 10 wherein said circuitry is formed in another integrated circuit.

12. The integrated circuit of claim 11 wherein said another integrated circuit is part of a line of separation such that said circuitry is rendered inoperative upon separation.

13. The integrated circuit of claim 12 wherein said inoperative circuitry reduces structural defects due to mechanically-induced stress.

14. The integrated circuit of claim 9 wherein said pad is supported by a pad support.

15. The integrated circuit of claim 14 wherein said pad support comprises vias positioned between custom metal layer segments.

16. A method comprising: forming a plurality of circuits in a lower layer region, each of said plurality of circuits having a substantially similar structure; defining the functionality of a compound integrated circuit; and sizing said compound integrated circuit to provide said defined functionality.

17. The method of claim 16 further comprising forming a circuit in an upper layer region based on said size of said compound integrated circuit.

18. The method of claim 17 further comprising forming an isolating ring segment in said lower layer region for each of said plurality of circuits, wherein one or more segments of each of said isolating rings adjacent to the periphery of said size compound integrated circuit forms a lower layer seal ring.

19. The method of claim 18 further comprising forming a seal ring segment in said upper layer region for said compound integrated circuit, wherein said seal ring in said upper layer region has a segment that is vertically and horizontally offset from said lower layer seal ring.

20. The method of claim 17 wherein said circuit formed in said upper layer region is formed over a first subset of said plurality of circuits, wherein a second subset of said plurality of circuits define a line for separating said compound integrated circuit.

21. A substrate comprising: master modules distributed over a surface of said substrate, wherein each master module includes a memory, an input interface and an output interface, wherein the functionality of said substrate is determined by physical connections established between and within said master modules.

22. The substrate of claim 21 wherein said each master module further includes one or more logic circuits.

23. The substrate of claim 21 operative to consume substantially uniform power over said surface of said substrate.

24. The substrate of claim 23 wherein operative master modules of said master modules consume substantially the same amount of power.

25. The substrate of claim 21 wherein at least two or more contiguous master modules define a line for separating said substrate.